Program Listing for File xip_ssi.h

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#pragma once

#include "../enums/XIP_SSI_CTRLR0_SPI_FRF.h"
#include "../enums/XIP_SSI_CTRLR0_TMOD.h"
#include "../enums/XIP_SSI_SPI_CTRLR0_INST_L.h"
#include "../enums/XIP_SSI_SPI_CTRLR0_TRANS_TYPE.h"
#include "../ifgen/common.h"

namespace RP2040
{

struct [[gnu::packed]] xip_ssi
{
    /* Constant attributes. */
    static constexpr std::size_t size = 252;
    /* Fields. */
    uint32_t CTRLR0;
    uint32_t CTRLR1;
    uint32_t SSIENR;
    uint32_t MWCR;
    uint32_t SER;
    uint32_t BAUDR;
    uint32_t TXFTLR;
    uint32_t RXFTLR;
    const uint32_t TXFLR = {};
    const uint32_t RXFLR = {};
    const uint32_t SR = {};
    uint32_t IMR;
    const uint32_t ISR = {};
    const uint32_t RISR = {};
    const uint32_t TXOICR =
        {};
    const uint32_t RXOICR =
        {};
    const uint32_t RXUICR =
        {};
    const uint32_t MSTICR =
        {};
    const uint32_t ICR = {};
    uint32_t DMACR;
    uint32_t DMATDLR;
    uint32_t DMARDLR;
    const uint32_t IDR = {};
    const uint32_t SSI_VERSION_ID = {};
    uint32_t DR0;
    static constexpr std::size_t reserved_padding0_length = 35;
    const uint32_t reserved_padding0[reserved_padding0_length] = {};
    uint32_t RX_SAMPLE_DLY;
    uint32_t SPI_CTRLR0;
    uint32_t TXD_DRIVE_EDGE;
    /* Methods. */

    inline uint8_t get_CTRLR0_DFS() volatile
    {
        return (CTRLR0 >> 0u) & 0b1111u;
    }

    inline void set_CTRLR0_DFS(uint8_t value) volatile
    {
        uint32_t curr = CTRLR0;

        curr &= ~(0b1111u << 0u);
        curr |= (value & 0b1111u) << 0u;

        CTRLR0 = curr;
    }

    inline uint8_t get_CTRLR0_FRF() volatile
    {
        return (CTRLR0 >> 4u) & 0b11u;
    }

    inline void set_CTRLR0_FRF(uint8_t value) volatile
    {
        uint32_t curr = CTRLR0;

        curr &= ~(0b11u << 4u);
        curr |= (value & 0b11u) << 4u;

        CTRLR0 = curr;
    }

    inline bool get_CTRLR0_SCPH() volatile
    {
        return CTRLR0 & (1u << 6u);
    }

    inline void set_CTRLR0_SCPH() volatile
    {
        CTRLR0 |= 1u << 6u;
    }

    inline void clear_CTRLR0_SCPH() volatile
    {
        CTRLR0 &= ~(1u << 6u);
    }

    inline void toggle_CTRLR0_SCPH() volatile
    {
        CTRLR0 ^= 1u << 6u;
    }

    inline bool get_CTRLR0_SCPOL() volatile
    {
        return CTRLR0 & (1u << 7u);
    }

    inline void set_CTRLR0_SCPOL() volatile
    {
        CTRLR0 |= 1u << 7u;
    }

    inline void clear_CTRLR0_SCPOL() volatile
    {
        CTRLR0 &= ~(1u << 7u);
    }

    inline void toggle_CTRLR0_SCPOL() volatile
    {
        CTRLR0 ^= 1u << 7u;
    }

    inline XIP_SSI_CTRLR0_TMOD get_CTRLR0_TMOD() volatile
    {
        return XIP_SSI_CTRLR0_TMOD((CTRLR0 >> 8u) & 0b11u);
    }

    inline void set_CTRLR0_TMOD(XIP_SSI_CTRLR0_TMOD value) volatile
    {
        uint32_t curr = CTRLR0;

        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(value) & 0b11u) << 8u;

        CTRLR0 = curr;
    }

    inline bool get_CTRLR0_SLV_OE() volatile
    {
        return CTRLR0 & (1u << 10u);
    }

    inline void set_CTRLR0_SLV_OE() volatile
    {
        CTRLR0 |= 1u << 10u;
    }

    inline void clear_CTRLR0_SLV_OE() volatile
    {
        CTRLR0 &= ~(1u << 10u);
    }

    inline void toggle_CTRLR0_SLV_OE() volatile
    {
        CTRLR0 ^= 1u << 10u;
    }

    inline bool get_CTRLR0_SRL() volatile
    {
        return CTRLR0 & (1u << 11u);
    }

    inline void set_CTRLR0_SRL() volatile
    {
        CTRLR0 |= 1u << 11u;
    }

    inline void clear_CTRLR0_SRL() volatile
    {
        CTRLR0 &= ~(1u << 11u);
    }

    inline void toggle_CTRLR0_SRL() volatile
    {
        CTRLR0 ^= 1u << 11u;
    }

    inline uint8_t get_CTRLR0_CFS() volatile
    {
        return (CTRLR0 >> 12u) & 0b1111u;
    }

    inline void set_CTRLR0_CFS(uint8_t value) volatile
    {
        uint32_t curr = CTRLR0;

        curr &= ~(0b1111u << 12u);
        curr |= (value & 0b1111u) << 12u;

        CTRLR0 = curr;
    }

    inline uint8_t get_CTRLR0_DFS_32() volatile
    {
        return (CTRLR0 >> 16u) & 0b11111u;
    }

    inline void set_CTRLR0_DFS_32(uint8_t value) volatile
    {
        uint32_t curr = CTRLR0;

        curr &= ~(0b11111u << 16u);
        curr |= (value & 0b11111u) << 16u;

        CTRLR0 = curr;
    }

    inline XIP_SSI_CTRLR0_SPI_FRF get_CTRLR0_SPI_FRF() volatile
    {
        return XIP_SSI_CTRLR0_SPI_FRF((CTRLR0 >> 21u) & 0b11u);
    }

    inline void set_CTRLR0_SPI_FRF(XIP_SSI_CTRLR0_SPI_FRF value) volatile
    {
        uint32_t curr = CTRLR0;

        curr &= ~(0b11u << 21u);
        curr |= (std::to_underlying(value) & 0b11u) << 21u;

        CTRLR0 = curr;
    }

    inline bool get_CTRLR0_SSTE() volatile
    {
        return CTRLR0 & (1u << 24u);
    }

    inline void set_CTRLR0_SSTE() volatile
    {
        CTRLR0 |= 1u << 24u;
    }

    inline void clear_CTRLR0_SSTE() volatile
    {
        CTRLR0 &= ~(1u << 24u);
    }

    inline void toggle_CTRLR0_SSTE() volatile
    {
        CTRLR0 ^= 1u << 24u;
    }

    inline void get_CTRLR0(uint8_t &DFS, uint8_t &FRF, bool &SCPH, bool &SCPOL,
                           XIP_SSI_CTRLR0_TMOD &TMOD, bool &SLV_OE, bool &SRL,
                           uint8_t &CFS, uint8_t &DFS_32,
                           XIP_SSI_CTRLR0_SPI_FRF &SPI_FRF,
                           bool &SSTE) volatile
    {
        uint32_t curr = CTRLR0;

        DFS = (curr >> 0u) & 0b1111u;
        FRF = (curr >> 4u) & 0b11u;
        SCPH = curr & (1u << 6u);
        SCPOL = curr & (1u << 7u);
        TMOD = XIP_SSI_CTRLR0_TMOD((curr >> 8u) & 0b11u);
        SLV_OE = curr & (1u << 10u);
        SRL = curr & (1u << 11u);
        CFS = (curr >> 12u) & 0b1111u;
        DFS_32 = (curr >> 16u) & 0b11111u;
        SPI_FRF = XIP_SSI_CTRLR0_SPI_FRF((curr >> 21u) & 0b11u);
        SSTE = curr & (1u << 24u);
    }

    inline void set_CTRLR0(uint8_t DFS, uint8_t FRF, bool SCPH, bool SCPOL,
                           XIP_SSI_CTRLR0_TMOD TMOD, bool SLV_OE, bool SRL,
                           uint8_t CFS, uint8_t DFS_32,
                           XIP_SSI_CTRLR0_SPI_FRF SPI_FRF, bool SSTE) volatile
    {
        uint32_t curr = CTRLR0;

        curr &= ~(0b1111u << 0u);
        curr |= (DFS & 0b1111u) << 0u;
        curr &= ~(0b11u << 4u);
        curr |= (FRF & 0b11u) << 4u;
        curr &= ~(0b1u << 6u);
        curr |= (SCPH & 0b1u) << 6u;
        curr &= ~(0b1u << 7u);
        curr |= (SCPOL & 0b1u) << 7u;
        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(TMOD) & 0b11u) << 8u;
        curr &= ~(0b1u << 10u);
        curr |= (SLV_OE & 0b1u) << 10u;
        curr &= ~(0b1u << 11u);
        curr |= (SRL & 0b1u) << 11u;
        curr &= ~(0b1111u << 12u);
        curr |= (CFS & 0b1111u) << 12u;
        curr &= ~(0b11111u << 16u);
        curr |= (DFS_32 & 0b11111u) << 16u;
        curr &= ~(0b11u << 21u);
        curr |= (std::to_underlying(SPI_FRF) & 0b11u) << 21u;
        curr &= ~(0b1u << 24u);
        curr |= (SSTE & 0b1u) << 24u;

        CTRLR0 = curr;
    }

    inline uint16_t get_CTRLR1_NDF() volatile
    {
        return (CTRLR1 >> 0u) & 0b1111111111111111u;
    }

    inline void set_CTRLR1_NDF(uint16_t value) volatile
    {
        uint32_t curr = CTRLR1;

        curr &= ~(0b1111111111111111u << 0u);
        curr |= (value & 0b1111111111111111u) << 0u;

        CTRLR1 = curr;
    }

    inline bool get_SSIENR_SSI_EN() volatile
    {
        return SSIENR & (1u << 0u);
    }

    inline void set_SSIENR_SSI_EN() volatile
    {
        SSIENR |= 1u << 0u;
    }

    inline void clear_SSIENR_SSI_EN() volatile
    {
        SSIENR &= ~(1u << 0u);
    }

    inline void toggle_SSIENR_SSI_EN() volatile
    {
        SSIENR ^= 1u << 0u;
    }

    inline bool get_MWCR_MWMOD() volatile
    {
        return MWCR & (1u << 0u);
    }

    inline void set_MWCR_MWMOD() volatile
    {
        MWCR |= 1u << 0u;
    }

    inline void clear_MWCR_MWMOD() volatile
    {
        MWCR &= ~(1u << 0u);
    }

    inline void toggle_MWCR_MWMOD() volatile
    {
        MWCR ^= 1u << 0u;
    }

    inline bool get_MWCR_MDD() volatile
    {
        return MWCR & (1u << 1u);
    }

    inline void set_MWCR_MDD() volatile
    {
        MWCR |= 1u << 1u;
    }

    inline void clear_MWCR_MDD() volatile
    {
        MWCR &= ~(1u << 1u);
    }

    inline void toggle_MWCR_MDD() volatile
    {
        MWCR ^= 1u << 1u;
    }

    inline bool get_MWCR_MHS() volatile
    {
        return MWCR & (1u << 2u);
    }

    inline void set_MWCR_MHS() volatile
    {
        MWCR |= 1u << 2u;
    }

    inline void clear_MWCR_MHS() volatile
    {
        MWCR &= ~(1u << 2u);
    }

    inline void toggle_MWCR_MHS() volatile
    {
        MWCR ^= 1u << 2u;
    }

    inline void get_MWCR(bool &MWMOD, bool &MDD, bool &MHS) volatile
    {
        uint32_t curr = MWCR;

        MWMOD = curr & (1u << 0u);
        MDD = curr & (1u << 1u);
        MHS = curr & (1u << 2u);
    }

    inline void set_MWCR(bool MWMOD, bool MDD, bool MHS) volatile
    {
        uint32_t curr = MWCR;

        curr &= ~(0b1u << 0u);
        curr |= (MWMOD & 0b1u) << 0u;
        curr &= ~(0b1u << 1u);
        curr |= (MDD & 0b1u) << 1u;
        curr &= ~(0b1u << 2u);
        curr |= (MHS & 0b1u) << 2u;

        MWCR = curr;
    }

    inline bool get_SER_SER() volatile
    {
        return SER & (1u << 0u);
    }

    inline void set_SER_SER() volatile
    {
        SER |= 1u << 0u;
    }

    inline void clear_SER_SER() volatile
    {
        SER &= ~(1u << 0u);
    }

    inline void toggle_SER_SER() volatile
    {
        SER ^= 1u << 0u;
    }

    inline uint16_t get_BAUDR_SCKDV() volatile
    {
        return (BAUDR >> 0u) & 0b1111111111111111u;
    }

    inline void set_BAUDR_SCKDV(uint16_t value) volatile
    {
        uint32_t curr = BAUDR;

        curr &= ~(0b1111111111111111u << 0u);
        curr |= (value & 0b1111111111111111u) << 0u;

        BAUDR = curr;
    }

    inline uint8_t get_TXFTLR_TFT() volatile
    {
        return (TXFTLR >> 0u) & 0b11111111u;
    }

    inline void set_TXFTLR_TFT(uint8_t value) volatile
    {
        uint32_t curr = TXFTLR;

        curr &= ~(0b11111111u << 0u);
        curr |= (value & 0b11111111u) << 0u;

        TXFTLR = curr;
    }

    inline uint8_t get_RXFTLR_RFT() volatile
    {
        return (RXFTLR >> 0u) & 0b11111111u;
    }

    inline void set_RXFTLR_RFT(uint8_t value) volatile
    {
        uint32_t curr = RXFTLR;

        curr &= ~(0b11111111u << 0u);
        curr |= (value & 0b11111111u) << 0u;

        RXFTLR = curr;
    }

    inline uint8_t get_TXFLR_TFTFL() volatile
    {
        return (TXFLR >> 0u) & 0b11111111u;
    }

    inline uint8_t get_RXFLR_RXTFL() volatile
    {
        return (RXFLR >> 0u) & 0b11111111u;
    }

    inline bool get_SR_BUSY() volatile
    {
        return SR & (1u << 0u);
    }

    inline bool get_SR_TFNF() volatile
    {
        return SR & (1u << 1u);
    }

    inline bool get_SR_TFE() volatile
    {
        return SR & (1u << 2u);
    }

    inline bool get_SR_RFNE() volatile
    {
        return SR & (1u << 3u);
    }

    inline bool get_SR_RFF() volatile
    {
        return SR & (1u << 4u);
    }

    inline bool get_SR_TXE() volatile
    {
        return SR & (1u << 5u);
    }

    inline bool get_SR_DCOL() volatile
    {
        return SR & (1u << 6u);
    }

    inline void get_SR(bool &BUSY, bool &TFNF, bool &TFE, bool &RFNE,
                       bool &RFF, bool &TXE, bool &DCOL) volatile
    {
        uint32_t curr = SR;

        BUSY = curr & (1u << 0u);
        TFNF = curr & (1u << 1u);
        TFE = curr & (1u << 2u);
        RFNE = curr & (1u << 3u);
        RFF = curr & (1u << 4u);
        TXE = curr & (1u << 5u);
        DCOL = curr & (1u << 6u);
    }

    inline bool get_IMR_TXEIM() volatile
    {
        return IMR & (1u << 0u);
    }

    inline void set_IMR_TXEIM() volatile
    {
        IMR |= 1u << 0u;
    }

    inline void clear_IMR_TXEIM() volatile
    {
        IMR &= ~(1u << 0u);
    }

    inline void toggle_IMR_TXEIM() volatile
    {
        IMR ^= 1u << 0u;
    }

    inline bool get_IMR_TXOIM() volatile
    {
        return IMR & (1u << 1u);
    }

    inline void set_IMR_TXOIM() volatile
    {
        IMR |= 1u << 1u;
    }

    inline void clear_IMR_TXOIM() volatile
    {
        IMR &= ~(1u << 1u);
    }

    inline void toggle_IMR_TXOIM() volatile
    {
        IMR ^= 1u << 1u;
    }

    inline bool get_IMR_RXUIM() volatile
    {
        return IMR & (1u << 2u);
    }

    inline void set_IMR_RXUIM() volatile
    {
        IMR |= 1u << 2u;
    }

    inline void clear_IMR_RXUIM() volatile
    {
        IMR &= ~(1u << 2u);
    }

    inline void toggle_IMR_RXUIM() volatile
    {
        IMR ^= 1u << 2u;
    }

    inline bool get_IMR_RXOIM() volatile
    {
        return IMR & (1u << 3u);
    }

    inline void set_IMR_RXOIM() volatile
    {
        IMR |= 1u << 3u;
    }

    inline void clear_IMR_RXOIM() volatile
    {
        IMR &= ~(1u << 3u);
    }

    inline void toggle_IMR_RXOIM() volatile
    {
        IMR ^= 1u << 3u;
    }

    inline bool get_IMR_RXFIM() volatile
    {
        return IMR & (1u << 4u);
    }

    inline void set_IMR_RXFIM() volatile
    {
        IMR |= 1u << 4u;
    }

    inline void clear_IMR_RXFIM() volatile
    {
        IMR &= ~(1u << 4u);
    }

    inline void toggle_IMR_RXFIM() volatile
    {
        IMR ^= 1u << 4u;
    }

    inline bool get_IMR_MSTIM() volatile
    {
        return IMR & (1u << 5u);
    }

    inline void set_IMR_MSTIM() volatile
    {
        IMR |= 1u << 5u;
    }

    inline void clear_IMR_MSTIM() volatile
    {
        IMR &= ~(1u << 5u);
    }

    inline void toggle_IMR_MSTIM() volatile
    {
        IMR ^= 1u << 5u;
    }

    inline void get_IMR(bool &TXEIM, bool &TXOIM, bool &RXUIM, bool &RXOIM,
                        bool &RXFIM, bool &MSTIM) volatile
    {
        uint32_t curr = IMR;

        TXEIM = curr & (1u << 0u);
        TXOIM = curr & (1u << 1u);
        RXUIM = curr & (1u << 2u);
        RXOIM = curr & (1u << 3u);
        RXFIM = curr & (1u << 4u);
        MSTIM = curr & (1u << 5u);
    }

    inline void set_IMR(bool TXEIM, bool TXOIM, bool RXUIM, bool RXOIM,
                        bool RXFIM, bool MSTIM) volatile
    {
        uint32_t curr = IMR;

        curr &= ~(0b1u << 0u);
        curr |= (TXEIM & 0b1u) << 0u;
        curr &= ~(0b1u << 1u);
        curr |= (TXOIM & 0b1u) << 1u;
        curr &= ~(0b1u << 2u);
        curr |= (RXUIM & 0b1u) << 2u;
        curr &= ~(0b1u << 3u);
        curr |= (RXOIM & 0b1u) << 3u;
        curr &= ~(0b1u << 4u);
        curr |= (RXFIM & 0b1u) << 4u;
        curr &= ~(0b1u << 5u);
        curr |= (MSTIM & 0b1u) << 5u;

        IMR = curr;
    }

    inline bool get_ISR_TXEIS() volatile
    {
        return ISR & (1u << 0u);
    }

    inline bool get_ISR_TXOIS() volatile
    {
        return ISR & (1u << 1u);
    }

    inline bool get_ISR_RXUIS() volatile
    {
        return ISR & (1u << 2u);
    }

    inline bool get_ISR_RXOIS() volatile
    {
        return ISR & (1u << 3u);
    }

    inline bool get_ISR_RXFIS() volatile
    {
        return ISR & (1u << 4u);
    }

    inline bool get_ISR_MSTIS() volatile
    {
        return ISR & (1u << 5u);
    }

    inline void get_ISR(bool &TXEIS, bool &TXOIS, bool &RXUIS, bool &RXOIS,
                        bool &RXFIS, bool &MSTIS) volatile
    {
        uint32_t curr = ISR;

        TXEIS = curr & (1u << 0u);
        TXOIS = curr & (1u << 1u);
        RXUIS = curr & (1u << 2u);
        RXOIS = curr & (1u << 3u);
        RXFIS = curr & (1u << 4u);
        MSTIS = curr & (1u << 5u);
    }

    inline bool get_RISR_TXEIR() volatile
    {
        return RISR & (1u << 0u);
    }

    inline bool get_RISR_TXOIR() volatile
    {
        return RISR & (1u << 1u);
    }

    inline bool get_RISR_RXUIR() volatile
    {
        return RISR & (1u << 2u);
    }

    inline bool get_RISR_RXOIR() volatile
    {
        return RISR & (1u << 3u);
    }

    inline bool get_RISR_RXFIR() volatile
    {
        return RISR & (1u << 4u);
    }

    inline bool get_RISR_MSTIR() volatile
    {
        return RISR & (1u << 5u);
    }

    inline void get_RISR(bool &TXEIR, bool &TXOIR, bool &RXUIR, bool &RXOIR,
                         bool &RXFIR, bool &MSTIR) volatile
    {
        uint32_t curr = RISR;

        TXEIR = curr & (1u << 0u);
        TXOIR = curr & (1u << 1u);
        RXUIR = curr & (1u << 2u);
        RXOIR = curr & (1u << 3u);
        RXFIR = curr & (1u << 4u);
        MSTIR = curr & (1u << 5u);
    }

    inline bool get_TXOICR_TXOICR() volatile
    {
        return TXOICR & (1u << 0u);
    }

    inline bool get_RXOICR_RXOICR() volatile
    {
        return RXOICR & (1u << 0u);
    }

    inline bool get_RXUICR_RXUICR() volatile
    {
        return RXUICR & (1u << 0u);
    }

    inline bool get_MSTICR_MSTICR() volatile
    {
        return MSTICR & (1u << 0u);
    }

    inline bool get_ICR_ICR() volatile
    {
        return ICR & (1u << 0u);
    }

    inline bool get_DMACR_RDMAE() volatile
    {
        return DMACR & (1u << 0u);
    }

    inline void set_DMACR_RDMAE() volatile
    {
        DMACR |= 1u << 0u;
    }

    inline void clear_DMACR_RDMAE() volatile
    {
        DMACR &= ~(1u << 0u);
    }

    inline void toggle_DMACR_RDMAE() volatile
    {
        DMACR ^= 1u << 0u;
    }

    inline bool get_DMACR_TDMAE() volatile
    {
        return DMACR & (1u << 1u);
    }

    inline void set_DMACR_TDMAE() volatile
    {
        DMACR |= 1u << 1u;
    }

    inline void clear_DMACR_TDMAE() volatile
    {
        DMACR &= ~(1u << 1u);
    }

    inline void toggle_DMACR_TDMAE() volatile
    {
        DMACR ^= 1u << 1u;
    }

    inline void get_DMACR(bool &RDMAE, bool &TDMAE) volatile
    {
        uint32_t curr = DMACR;

        RDMAE = curr & (1u << 0u);
        TDMAE = curr & (1u << 1u);
    }

    inline void set_DMACR(bool RDMAE, bool TDMAE) volatile
    {
        uint32_t curr = DMACR;

        curr &= ~(0b1u << 0u);
        curr |= (RDMAE & 0b1u) << 0u;
        curr &= ~(0b1u << 1u);
        curr |= (TDMAE & 0b1u) << 1u;

        DMACR = curr;
    }

    inline uint8_t get_DMATDLR_DMATDL() volatile
    {
        return (DMATDLR >> 0u) & 0b11111111u;
    }

    inline void set_DMATDLR_DMATDL(uint8_t value) volatile
    {
        uint32_t curr = DMATDLR;

        curr &= ~(0b11111111u << 0u);
        curr |= (value & 0b11111111u) << 0u;

        DMATDLR = curr;
    }

    inline uint8_t get_DMARDLR_DMARDL() volatile
    {
        return (DMARDLR >> 0u) & 0b11111111u;
    }

    inline void set_DMARDLR_DMARDL(uint8_t value) volatile
    {
        uint32_t curr = DMARDLR;

        curr &= ~(0b11111111u << 0u);
        curr |= (value & 0b11111111u) << 0u;

        DMARDLR = curr;
    }

    inline uint32_t get_IDR_IDCODE() volatile
    {
        return (IDR >> 0u) & 0b11111111111111111111111111111111u;
    }

    inline uint32_t get_SSI_VERSION_ID_SSI_COMP_VERSION() volatile
    {
        return (SSI_VERSION_ID >> 0u) & 0b11111111111111111111111111111111u;
    }

    inline uint32_t get_DR0_DR() volatile
    {
        return (DR0 >> 0u) & 0b11111111111111111111111111111111u;
    }

    inline void set_DR0_DR(uint32_t value) volatile
    {
        uint32_t curr = DR0;

        curr &= ~(0b11111111111111111111111111111111u << 0u);
        curr |= (value & 0b11111111111111111111111111111111u) << 0u;

        DR0 = curr;
    }

    inline uint8_t get_RX_SAMPLE_DLY_RSD() volatile
    {
        return (RX_SAMPLE_DLY >> 0u) & 0b11111111u;
    }

    inline void set_RX_SAMPLE_DLY_RSD(uint8_t value) volatile
    {
        uint32_t curr = RX_SAMPLE_DLY;

        curr &= ~(0b11111111u << 0u);
        curr |= (value & 0b11111111u) << 0u;

        RX_SAMPLE_DLY = curr;
    }

    inline XIP_SSI_SPI_CTRLR0_TRANS_TYPE get_SPI_CTRLR0_TRANS_TYPE() volatile
    {
        return XIP_SSI_SPI_CTRLR0_TRANS_TYPE((SPI_CTRLR0 >> 0u) & 0b11u);
    }

    inline void set_SPI_CTRLR0_TRANS_TYPE(
        XIP_SSI_SPI_CTRLR0_TRANS_TYPE value) volatile
    {
        uint32_t curr = SPI_CTRLR0;

        curr &= ~(0b11u << 0u);
        curr |= (std::to_underlying(value) & 0b11u) << 0u;

        SPI_CTRLR0 = curr;
    }

    inline uint8_t get_SPI_CTRLR0_ADDR_L() volatile
    {
        return (SPI_CTRLR0 >> 2u) & 0b1111u;
    }

    inline void set_SPI_CTRLR0_ADDR_L(uint8_t value) volatile
    {
        uint32_t curr = SPI_CTRLR0;

        curr &= ~(0b1111u << 2u);
        curr |= (value & 0b1111u) << 2u;

        SPI_CTRLR0 = curr;
    }

    inline XIP_SSI_SPI_CTRLR0_INST_L get_SPI_CTRLR0_INST_L() volatile
    {
        return XIP_SSI_SPI_CTRLR0_INST_L((SPI_CTRLR0 >> 8u) & 0b11u);
    }

    inline void set_SPI_CTRLR0_INST_L(XIP_SSI_SPI_CTRLR0_INST_L value) volatile
    {
        uint32_t curr = SPI_CTRLR0;

        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(value) & 0b11u) << 8u;

        SPI_CTRLR0 = curr;
    }

    inline uint8_t get_SPI_CTRLR0_WAIT_CYCLES() volatile
    {
        return (SPI_CTRLR0 >> 11u) & 0b11111u;
    }

    inline void set_SPI_CTRLR0_WAIT_CYCLES(uint8_t value) volatile
    {
        uint32_t curr = SPI_CTRLR0;

        curr &= ~(0b11111u << 11u);
        curr |= (value & 0b11111u) << 11u;

        SPI_CTRLR0 = curr;
    }

    inline bool get_SPI_CTRLR0_SPI_DDR_EN() volatile
    {
        return SPI_CTRLR0 & (1u << 16u);
    }

    inline void set_SPI_CTRLR0_SPI_DDR_EN() volatile
    {
        SPI_CTRLR0 |= 1u << 16u;
    }

    inline void clear_SPI_CTRLR0_SPI_DDR_EN() volatile
    {
        SPI_CTRLR0 &= ~(1u << 16u);
    }

    inline void toggle_SPI_CTRLR0_SPI_DDR_EN() volatile
    {
        SPI_CTRLR0 ^= 1u << 16u;
    }

    inline bool get_SPI_CTRLR0_INST_DDR_EN() volatile
    {
        return SPI_CTRLR0 & (1u << 17u);
    }

    inline void set_SPI_CTRLR0_INST_DDR_EN() volatile
    {
        SPI_CTRLR0 |= 1u << 17u;
    }

    inline void clear_SPI_CTRLR0_INST_DDR_EN() volatile
    {
        SPI_CTRLR0 &= ~(1u << 17u);
    }

    inline void toggle_SPI_CTRLR0_INST_DDR_EN() volatile
    {
        SPI_CTRLR0 ^= 1u << 17u;
    }

    inline bool get_SPI_CTRLR0_SPI_RXDS_EN() volatile
    {
        return SPI_CTRLR0 & (1u << 18u);
    }

    inline void set_SPI_CTRLR0_SPI_RXDS_EN() volatile
    {
        SPI_CTRLR0 |= 1u << 18u;
    }

    inline void clear_SPI_CTRLR0_SPI_RXDS_EN() volatile
    {
        SPI_CTRLR0 &= ~(1u << 18u);
    }

    inline void toggle_SPI_CTRLR0_SPI_RXDS_EN() volatile
    {
        SPI_CTRLR0 ^= 1u << 18u;
    }

    inline uint8_t get_SPI_CTRLR0_XIP_CMD() volatile
    {
        return (SPI_CTRLR0 >> 24u) & 0b11111111u;
    }

    inline void set_SPI_CTRLR0_XIP_CMD(uint8_t value) volatile
    {
        uint32_t curr = SPI_CTRLR0;

        curr &= ~(0b11111111u << 24u);
        curr |= (value & 0b11111111u) << 24u;

        SPI_CTRLR0 = curr;
    }

    inline void get_SPI_CTRLR0(XIP_SSI_SPI_CTRLR0_TRANS_TYPE &TRANS_TYPE,
                               uint8_t &ADDR_L,
                               XIP_SSI_SPI_CTRLR0_INST_L &INST_L,
                               uint8_t &WAIT_CYCLES, bool &SPI_DDR_EN,
                               bool &INST_DDR_EN, bool &SPI_RXDS_EN,
                               uint8_t &XIP_CMD) volatile
    {
        uint32_t curr = SPI_CTRLR0;

        TRANS_TYPE = XIP_SSI_SPI_CTRLR0_TRANS_TYPE((curr >> 0u) & 0b11u);
        ADDR_L = (curr >> 2u) & 0b1111u;
        INST_L = XIP_SSI_SPI_CTRLR0_INST_L((curr >> 8u) & 0b11u);
        WAIT_CYCLES = (curr >> 11u) & 0b11111u;
        SPI_DDR_EN = curr & (1u << 16u);
        INST_DDR_EN = curr & (1u << 17u);
        SPI_RXDS_EN = curr & (1u << 18u);
        XIP_CMD = (curr >> 24u) & 0b11111111u;
    }

    inline void set_SPI_CTRLR0(XIP_SSI_SPI_CTRLR0_TRANS_TYPE TRANS_TYPE,
                               uint8_t ADDR_L,
                               XIP_SSI_SPI_CTRLR0_INST_L INST_L,
                               uint8_t WAIT_CYCLES, bool SPI_DDR_EN,
                               bool INST_DDR_EN, bool SPI_RXDS_EN,
                               uint8_t XIP_CMD) volatile
    {
        uint32_t curr = SPI_CTRLR0;

        curr &= ~(0b11u << 0u);
        curr |= (std::to_underlying(TRANS_TYPE) & 0b11u) << 0u;
        curr &= ~(0b1111u << 2u);
        curr |= (ADDR_L & 0b1111u) << 2u;
        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(INST_L) & 0b11u) << 8u;
        curr &= ~(0b11111u << 11u);
        curr |= (WAIT_CYCLES & 0b11111u) << 11u;
        curr &= ~(0b1u << 16u);
        curr |= (SPI_DDR_EN & 0b1u) << 16u;
        curr &= ~(0b1u << 17u);
        curr |= (INST_DDR_EN & 0b1u) << 17u;
        curr &= ~(0b1u << 18u);
        curr |= (SPI_RXDS_EN & 0b1u) << 18u;
        curr &= ~(0b11111111u << 24u);
        curr |= (XIP_CMD & 0b11111111u) << 24u;

        SPI_CTRLR0 = curr;
    }

    inline uint8_t get_TXD_DRIVE_EDGE_TDE() volatile
    {
        return (TXD_DRIVE_EDGE >> 0u) & 0b11111111u;
    }

    inline void set_TXD_DRIVE_EDGE_TDE(uint8_t value) volatile
    {
        uint32_t curr = TXD_DRIVE_EDGE;

        curr &= ~(0b11111111u << 0u);
        curr |= (value & 0b11111111u) << 0u;

        TXD_DRIVE_EDGE = curr;
    }
};

static_assert(sizeof(xip_ssi) == xip_ssi::size);

static volatile xip_ssi *const XIP_SSI =
    reinterpret_cast<xip_ssi *>(0x18000000);

}; // namespace RP2040