Struct ppb#

Defined in File ppb.h

Struct Documentation#

struct ppb#

Public Functions

inline bool get_SYST_CSR_ENABLE() volatile#

Get SYST_CSR’s ENABLE bit.

Enable SysTick counter:

0 = Counter disabled.

1 = Counter enabled.

inline void set_SYST_CSR_ENABLE() volatile#

Set SYST_CSR’s ENABLE bit.

Enable SysTick counter:

0 = Counter disabled.

1 = Counter enabled.

inline void clear_SYST_CSR_ENABLE() volatile#

Clear SYST_CSR’s ENABLE bit.

Enable SysTick counter:

0 = Counter disabled.

1 = Counter enabled.

inline void toggle_SYST_CSR_ENABLE() volatile#

Toggle SYST_CSR’s ENABLE bit.

Enable SysTick counter:

0 = Counter disabled.

1 = Counter enabled.

inline bool get_SYST_CSR_TICKINT() volatile#

Get SYST_CSR’s TICKINT bit.

Enables SysTick exception request:

0 = Counting down to zero does not assert the SysTick exception request.

1 = Counting down to zero to asserts the SysTick exception request.

inline void set_SYST_CSR_TICKINT() volatile#

Set SYST_CSR’s TICKINT bit.

Enables SysTick exception request:

0 = Counting down to zero does not assert the SysTick exception request.

1 = Counting down to zero to asserts the SysTick exception request.

inline void clear_SYST_CSR_TICKINT() volatile#

Clear SYST_CSR’s TICKINT bit.

Enables SysTick exception request:

0 = Counting down to zero does not assert the SysTick exception request.

1 = Counting down to zero to asserts the SysTick exception request.

inline void toggle_SYST_CSR_TICKINT() volatile#

Toggle SYST_CSR’s TICKINT bit.

Enables SysTick exception request:

0 = Counting down to zero does not assert the SysTick exception request.

1 = Counting down to zero to asserts the SysTick exception request.

inline bool get_SYST_CSR_CLKSOURCE() volatile#

Get SYST_CSR’s CLKSOURCE bit.

SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.

Selects the SysTick timer clock source:

0 = External reference clock.

1 = Processor clock.

inline void set_SYST_CSR_CLKSOURCE() volatile#

Set SYST_CSR’s CLKSOURCE bit.

SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.

Selects the SysTick timer clock source:

0 = External reference clock.

1 = Processor clock.

inline void clear_SYST_CSR_CLKSOURCE() volatile#

Clear SYST_CSR’s CLKSOURCE bit.

SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.

Selects the SysTick timer clock source:

0 = External reference clock.

1 = Processor clock.

inline void toggle_SYST_CSR_CLKSOURCE() volatile#

Toggle SYST_CSR’s CLKSOURCE bit.

SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.

Selects the SysTick timer clock source:

0 = External reference clock.

1 = Processor clock.

inline bool get_SYST_CSR_COUNTFLAG() volatile#

Get SYST_CSR’s COUNTFLAG bit.

Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger.

inline void get_SYST_CSR(bool &ENABLE, bool &TICKINT, bool &CLKSOURCE, bool &COUNTFLAG) volatile#

Get all of SYST_CSR’s bit fields.

(read-write) Use the SysTick Control and Status Register to enable the SysTick features.

inline void set_SYST_CSR(bool ENABLE, bool TICKINT, bool CLKSOURCE) volatile#

Set all of SYST_CSR’s bit fields.

(read-write) Use the SysTick Control and Status Register to enable the SysTick features.

inline uint32_t get_SYST_RVR_RELOAD() volatile#

Get SYST_RVR’s RELOAD field.

Value to load into the SysTick Current Value Register when the counter reaches 0.

inline void set_SYST_RVR_RELOAD(uint32_t value) volatile#

Set SYST_RVR’s RELOAD field.

Value to load into the SysTick Current Value Register when the counter reaches 0.

inline uint32_t get_SYST_CVR_CURRENT() volatile#

Get SYST_CVR’s CURRENT field.

Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.

inline void set_SYST_CVR_CURRENT(uint32_t value) volatile#

Set SYST_CVR’s CURRENT field.

inline uint32_t get_SYST_CALIB_TENMS() volatile#

Get SYST_CALIB’s TENMS field.

An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known.

inline bool get_SYST_CALIB_SKEW() volatile#

Get SYST_CALIB’s SKEW bit.

If reads as 1, the calibration value for 10ms is inexact (due to clock frequency).

inline bool get_SYST_CALIB_NOREF() volatile#

Get SYST_CALIB’s NOREF bit.

If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0.

inline void get_SYST_CALIB(uint32_t &TENMS, bool &SKEW, bool &NOREF) volatile#

Get all of SYST_CALIB’s bit fields.

(read-only) Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.

inline uint32_t get_NVIC_ISER_SETENA() volatile#

Get NVIC_ISER’s SETENA field.

Interrupt set-enable bits.

Write:

0 = No effect.

1 = Enable interrupt.

Read:

0 = Interrupt disabled.

1 = Interrupt enabled.

inline void set_NVIC_ISER_SETENA(uint32_t value) volatile#

Set NVIC_ISER’s SETENA field.

Interrupt set-enable bits.

Write:

0 = No effect.

1 = Enable interrupt.

Read:

0 = Interrupt disabled.

1 = Interrupt enabled.

inline uint32_t get_NVIC_ICER_CLRENA() volatile#

Get NVIC_ICER’s CLRENA field.

Interrupt clear-enable bits.

Write:

0 = No effect.

1 = Disable interrupt.

Read:

0 = Interrupt disabled.

1 = Interrupt enabled.

inline void set_NVIC_ICER_CLRENA(uint32_t value) volatile#

Set NVIC_ICER’s CLRENA field.

Interrupt clear-enable bits.

Write:

0 = No effect.

1 = Disable interrupt.

Read:

0 = Interrupt disabled.

1 = Interrupt enabled.

inline uint32_t get_NVIC_ISPR_SETPEND() volatile#

Get NVIC_ISPR’s SETPEND field.

Interrupt set-pending bits.

Write:

0 = No effect.

1 = Changes interrupt state to pending.

Read:

0 = Interrupt is not pending.

1 = Interrupt is pending.

Note: Writing 1 to the NVIC_ISPR bit corresponding to:

An interrupt that is pending has no effect.

A disabled interrupt sets the state of that interrupt to pending.

inline void set_NVIC_ISPR_SETPEND(uint32_t value) volatile#

Set NVIC_ISPR’s SETPEND field.

Interrupt set-pending bits.

Write:

0 = No effect.

1 = Changes interrupt state to pending.

Read:

0 = Interrupt is not pending.

1 = Interrupt is pending.

Note: Writing 1 to the NVIC_ISPR bit corresponding to:

An interrupt that is pending has no effect.

A disabled interrupt sets the state of that interrupt to pending.

inline uint32_t get_NVIC_ICPR_CLRPEND() volatile#

Get NVIC_ICPR’s CLRPEND field.

Interrupt clear-pending bits.

Write:

0 = No effect.

1 = Removes pending state and interrupt.

Read:

0 = Interrupt is not pending.

1 = Interrupt is pending.

inline void set_NVIC_ICPR_CLRPEND(uint32_t value) volatile#

Set NVIC_ICPR’s CLRPEND field.

Interrupt clear-pending bits.

Write:

0 = No effect.

1 = Removes pending state and interrupt.

Read:

0 = Interrupt is not pending.

1 = Interrupt is pending.

inline uint8_t get_NVIC_IPR0_IP_0() volatile#

Get NVIC_IPR0’s IP_0 field.

Priority of interrupt 0

inline void set_NVIC_IPR0_IP_0(uint8_t value) volatile#

Set NVIC_IPR0’s IP_0 field.

Priority of interrupt 0

inline uint8_t get_NVIC_IPR0_IP_1() volatile#

Get NVIC_IPR0’s IP_1 field.

Priority of interrupt 1

inline void set_NVIC_IPR0_IP_1(uint8_t value) volatile#

Set NVIC_IPR0’s IP_1 field.

Priority of interrupt 1

inline uint8_t get_NVIC_IPR0_IP_2() volatile#

Get NVIC_IPR0’s IP_2 field.

Priority of interrupt 2

inline void set_NVIC_IPR0_IP_2(uint8_t value) volatile#

Set NVIC_IPR0’s IP_2 field.

Priority of interrupt 2

inline uint8_t get_NVIC_IPR0_IP_3() volatile#

Get NVIC_IPR0’s IP_3 field.

Priority of interrupt 3

inline void set_NVIC_IPR0_IP_3(uint8_t value) volatile#

Set NVIC_IPR0’s IP_3 field.

Priority of interrupt 3

inline void get_NVIC_IPR0(uint8_t &IP_0, uint8_t &IP_1, uint8_t &IP_2, uint8_t &IP_3) volatile#

Get all of NVIC_IPR0’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.

These registers are only word-accessible

inline void set_NVIC_IPR0(uint8_t IP_0, uint8_t IP_1, uint8_t IP_2, uint8_t IP_3) volatile#

Set all of NVIC_IPR0’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.

These registers are only word-accessible

inline uint8_t get_NVIC_IPR1_IP_4() volatile#

Get NVIC_IPR1’s IP_4 field.

Priority of interrupt 4

inline void set_NVIC_IPR1_IP_4(uint8_t value) volatile#

Set NVIC_IPR1’s IP_4 field.

Priority of interrupt 4

inline uint8_t get_NVIC_IPR1_IP_5() volatile#

Get NVIC_IPR1’s IP_5 field.

Priority of interrupt 5

inline void set_NVIC_IPR1_IP_5(uint8_t value) volatile#

Set NVIC_IPR1’s IP_5 field.

Priority of interrupt 5

inline uint8_t get_NVIC_IPR1_IP_6() volatile#

Get NVIC_IPR1’s IP_6 field.

Priority of interrupt 6

inline void set_NVIC_IPR1_IP_6(uint8_t value) volatile#

Set NVIC_IPR1’s IP_6 field.

Priority of interrupt 6

inline uint8_t get_NVIC_IPR1_IP_7() volatile#

Get NVIC_IPR1’s IP_7 field.

Priority of interrupt 7

inline void set_NVIC_IPR1_IP_7(uint8_t value) volatile#

Set NVIC_IPR1’s IP_7 field.

Priority of interrupt 7

inline void get_NVIC_IPR1(uint8_t &IP_4, uint8_t &IP_5, uint8_t &IP_6, uint8_t &IP_7) volatile#

Get all of NVIC_IPR1’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

inline void set_NVIC_IPR1(uint8_t IP_4, uint8_t IP_5, uint8_t IP_6, uint8_t IP_7) volatile#

Set all of NVIC_IPR1’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

inline uint8_t get_NVIC_IPR2_IP_8() volatile#

Get NVIC_IPR2’s IP_8 field.

Priority of interrupt 8

inline void set_NVIC_IPR2_IP_8(uint8_t value) volatile#

Set NVIC_IPR2’s IP_8 field.

Priority of interrupt 8

inline uint8_t get_NVIC_IPR2_IP_9() volatile#

Get NVIC_IPR2’s IP_9 field.

Priority of interrupt 9

inline void set_NVIC_IPR2_IP_9(uint8_t value) volatile#

Set NVIC_IPR2’s IP_9 field.

Priority of interrupt 9

inline uint8_t get_NVIC_IPR2_IP_10() volatile#

Get NVIC_IPR2’s IP_10 field.

Priority of interrupt 10

inline void set_NVIC_IPR2_IP_10(uint8_t value) volatile#

Set NVIC_IPR2’s IP_10 field.

Priority of interrupt 10

inline uint8_t get_NVIC_IPR2_IP_11() volatile#

Get NVIC_IPR2’s IP_11 field.

Priority of interrupt 11

inline void set_NVIC_IPR2_IP_11(uint8_t value) volatile#

Set NVIC_IPR2’s IP_11 field.

Priority of interrupt 11

inline void get_NVIC_IPR2(uint8_t &IP_8, uint8_t &IP_9, uint8_t &IP_10, uint8_t &IP_11) volatile#

Get all of NVIC_IPR2’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

inline void set_NVIC_IPR2(uint8_t IP_8, uint8_t IP_9, uint8_t IP_10, uint8_t IP_11) volatile#

Set all of NVIC_IPR2’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

inline uint8_t get_NVIC_IPR3_IP_12() volatile#

Get NVIC_IPR3’s IP_12 field.

Priority of interrupt 12

inline void set_NVIC_IPR3_IP_12(uint8_t value) volatile#

Set NVIC_IPR3’s IP_12 field.

Priority of interrupt 12

inline uint8_t get_NVIC_IPR3_IP_13() volatile#

Get NVIC_IPR3’s IP_13 field.

Priority of interrupt 13

inline void set_NVIC_IPR3_IP_13(uint8_t value) volatile#

Set NVIC_IPR3’s IP_13 field.

Priority of interrupt 13

inline uint8_t get_NVIC_IPR3_IP_14() volatile#

Get NVIC_IPR3’s IP_14 field.

Priority of interrupt 14

inline void set_NVIC_IPR3_IP_14(uint8_t value) volatile#

Set NVIC_IPR3’s IP_14 field.

Priority of interrupt 14

inline uint8_t get_NVIC_IPR3_IP_15() volatile#

Get NVIC_IPR3’s IP_15 field.

Priority of interrupt 15

inline void set_NVIC_IPR3_IP_15(uint8_t value) volatile#

Set NVIC_IPR3’s IP_15 field.

Priority of interrupt 15

inline void get_NVIC_IPR3(uint8_t &IP_12, uint8_t &IP_13, uint8_t &IP_14, uint8_t &IP_15) volatile#

Get all of NVIC_IPR3’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

inline void set_NVIC_IPR3(uint8_t IP_12, uint8_t IP_13, uint8_t IP_14, uint8_t IP_15) volatile#

Set all of NVIC_IPR3’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

inline uint8_t get_NVIC_IPR4_IP_16() volatile#

Get NVIC_IPR4’s IP_16 field.

Priority of interrupt 16

inline void set_NVIC_IPR4_IP_16(uint8_t value) volatile#

Set NVIC_IPR4’s IP_16 field.

Priority of interrupt 16

inline uint8_t get_NVIC_IPR4_IP_17() volatile#

Get NVIC_IPR4’s IP_17 field.

Priority of interrupt 17

inline void set_NVIC_IPR4_IP_17(uint8_t value) volatile#

Set NVIC_IPR4’s IP_17 field.

Priority of interrupt 17

inline uint8_t get_NVIC_IPR4_IP_18() volatile#

Get NVIC_IPR4’s IP_18 field.

Priority of interrupt 18

inline void set_NVIC_IPR4_IP_18(uint8_t value) volatile#

Set NVIC_IPR4’s IP_18 field.

Priority of interrupt 18

inline uint8_t get_NVIC_IPR4_IP_19() volatile#

Get NVIC_IPR4’s IP_19 field.

Priority of interrupt 19

inline void set_NVIC_IPR4_IP_19(uint8_t value) volatile#

Set NVIC_IPR4’s IP_19 field.

Priority of interrupt 19

inline void get_NVIC_IPR4(uint8_t &IP_16, uint8_t &IP_17, uint8_t &IP_18, uint8_t &IP_19) volatile#

Get all of NVIC_IPR4’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

inline void set_NVIC_IPR4(uint8_t IP_16, uint8_t IP_17, uint8_t IP_18, uint8_t IP_19) volatile#

Set all of NVIC_IPR4’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

inline uint8_t get_NVIC_IPR5_IP_20() volatile#

Get NVIC_IPR5’s IP_20 field.

Priority of interrupt 20

inline void set_NVIC_IPR5_IP_20(uint8_t value) volatile#

Set NVIC_IPR5’s IP_20 field.

Priority of interrupt 20

inline uint8_t get_NVIC_IPR5_IP_21() volatile#

Get NVIC_IPR5’s IP_21 field.

Priority of interrupt 21

inline void set_NVIC_IPR5_IP_21(uint8_t value) volatile#

Set NVIC_IPR5’s IP_21 field.

Priority of interrupt 21

inline uint8_t get_NVIC_IPR5_IP_22() volatile#

Get NVIC_IPR5’s IP_22 field.

Priority of interrupt 22

inline void set_NVIC_IPR5_IP_22(uint8_t value) volatile#

Set NVIC_IPR5’s IP_22 field.

Priority of interrupt 22

inline uint8_t get_NVIC_IPR5_IP_23() volatile#

Get NVIC_IPR5’s IP_23 field.

Priority of interrupt 23

inline void set_NVIC_IPR5_IP_23(uint8_t value) volatile#

Set NVIC_IPR5’s IP_23 field.

Priority of interrupt 23

inline void get_NVIC_IPR5(uint8_t &IP_20, uint8_t &IP_21, uint8_t &IP_22, uint8_t &IP_23) volatile#

Get all of NVIC_IPR5’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

inline void set_NVIC_IPR5(uint8_t IP_20, uint8_t IP_21, uint8_t IP_22, uint8_t IP_23) volatile#

Set all of NVIC_IPR5’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

inline uint8_t get_NVIC_IPR6_IP_24() volatile#

Get NVIC_IPR6’s IP_24 field.

Priority of interrupt 24

inline void set_NVIC_IPR6_IP_24(uint8_t value) volatile#

Set NVIC_IPR6’s IP_24 field.

Priority of interrupt 24

inline uint8_t get_NVIC_IPR6_IP_25() volatile#

Get NVIC_IPR6’s IP_25 field.

Priority of interrupt 25

inline void set_NVIC_IPR6_IP_25(uint8_t value) volatile#

Set NVIC_IPR6’s IP_25 field.

Priority of interrupt 25

inline uint8_t get_NVIC_IPR6_IP_26() volatile#

Get NVIC_IPR6’s IP_26 field.

Priority of interrupt 26

inline void set_NVIC_IPR6_IP_26(uint8_t value) volatile#

Set NVIC_IPR6’s IP_26 field.

Priority of interrupt 26

inline uint8_t get_NVIC_IPR6_IP_27() volatile#

Get NVIC_IPR6’s IP_27 field.

Priority of interrupt 27

inline void set_NVIC_IPR6_IP_27(uint8_t value) volatile#

Set NVIC_IPR6’s IP_27 field.

Priority of interrupt 27

inline void get_NVIC_IPR6(uint8_t &IP_24, uint8_t &IP_25, uint8_t &IP_26, uint8_t &IP_27) volatile#

Get all of NVIC_IPR6’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

inline void set_NVIC_IPR6(uint8_t IP_24, uint8_t IP_25, uint8_t IP_26, uint8_t IP_27) volatile#

Set all of NVIC_IPR6’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

inline uint8_t get_NVIC_IPR7_IP_28() volatile#

Get NVIC_IPR7’s IP_28 field.

Priority of interrupt 28

inline void set_NVIC_IPR7_IP_28(uint8_t value) volatile#

Set NVIC_IPR7’s IP_28 field.

Priority of interrupt 28

inline uint8_t get_NVIC_IPR7_IP_29() volatile#

Get NVIC_IPR7’s IP_29 field.

Priority of interrupt 29

inline void set_NVIC_IPR7_IP_29(uint8_t value) volatile#

Set NVIC_IPR7’s IP_29 field.

Priority of interrupt 29

inline uint8_t get_NVIC_IPR7_IP_30() volatile#

Get NVIC_IPR7’s IP_30 field.

Priority of interrupt 30

inline void set_NVIC_IPR7_IP_30(uint8_t value) volatile#

Set NVIC_IPR7’s IP_30 field.

Priority of interrupt 30

inline uint8_t get_NVIC_IPR7_IP_31() volatile#

Get NVIC_IPR7’s IP_31 field.

Priority of interrupt 31

inline void set_NVIC_IPR7_IP_31(uint8_t value) volatile#

Set NVIC_IPR7’s IP_31 field.

Priority of interrupt 31

inline void get_NVIC_IPR7(uint8_t &IP_28, uint8_t &IP_29, uint8_t &IP_30, uint8_t &IP_31) volatile#

Get all of NVIC_IPR7’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

inline void set_NVIC_IPR7(uint8_t IP_28, uint8_t IP_29, uint8_t IP_30, uint8_t IP_31) volatile#

Set all of NVIC_IPR7’s bit fields.

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

inline uint8_t get_CPUID_REVISION() volatile#

Get CPUID’s REVISION field.

Minor revision number m in the rnpm revision status:

0x1 = Patch 1.

inline uint16_t get_CPUID_PARTNO() volatile#

Get CPUID’s PARTNO field.

Number of processor within family: 0xC60 = Cortex-M0+

inline uint8_t get_CPUID_ARCHITECTURE() volatile#

Get CPUID’s ARCHITECTURE field.

Constant that defines the architecture of the processor:

0xC = ARMv6-M architecture.

inline uint8_t get_CPUID_VARIANT() volatile#

Get CPUID’s VARIANT field.

Major revision number n in the rnpm revision status:

0x0 = Revision 0.

inline uint8_t get_CPUID_IMPLEMENTER() volatile#

Get CPUID’s IMPLEMENTER field.

Implementor code: 0x41 = ARM

inline void get_CPUID(uint8_t &REVISION, uint16_t &PARTNO, uint8_t &ARCHITECTURE, uint8_t &VARIANT, uint8_t &IMPLEMENTER) volatile#

Get all of CPUID’s bit fields.

(read-only) Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.

inline uint16_t get_ICSR_VECTACTIVE() volatile#

Get ICSR’s VECTACTIVE field.

Active exception number field. Reset clears the VECTACTIVE field.

inline uint16_t get_ICSR_VECTPENDING() volatile#

Get ICSR’s VECTPENDING field.

Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier.

inline bool get_ICSR_ISRPENDING() volatile#

Get ICSR’s ISRPENDING bit.

External interrupt pending flag

inline bool get_ICSR_ISRPREEMPT() volatile#

Get ICSR’s ISRPREEMPT bit.

The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.

inline bool get_ICSR_PENDSTCLR() volatile#

Get ICSR’s PENDSTCLR bit.

SysTick exception clear-pending bit.

Write:

0 = No effect.

1 = Removes the pending state from the SysTick exception.

This bit is WO. On a register read its value is Unknown.

inline void set_ICSR_PENDSTCLR() volatile#

Set ICSR’s PENDSTCLR bit.

SysTick exception clear-pending bit.

Write:

0 = No effect.

1 = Removes the pending state from the SysTick exception.

This bit is WO. On a register read its value is Unknown.

inline void clear_ICSR_PENDSTCLR() volatile#

Clear ICSR’s PENDSTCLR bit.

SysTick exception clear-pending bit.

Write:

0 = No effect.

1 = Removes the pending state from the SysTick exception.

This bit is WO. On a register read its value is Unknown.

inline void toggle_ICSR_PENDSTCLR() volatile#

Toggle ICSR’s PENDSTCLR bit.

SysTick exception clear-pending bit.

Write:

0 = No effect.

1 = Removes the pending state from the SysTick exception.

This bit is WO. On a register read its value is Unknown.

inline bool get_ICSR_PENDSTSET() volatile#

Get ICSR’s PENDSTSET bit.

SysTick exception set-pending bit.

Write:

0 = No effect.

1 = Changes SysTick exception state to pending.

Read:

0 = SysTick exception is not pending.

1 = SysTick exception is pending.

inline void set_ICSR_PENDSTSET() volatile#

Set ICSR’s PENDSTSET bit.

SysTick exception set-pending bit.

Write:

0 = No effect.

1 = Changes SysTick exception state to pending.

Read:

0 = SysTick exception is not pending.

1 = SysTick exception is pending.

inline void clear_ICSR_PENDSTSET() volatile#

Clear ICSR’s PENDSTSET bit.

SysTick exception set-pending bit.

Write:

0 = No effect.

1 = Changes SysTick exception state to pending.

Read:

0 = SysTick exception is not pending.

1 = SysTick exception is pending.

inline void toggle_ICSR_PENDSTSET() volatile#

Toggle ICSR’s PENDSTSET bit.

SysTick exception set-pending bit.

Write:

0 = No effect.

1 = Changes SysTick exception state to pending.

Read:

0 = SysTick exception is not pending.

1 = SysTick exception is pending.

inline bool get_ICSR_PENDSVCLR() volatile#

Get ICSR’s PENDSVCLR bit.

PendSV clear-pending bit.

Write:

0 = No effect.

1 = Removes the pending state from the PendSV exception.

inline void set_ICSR_PENDSVCLR() volatile#

Set ICSR’s PENDSVCLR bit.

PendSV clear-pending bit.

Write:

0 = No effect.

1 = Removes the pending state from the PendSV exception.

inline void clear_ICSR_PENDSVCLR() volatile#

Clear ICSR’s PENDSVCLR bit.

PendSV clear-pending bit.

Write:

0 = No effect.

1 = Removes the pending state from the PendSV exception.

inline void toggle_ICSR_PENDSVCLR() volatile#

Toggle ICSR’s PENDSVCLR bit.

PendSV clear-pending bit.

Write:

0 = No effect.

1 = Removes the pending state from the PendSV exception.

inline bool get_ICSR_PENDSVSET() volatile#

Get ICSR’s PENDSVSET bit.

PendSV set-pending bit.

Write:

0 = No effect.

1 = Changes PendSV exception state to pending.

Read:

0 = PendSV exception is not pending.

1 = PendSV exception is pending.

Writing 1 to this bit is the only way to set the PendSV exception state to pending.

inline void set_ICSR_PENDSVSET() volatile#

Set ICSR’s PENDSVSET bit.

PendSV set-pending bit.

Write:

0 = No effect.

1 = Changes PendSV exception state to pending.

Read:

0 = PendSV exception is not pending.

1 = PendSV exception is pending.

Writing 1 to this bit is the only way to set the PendSV exception state to pending.

inline void clear_ICSR_PENDSVSET() volatile#

Clear ICSR’s PENDSVSET bit.

PendSV set-pending bit.

Write:

0 = No effect.

1 = Changes PendSV exception state to pending.

Read:

0 = PendSV exception is not pending.

1 = PendSV exception is pending.

Writing 1 to this bit is the only way to set the PendSV exception state to pending.

inline void toggle_ICSR_PENDSVSET() volatile#

Toggle ICSR’s PENDSVSET bit.

PendSV set-pending bit.

Write:

0 = No effect.

1 = Changes PendSV exception state to pending.

Read:

0 = PendSV exception is not pending.

1 = PendSV exception is pending.

Writing 1 to this bit is the only way to set the PendSV exception state to pending.

inline bool get_ICSR_NMIPENDSET() volatile#

Get ICSR’s NMIPENDSET bit.

Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.

NMI set-pending bit.

Write:

0 = No effect.

1 = Changes NMI exception state to pending.

Read:

0 = NMI exception is not pending.

1 = NMI exception is pending.

Because NMI is the highest-priority exception, normally the processor enters the NMI

exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears

this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the

NMI signal is reasserted while the processor is executing that handler.

inline void set_ICSR_NMIPENDSET() volatile#

Set ICSR’s NMIPENDSET bit.

Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.

NMI set-pending bit.

Write:

0 = No effect.

1 = Changes NMI exception state to pending.

Read:

0 = NMI exception is not pending.

1 = NMI exception is pending.

Because NMI is the highest-priority exception, normally the processor enters the NMI

exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears

this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the

NMI signal is reasserted while the processor is executing that handler.

inline void clear_ICSR_NMIPENDSET() volatile#

Clear ICSR’s NMIPENDSET bit.

Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.

NMI set-pending bit.

Write:

0 = No effect.

1 = Changes NMI exception state to pending.

Read:

0 = NMI exception is not pending.

1 = NMI exception is pending.

Because NMI is the highest-priority exception, normally the processor enters the NMI

exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears

this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the

NMI signal is reasserted while the processor is executing that handler.

inline void toggle_ICSR_NMIPENDSET() volatile#

Toggle ICSR’s NMIPENDSET bit.

Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.

NMI set-pending bit.

Write:

0 = No effect.

1 = Changes NMI exception state to pending.

Read:

0 = NMI exception is not pending.

1 = NMI exception is pending.

Because NMI is the highest-priority exception, normally the processor enters the NMI

exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears

this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the

NMI signal is reasserted while the processor is executing that handler.

inline void get_ICSR(uint16_t &VECTACTIVE, uint16_t &VECTPENDING, bool &ISRPENDING, bool &ISRPREEMPT, bool &PENDSTCLR, bool &PENDSTSET, bool &PENDSVCLR, bool &PENDSVSET, bool &NMIPENDSET) volatile#

Get all of ICSR’s bit fields.

(read-write) Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.

inline void set_ICSR(bool PENDSTCLR, bool PENDSTSET, bool PENDSVCLR, bool PENDSVSET, bool NMIPENDSET) volatile#

Set all of ICSR’s bit fields.

inline uint32_t get_VTOR_TBLOFF() volatile#

Get VTOR’s TBLOFF field.

Bits [31:8] of the indicate the vector table offset address.

inline void set_VTOR_TBLOFF(uint32_t value) volatile#

Set VTOR’s TBLOFF field.

Bits [31:8] of the indicate the vector table offset address.

inline bool get_AIRCR_VECTCLRACTIVE() volatile#

Get AIRCR’s VECTCLRACTIVE bit.

Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.

inline void set_AIRCR_VECTCLRACTIVE() volatile#

Set AIRCR’s VECTCLRACTIVE bit.

inline void clear_AIRCR_VECTCLRACTIVE() volatile#

Clear AIRCR’s VECTCLRACTIVE bit.

inline void toggle_AIRCR_VECTCLRACTIVE() volatile#

Toggle AIRCR’s VECTCLRACTIVE bit.

inline bool get_AIRCR_SYSRESETREQ() volatile#

Get AIRCR’s SYSRESETREQ bit.

Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.

inline void set_AIRCR_SYSRESETREQ() volatile#

Set AIRCR’s SYSRESETREQ bit.

inline void clear_AIRCR_SYSRESETREQ() volatile#

Clear AIRCR’s SYSRESETREQ bit.

inline void toggle_AIRCR_SYSRESETREQ() volatile#

Toggle AIRCR’s SYSRESETREQ bit.

inline bool get_AIRCR_ENDIANESS() volatile#

Get AIRCR’s ENDIANESS bit.

Data endianness implemented:

0 = Little-endian.

inline uint16_t get_AIRCR_VECTKEY() volatile#

Get AIRCR’s VECTKEY field.

Reads as Unknown

On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.

inline void set_AIRCR_VECTKEY(uint16_t value) volatile#

Set AIRCR’s VECTKEY field.

Reads as Unknown

On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.

inline void get_AIRCR(bool &VECTCLRACTIVE, bool &SYSRESETREQ, bool &ENDIANESS, uint16_t &VECTKEY) volatile#

Get all of AIRCR’s bit fields.

(read-write) Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.

inline void set_AIRCR(bool VECTCLRACTIVE, bool SYSRESETREQ, uint16_t VECTKEY) volatile#

Set all of AIRCR’s bit fields.

(read-write) Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.

inline bool get_SCR_SLEEPONEXIT() volatile#

Get SCR’s SLEEPONEXIT bit.

Indicates sleep-on-exit when returning from Handler mode to Thread mode:

0 = Do not sleep when returning to Thread mode.

1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.

Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.

inline void set_SCR_SLEEPONEXIT() volatile#

Set SCR’s SLEEPONEXIT bit.

Indicates sleep-on-exit when returning from Handler mode to Thread mode:

0 = Do not sleep when returning to Thread mode.

1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.

Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.

inline void clear_SCR_SLEEPONEXIT() volatile#

Clear SCR’s SLEEPONEXIT bit.

Indicates sleep-on-exit when returning from Handler mode to Thread mode:

0 = Do not sleep when returning to Thread mode.

1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.

Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.

inline void toggle_SCR_SLEEPONEXIT() volatile#

Toggle SCR’s SLEEPONEXIT bit.

Indicates sleep-on-exit when returning from Handler mode to Thread mode:

0 = Do not sleep when returning to Thread mode.

1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.

Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.

inline bool get_SCR_SLEEPDEEP() volatile#

Get SCR’s SLEEPDEEP bit.

Controls whether the processor uses sleep or deep sleep as its low power mode:

0 = Sleep.

1 = Deep sleep.

inline void set_SCR_SLEEPDEEP() volatile#

Set SCR’s SLEEPDEEP bit.

Controls whether the processor uses sleep or deep sleep as its low power mode:

0 = Sleep.

1 = Deep sleep.

inline void clear_SCR_SLEEPDEEP() volatile#

Clear SCR’s SLEEPDEEP bit.

Controls whether the processor uses sleep or deep sleep as its low power mode:

0 = Sleep.

1 = Deep sleep.

inline void toggle_SCR_SLEEPDEEP() volatile#

Toggle SCR’s SLEEPDEEP bit.

Controls whether the processor uses sleep or deep sleep as its low power mode:

0 = Sleep.

1 = Deep sleep.

inline bool get_SCR_SEVONPEND() volatile#

Get SCR’s SEVONPEND bit.

Send Event on Pending bit:

0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the

processor is not waiting for an event, the event is registered and affects the next WFE.

The processor also wakes up on execution of an SEV instruction or an external event.

inline void set_SCR_SEVONPEND() volatile#

Set SCR’s SEVONPEND bit.

Send Event on Pending bit:

0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the

processor is not waiting for an event, the event is registered and affects the next WFE.

The processor also wakes up on execution of an SEV instruction or an external event.

inline void clear_SCR_SEVONPEND() volatile#

Clear SCR’s SEVONPEND bit.

Send Event on Pending bit:

0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the

processor is not waiting for an event, the event is registered and affects the next WFE.

The processor also wakes up on execution of an SEV instruction or an external event.

inline void toggle_SCR_SEVONPEND() volatile#

Toggle SCR’s SEVONPEND bit.

Send Event on Pending bit:

0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the

processor is not waiting for an event, the event is registered and affects the next WFE.

The processor also wakes up on execution of an SEV instruction or an external event.

inline void get_SCR(bool &SLEEPONEXIT, bool &SLEEPDEEP, bool &SEVONPEND) volatile#

Get all of SCR’s bit fields.

(read-write) System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.

inline void set_SCR(bool SLEEPONEXIT, bool SLEEPDEEP, bool SEVONPEND) volatile#

Set all of SCR’s bit fields.

inline bool get_CCR_UNALIGN_TRP() volatile#

Get CCR’s UNALIGN_TRP bit.

Always reads as one, indicates that all unaligned accesses generate a HardFault.

inline bool get_CCR_STKALIGN() volatile#

Get CCR’s STKALIGN bit.

Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.

inline void get_CCR(bool &UNALIGN_TRP, bool &STKALIGN) volatile#

Get all of CCR’s bit fields.

(read-only) The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.

inline uint8_t get_SHPR2_PRI_11() volatile#

Get SHPR2’s PRI_11 field.

Priority of system handler 11, SVCall

inline void set_SHPR2_PRI_11(uint8_t value) volatile#

Set SHPR2’s PRI_11 field.

Priority of system handler 11, SVCall

inline uint8_t get_SHPR3_PRI_14() volatile#

Get SHPR3’s PRI_14 field.

Priority of system handler 14, PendSV

inline void set_SHPR3_PRI_14(uint8_t value) volatile#

Set SHPR3’s PRI_14 field.

Priority of system handler 14, PendSV

inline uint8_t get_SHPR3_PRI_15() volatile#

Get SHPR3’s PRI_15 field.

Priority of system handler 15, SysTick

inline void set_SHPR3_PRI_15(uint8_t value) volatile#

Set SHPR3’s PRI_15 field.

Priority of system handler 15, SysTick

inline void get_SHPR3(uint8_t &PRI_14, uint8_t &PRI_15) volatile#

Get all of SHPR3’s bit fields.

(read-write) System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.

inline void set_SHPR3(uint8_t PRI_14, uint8_t PRI_15) volatile#

Set all of SHPR3’s bit fields.

inline bool get_SHCSR_SVCALLPENDED() volatile#

Get SHCSR’s SVCALLPENDED bit.

Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall.

inline void set_SHCSR_SVCALLPENDED() volatile#

Set SHCSR’s SVCALLPENDED bit.

Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall.

inline void clear_SHCSR_SVCALLPENDED() volatile#

Clear SHCSR’s SVCALLPENDED bit.

Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall.

inline void toggle_SHCSR_SVCALLPENDED() volatile#

Toggle SHCSR’s SVCALLPENDED bit.

Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall.

inline bool get_MPU_TYPE_SEPARATE() volatile#

Get MPU_TYPE’s SEPARATE bit.

Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU.

inline uint8_t get_MPU_TYPE_DREGION() volatile#

Get MPU_TYPE’s DREGION field.

Number of regions supported by the MPU.

inline uint8_t get_MPU_TYPE_IREGION() volatile#

Get MPU_TYPE’s IREGION field.

Instruction region. Reads as zero as ARMv6-M only supports a unified MPU.

inline void get_MPU_TYPE(bool &SEPARATE, uint8_t &DREGION, uint8_t &IREGION) volatile#

Get all of MPU_TYPE’s bit fields.

(read-only) Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.

inline bool get_MPU_CTRL_ENABLE() volatile#

Get MPU_CTRL’s ENABLE bit.

Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.

0 = MPU disabled.

1 = MPU enabled.

inline void set_MPU_CTRL_ENABLE() volatile#

Set MPU_CTRL’s ENABLE bit.

Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.

0 = MPU disabled.

1 = MPU enabled.

inline void clear_MPU_CTRL_ENABLE() volatile#

Clear MPU_CTRL’s ENABLE bit.

Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.

0 = MPU disabled.

1 = MPU enabled.

inline void toggle_MPU_CTRL_ENABLE() volatile#

Toggle MPU_CTRL’s ENABLE bit.

Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.

0 = MPU disabled.

1 = MPU enabled.

inline bool get_MPU_CTRL_HFNMIENA() volatile#

Get MPU_CTRL’s HFNMIENA bit.

Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.

When the MPU is enabled:

0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.

1 = the MPU is enabled during HardFault and NMI handlers.

inline void set_MPU_CTRL_HFNMIENA() volatile#

Set MPU_CTRL’s HFNMIENA bit.

Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.

When the MPU is enabled:

0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.

1 = the MPU is enabled during HardFault and NMI handlers.

inline void clear_MPU_CTRL_HFNMIENA() volatile#

Clear MPU_CTRL’s HFNMIENA bit.

Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.

When the MPU is enabled:

0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.

1 = the MPU is enabled during HardFault and NMI handlers.

inline void toggle_MPU_CTRL_HFNMIENA() volatile#

Toggle MPU_CTRL’s HFNMIENA bit.

Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.

When the MPU is enabled:

0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.

1 = the MPU is enabled during HardFault and NMI handlers.

inline bool get_MPU_CTRL_PRIVDEFENA() volatile#

Get MPU_CTRL’s PRIVDEFENA bit.

Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.

0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not

covered by any enabled region causes a fault.

1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.

When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.

inline void set_MPU_CTRL_PRIVDEFENA() volatile#

Set MPU_CTRL’s PRIVDEFENA bit.

Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.

0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not

covered by any enabled region causes a fault.

1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.

When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.

inline void clear_MPU_CTRL_PRIVDEFENA() volatile#

Clear MPU_CTRL’s PRIVDEFENA bit.

Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.

0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not

covered by any enabled region causes a fault.

1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.

When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.

inline void toggle_MPU_CTRL_PRIVDEFENA() volatile#

Toggle MPU_CTRL’s PRIVDEFENA bit.

Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.

0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not

covered by any enabled region causes a fault.

1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.

When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.

inline void get_MPU_CTRL(bool &ENABLE, bool &HFNMIENA, bool &PRIVDEFENA) volatile#

Get all of MPU_CTRL’s bit fields.

(read-write) Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.

inline void set_MPU_CTRL(bool ENABLE, bool HFNMIENA, bool PRIVDEFENA) volatile#

Set all of MPU_CTRL’s bit fields.

inline uint8_t get_MPU_RNR_REGION() volatile#

Get MPU_RNR’s REGION field.

Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.

The MPU supports 8 memory regions, so the permitted values of this field are 0-7.

inline void set_MPU_RNR_REGION(uint8_t value) volatile#

Set MPU_RNR’s REGION field.

Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.

The MPU supports 8 memory regions, so the permitted values of this field are 0-7.

inline uint8_t get_MPU_RBAR_REGION() volatile#

Get MPU_RBAR’s REGION field.

On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR.

inline void set_MPU_RBAR_REGION(uint8_t value) volatile#

Set MPU_RBAR’s REGION field.

On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR.

inline bool get_MPU_RBAR_VALID() volatile#

Get MPU_RBAR’s VALID bit.

On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.

Write:

0 = MPU_RNR not changed, and the processor:

Updates the base address for the region specified in the MPU_RNR.

Ignores the value of the REGION field.

1 = The processor:

Updates the value of the MPU_RNR to the value of the REGION field.

Updates the base address for the region specified in the REGION field.

Always reads as zero.

inline void set_MPU_RBAR_VALID() volatile#

Set MPU_RBAR’s VALID bit.

On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.

Write:

0 = MPU_RNR not changed, and the processor:

Updates the base address for the region specified in the MPU_RNR.

Ignores the value of the REGION field.

1 = The processor:

Updates the value of the MPU_RNR to the value of the REGION field.

Updates the base address for the region specified in the REGION field.

Always reads as zero.

inline void clear_MPU_RBAR_VALID() volatile#

Clear MPU_RBAR’s VALID bit.

On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.

Write:

0 = MPU_RNR not changed, and the processor:

Updates the base address for the region specified in the MPU_RNR.

Ignores the value of the REGION field.

1 = The processor:

Updates the value of the MPU_RNR to the value of the REGION field.

Updates the base address for the region specified in the REGION field.

Always reads as zero.

inline void toggle_MPU_RBAR_VALID() volatile#

Toggle MPU_RBAR’s VALID bit.

On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.

Write:

0 = MPU_RNR not changed, and the processor:

Updates the base address for the region specified in the MPU_RNR.

Ignores the value of the REGION field.

1 = The processor:

Updates the value of the MPU_RNR to the value of the REGION field.

Updates the base address for the region specified in the REGION field.

Always reads as zero.

inline uint32_t get_MPU_RBAR_ADDR() volatile#

Get MPU_RBAR’s ADDR field.

Base address of the region.

inline void set_MPU_RBAR_ADDR(uint32_t value) volatile#

Set MPU_RBAR’s ADDR field.

Base address of the region.

inline void get_MPU_RBAR(uint8_t &REGION, bool &VALID, uint32_t &ADDR) volatile#

Get all of MPU_RBAR’s bit fields.

(read-write) Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.

inline void set_MPU_RBAR(uint8_t REGION, bool VALID, uint32_t ADDR) volatile#

Set all of MPU_RBAR’s bit fields.

inline bool get_MPU_RASR_ENABLE() volatile#

Get MPU_RASR’s ENABLE bit.

Enables the region.

inline void set_MPU_RASR_ENABLE() volatile#

Set MPU_RASR’s ENABLE bit.

Enables the region.

inline void clear_MPU_RASR_ENABLE() volatile#

Clear MPU_RASR’s ENABLE bit.

Enables the region.

inline void toggle_MPU_RASR_ENABLE() volatile#

Toggle MPU_RASR’s ENABLE bit.

Enables the region.

inline uint8_t get_MPU_RASR_SIZE() volatile#

Get MPU_RASR’s SIZE field.

Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes

inline void set_MPU_RASR_SIZE(uint8_t value) volatile#

Set MPU_RASR’s SIZE field.

Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes

inline uint8_t get_MPU_RASR_SRD() volatile#

Get MPU_RASR’s SRD field.

Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled.

inline void set_MPU_RASR_SRD(uint8_t value) volatile#

Set MPU_RASR’s SRD field.

Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled.

inline uint16_t get_MPU_RASR_ATTRS() volatile#

Get MPU_RASR’s ATTRS field.

The MPU Region Attribute field. Use to define the region attribute control.

28 = XN: Instruction access disable bit:

0 = Instruction fetches enabled.

1 = Instruction fetches disabled.

26:24 = AP: Access permission field

18 = S: Shareable bit

17 = C: Cacheable bit

16 = B: Bufferable bit

inline void set_MPU_RASR_ATTRS(uint16_t value) volatile#

Set MPU_RASR’s ATTRS field.

The MPU Region Attribute field. Use to define the region attribute control.

28 = XN: Instruction access disable bit:

0 = Instruction fetches enabled.

1 = Instruction fetches disabled.

26:24 = AP: Access permission field

18 = S: Shareable bit

17 = C: Cacheable bit

16 = B: Bufferable bit

inline void get_MPU_RASR(bool &ENABLE, uint8_t &SIZE, uint8_t &SRD, uint16_t &ATTRS) volatile#

Get all of MPU_RASR’s bit fields.

(read-write) Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.

inline void set_MPU_RASR(bool ENABLE, uint8_t SIZE, uint8_t SRD, uint16_t ATTRS) volatile#

Set all of MPU_RASR’s bit fields.

(read-write) Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.

Public Members

const uint32_t reserved_padding0[reserved_padding0_length] = {}#

uint32_t SYST_CSR#: (read-write) Use the SysTick Control and Status Register to enable the SysTick features.

uint32_t SYST_RVR#

(read-write) Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.

To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.

uint32_t SYST_CVR#: (read-write) Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.

const uint32_t SYST_CALIB = {}#: (read-only) Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.

const uint32_t reserved_padding1[reserved_padding1_length] = {}#

uint32_t NVIC_ISER#

(read-write) Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.

If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.

const uint32_t reserved_padding2[reserved_padding2_length] = {}#

uint32_t NVIC_ICER#: (read-write) Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.

const uint32_t reserved_padding3[reserved_padding3_length] = {}#

uint32_t NVIC_ISPR#: (read-write) The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.

const uint32_t reserved_padding4[reserved_padding4_length] = {}#

uint32_t NVIC_ICPR#: (read-write) Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.

const uint32_t reserved_padding5[reserved_padding5_length] = {}#

uint32_t NVIC_IPR0#

(read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.

These registers are only word-accessible

uint32_t NVIC_IPR1#: (read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

uint32_t NVIC_IPR2#: (read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

uint32_t NVIC_IPR3#: (read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

uint32_t NVIC_IPR4#: (read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

uint32_t NVIC_IPR5#: (read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

uint32_t NVIC_IPR6#: (read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

uint32_t NVIC_IPR7#: (read-write) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

const uint32_t reserved_padding6[reserved_padding6_length] = {}#

const uint32_t CPUID = {}#: (read-only) Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.

uint32_t ICSR#: (read-write) Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.

uint32_t VTOR#: (read-write) The VTOR holds the vector table offset address.

uint32_t AIRCR#: (read-write) Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.

uint32_t SCR#: (read-write) System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.

const uint32_t CCR = {}#: (read-only) The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.

const uint32_t reserved_padding7 = {}#

uint32_t SHPR2#: (read-write) System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.

uint32_t SHPR3#: (read-write) System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.

uint32_t SHCSR#: (read-write) Use the System Handler Control and State Register to determine or clear the pending status of SVCall.

const uint32_t reserved_padding8[reserved_padding8_length] = {}#

const uint32_t MPU_TYPE = {}#: (read-only) Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.

uint32_t MPU_CTRL#: (read-write) Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.

uint32_t MPU_RNR#: (read-write) Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.

uint32_t MPU_RBAR#: (read-write) Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.

uint32_t MPU_RASR#: (read-write) Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.

Public Static Attributes

static constexpr std::size_t size = 60836#: ppb’s size in bytes.

static constexpr std::size_t reserved_padding0_length = 14340#

static constexpr std::size_t reserved_padding1_length = 56#

static constexpr std::size_t reserved_padding2_length = 31#

static constexpr std::size_t reserved_padding3_length = 31#

static constexpr std::size_t reserved_padding4_length = 31#

static constexpr std::size_t reserved_padding5_length = 95#

static constexpr std::size_t reserved_padding6_length = 568#

static constexpr std::size_t reserved_padding8_length = 26#

Struct ppb

Contents

Struct ppb#

Struct Documentation#