Struct adc

• Defined in File adc.h

Struct Documentation

struct adc

Control and data interface to SAR ADC

Public Functions

inline bool get_CS_EN() volatile

Get CS’s EN bit.

Power on ADC and enable its clock.

1 - enabled. 0 - disabled.

inline void set_CS_EN() volatile

Set CS’s EN bit.

Power on ADC and enable its clock.

1 - enabled. 0 - disabled.

inline void clear_CS_EN() volatile

Clear CS’s EN bit.

Power on ADC and enable its clock.

1 - enabled. 0 - disabled.

inline void toggle_CS_EN() volatile

Toggle CS’s EN bit.

Power on ADC and enable its clock.

1 - enabled. 0 - disabled.

inline bool get_CS_TS_EN() volatile

Get CS’s TS_EN bit.

Power on temperature sensor. 1 - enabled. 0 - disabled.

inline void set_CS_TS_EN() volatile

Set CS’s TS_EN bit.

Power on temperature sensor. 1 - enabled. 0 - disabled.

inline void clear_CS_TS_EN() volatile

Clear CS’s TS_EN bit.

Power on temperature sensor. 1 - enabled. 0 - disabled.

inline void toggle_CS_TS_EN() volatile

Toggle CS’s TS_EN bit.

Power on temperature sensor. 1 - enabled. 0 - disabled.

inline bool get_CS_START_ONCE() volatile

Get CS’s START_ONCE bit.

Start a single conversion. Self-clearing. Ignored if start_many is asserted.

inline void set_CS_START_ONCE() volatile

Set CS’s START_ONCE bit.

Start a single conversion. Self-clearing. Ignored if start_many is asserted.

inline void clear_CS_START_ONCE() volatile

Clear CS’s START_ONCE bit.

Start a single conversion. Self-clearing. Ignored if start_many is asserted.

inline void toggle_CS_START_ONCE() volatile

Toggle CS’s START_ONCE bit.

Start a single conversion. Self-clearing. Ignored if start_many is asserted.

inline bool get_CS_START_MANY() volatile

Get CS’s START_MANY bit.

Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.

inline void set_CS_START_MANY() volatile

Set CS’s START_MANY bit.

Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.

inline void clear_CS_START_MANY() volatile

Clear CS’s START_MANY bit.

Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.

inline void toggle_CS_START_MANY() volatile

Toggle CS’s START_MANY bit.

Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.

inline bool get_CS_READY() volatile

Get CS’s READY bit.

1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.

0 whilst conversion in progress.

inline bool get_CS_ERR() volatile

Get CS’s ERR bit.

The most recent ADC conversion encountered an error; result is undefined or noisy.

inline bool get_CS_ERR_STICKY() volatile

Get CS’s ERR_STICKY bit.

Some past ADC conversion encountered an error. Write 1 to clear.

inline void set_CS_ERR_STICKY() volatile

Set CS’s ERR_STICKY bit.

Some past ADC conversion encountered an error. Write 1 to clear.

inline void clear_CS_ERR_STICKY() volatile

Clear CS’s ERR_STICKY bit.

Some past ADC conversion encountered an error. Write 1 to clear.

inline void toggle_CS_ERR_STICKY() volatile

Toggle CS’s ERR_STICKY bit.

Some past ADC conversion encountered an error. Write 1 to clear.

inline uint8_t get_CS_AINSEL() volatile

Get CS’s AINSEL field.

Select analog mux input. Updated automatically in round-robin mode.

inline void set_CS_AINSEL(uint8_t value) volatile

Set CS’s AINSEL field.

Select analog mux input. Updated automatically in round-robin mode.

inline uint8_t get_CS_RROBIN() volatile

Get CS’s RROBIN field.

Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.

Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.

The first channel to be sampled will be the one currently indicated by AINSEL.

AINSEL will be updated after each conversion with the newly-selected channel.

inline void set_CS_RROBIN(uint8_t value) volatile

Set CS’s RROBIN field.

Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.

Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.

The first channel to be sampled will be the one currently indicated by AINSEL.

AINSEL will be updated after each conversion with the newly-selected channel.

inline void get_CS(bool &EN, bool &TS_EN, bool &START_ONCE, bool &START_MANY, bool &READY, bool &ERR, bool &ERR_STICKY, uint8_t &AINSEL, uint8_t &RROBIN) volatile

Get all of CS’s bit fields.

(read-write) ADC Control and Status

inline void set_CS(bool EN, bool TS_EN, bool START_ONCE, bool START_MANY, bool ERR_STICKY, uint8_t AINSEL, uint8_t RROBIN) volatile

Set all of CS’s bit fields.

(read-write) ADC Control and Status

inline uint16_t get_RESULT_RESULT() volatile

Get RESULT’s RESULT field.

inline bool get_FCS_EN() volatile

Get FCS’s EN bit.

If 1: write result to the FIFO after each conversion.

inline void set_FCS_EN() volatile

Set FCS’s EN bit.

If 1: write result to the FIFO after each conversion.

inline void clear_FCS_EN() volatile

Clear FCS’s EN bit.

If 1: write result to the FIFO after each conversion.

inline void toggle_FCS_EN() volatile

Toggle FCS’s EN bit.

If 1: write result to the FIFO after each conversion.

inline bool get_FCS_SHIFT() volatile

Get FCS’s SHIFT bit.

If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.

inline void set_FCS_SHIFT() volatile

Set FCS’s SHIFT bit.

If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.

inline void clear_FCS_SHIFT() volatile

Clear FCS’s SHIFT bit.

If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.

inline void toggle_FCS_SHIFT() volatile

Toggle FCS’s SHIFT bit.

If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.

inline bool get_FCS_ERR() volatile

Get FCS’s ERR bit.

If 1: conversion error bit appears in the FIFO alongside the result

inline void set_FCS_ERR() volatile

Set FCS’s ERR bit.

If 1: conversion error bit appears in the FIFO alongside the result

inline void clear_FCS_ERR() volatile

Clear FCS’s ERR bit.

If 1: conversion error bit appears in the FIFO alongside the result

inline void toggle_FCS_ERR() volatile

Toggle FCS’s ERR bit.

If 1: conversion error bit appears in the FIFO alongside the result

inline bool get_FCS_DREQ_EN() volatile

Get FCS’s DREQ_EN bit.

If 1: assert DMA requests when FIFO contains data

inline void set_FCS_DREQ_EN() volatile

Set FCS’s DREQ_EN bit.

If 1: assert DMA requests when FIFO contains data

inline void clear_FCS_DREQ_EN() volatile

Clear FCS’s DREQ_EN bit.

If 1: assert DMA requests when FIFO contains data

inline void toggle_FCS_DREQ_EN() volatile

Toggle FCS’s DREQ_EN bit.

If 1: assert DMA requests when FIFO contains data

inline bool get_FCS_EMPTY() volatile

Get FCS’s EMPTY bit.

inline bool get_FCS_FULL() volatile

Get FCS’s FULL bit.

inline bool get_FCS_UNDER() volatile

Get FCS’s UNDER bit.

1 if the FIFO has been underflowed. Write 1 to clear.

inline void set_FCS_UNDER() volatile

Set FCS’s UNDER bit.

1 if the FIFO has been underflowed. Write 1 to clear.

inline void clear_FCS_UNDER() volatile

Clear FCS’s UNDER bit.

1 if the FIFO has been underflowed. Write 1 to clear.

inline void toggle_FCS_UNDER() volatile

Toggle FCS’s UNDER bit.

1 if the FIFO has been underflowed. Write 1 to clear.

inline bool get_FCS_OVER() volatile

Get FCS’s OVER bit.

1 if the FIFO has been overflowed. Write 1 to clear.

inline void set_FCS_OVER() volatile

Set FCS’s OVER bit.

1 if the FIFO has been overflowed. Write 1 to clear.

inline void clear_FCS_OVER() volatile

Clear FCS’s OVER bit.

1 if the FIFO has been overflowed. Write 1 to clear.

inline void toggle_FCS_OVER() volatile

Toggle FCS’s OVER bit.

1 if the FIFO has been overflowed. Write 1 to clear.

inline uint8_t get_FCS_LEVEL() volatile

Get FCS’s LEVEL field.

The number of conversion results currently waiting in the FIFO

inline uint8_t get_FCS_THRESH() volatile

Get FCS’s THRESH field.

DREQ/IRQ asserted when level >= threshold

inline void set_FCS_THRESH(uint8_t value) volatile

Set FCS’s THRESH field.

DREQ/IRQ asserted when level >= threshold

inline void get_FCS(bool &EN, bool &SHIFT, bool &ERR, bool &DREQ_EN, bool &EMPTY, bool &FULL, bool &UNDER, bool &OVER, uint8_t &LEVEL, uint8_t &THRESH) volatile

Get all of FCS’s bit fields.

(read-write) FIFO control and status

inline void set_FCS(bool EN, bool SHIFT, bool ERR, bool DREQ_EN, bool UNDER, bool OVER, uint8_t THRESH) volatile

Set all of FCS’s bit fields.

(read-write) FIFO control and status

inline uint16_t get_FIFO_VAL() volatile

Get FIFO’s VAL field.

inline bool get_FIFO_ERR() volatile

Get FIFO’s ERR bit.

1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted.

inline void get_FIFO(uint16_t &VAL, bool &ERR) volatile

Get all of FIFO’s bit fields.

(read-only) Conversion result FIFO

inline uint8_t get_DIV_FRAC() volatile

Get DIV’s FRAC field.

Fractional part of clock divisor. First-order delta-sigma.

inline void set_DIV_FRAC(uint8_t value) volatile

Set DIV’s FRAC field.

Fractional part of clock divisor. First-order delta-sigma.

inline uint16_t get_DIV_INT() volatile

Get DIV’s INT field.

Integer part of clock divisor.

inline void set_DIV_INT(uint16_t value) volatile

Set DIV’s INT field.

Integer part of clock divisor.

inline void get_DIV(uint8_t &FRAC, uint16_t &INT) volatile

Get all of DIV’s bit fields.

(read-write) Clock divider. If non-zero, CS_START_MANY will start conversions

at regular intervals rather than back-to-back.

The divider is reset when either of these fields are written.

Total period is 1 + INT + FRAC / 256

inline void set_DIV(uint8_t FRAC, uint16_t INT) volatile

Set all of DIV’s bit fields.

(read-write) Clock divider. If non-zero, CS_START_MANY will start conversions

at regular intervals rather than back-to-back.

The divider is reset when either of these fields are written.

Total period is 1 + INT + FRAC / 256

inline bool get_INTR_FIFO() volatile

Get INTR’s FIFO bit.

Triggered when the sample FIFO reaches a certain level.

This level can be programmed via the FCS_THRESH field.

inline bool get_INTE_FIFO() volatile

Get INTE’s FIFO bit.

Triggered when the sample FIFO reaches a certain level.

This level can be programmed via the FCS_THRESH field.

inline void set_INTE_FIFO() volatile

Set INTE’s FIFO bit.

Triggered when the sample FIFO reaches a certain level.

This level can be programmed via the FCS_THRESH field.

inline void clear_INTE_FIFO() volatile

Clear INTE’s FIFO bit.

Triggered when the sample FIFO reaches a certain level.

This level can be programmed via the FCS_THRESH field.

inline void toggle_INTE_FIFO() volatile

Toggle INTE’s FIFO bit.

Triggered when the sample FIFO reaches a certain level.

This level can be programmed via the FCS_THRESH field.

inline bool get_INTF_FIFO() volatile

Get INTF’s FIFO bit.

Triggered when the sample FIFO reaches a certain level.

This level can be programmed via the FCS_THRESH field.

inline void set_INTF_FIFO() volatile

Set INTF’s FIFO bit.

Triggered when the sample FIFO reaches a certain level.

This level can be programmed via the FCS_THRESH field.

inline void clear_INTF_FIFO() volatile

Clear INTF’s FIFO bit.

Triggered when the sample FIFO reaches a certain level.

This level can be programmed via the FCS_THRESH field.

inline void toggle_INTF_FIFO() volatile

Toggle INTF’s FIFO bit.

Triggered when the sample FIFO reaches a certain level.

This level can be programmed via the FCS_THRESH field.

inline bool get_INTS_FIFO() volatile

Get INTS’s FIFO bit.

Triggered when the sample FIFO reaches a certain level.

This level can be programmed via the FCS_THRESH field.

Public Members

uint32_t CS

(read-write) ADC Control and Status

const uint32_t RESULT = {}

(read-only) Result of most recent ADC conversion

uint32_t FCS

(read-write) FIFO control and status

const uint32_t FIFO = {}

(read-only) Conversion result FIFO

uint32_t DIV

(read-write) Clock divider. If non-zero, CS_START_MANY will start conversions

at regular intervals rather than back-to-back.

The divider is reset when either of these fields are written.

Total period is 1

• INT + FRAC / 256

const uint32_t INTR = {}

(read-only) Raw Interrupts

uint32_t INTE

(read-write) Interrupt Enable

uint32_t INTF

(read-write) Interrupt Force

const uint32_t INTS = {}

(read-only) Interrupt status after masking & forcing

Public Static Attributes

static constexpr std::size_t size = 36

adc’s size in bytes.