Struct rosc#

Struct Documentation#

struct rosc#

Public Functions

inline ROSC_CTRL_FREQ_RANGE get_CTRL_FREQ_RANGE() volatile#

Get CTRL’s FREQ_RANGE field.

Controls the number of delay stages in the ROSC ring

LOW uses stages 0 to 7

MEDIUM uses stages 0 to 5

HIGH uses stages 0 to 3

TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications

The clock output will not glitch when changing the range up one step at a time

The clock output will glitch when changing the range down

Note: the values here are gray coded which is why HIGH comes before TOOHIGH

inline void set_CTRL_FREQ_RANGE(ROSC_CTRL_FREQ_RANGE value) volatile#

Set CTRL’s FREQ_RANGE field.

Controls the number of delay stages in the ROSC ring

LOW uses stages 0 to 7

MEDIUM uses stages 0 to 5

HIGH uses stages 0 to 3

TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications

The clock output will not glitch when changing the range up one step at a time

The clock output will glitch when changing the range down

Note: the values here are gray coded which is why HIGH comes before TOOHIGH

inline ROSC_CTRL_ENABLE get_CTRL_ENABLE() volatile#

Get CTRL’s ENABLE field.

On power-up this field is initialised to ENABLE

The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up

The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.

inline void set_CTRL_ENABLE(ROSC_CTRL_ENABLE value) volatile#

Set CTRL’s ENABLE field.

On power-up this field is initialised to ENABLE

The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up

The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.

inline void get_CTRL(ROSC_CTRL_FREQ_RANGE &FREQ_RANGE, ROSC_CTRL_ENABLE &ENABLE) volatile#

Get all of CTRL’s bit fields.

(read-write) Ring Oscillator control

inline void set_CTRL(ROSC_CTRL_FREQ_RANGE FREQ_RANGE, ROSC_CTRL_ENABLE ENABLE) volatile#

Set all of CTRL’s bit fields.

(read-write) Ring Oscillator control

inline uint8_t get_FREQA_DS0() volatile#

Get FREQA’s DS0 field.

Stage 0 drive strength

inline void set_FREQA_DS0(uint8_t value) volatile#

Set FREQA’s DS0 field.

Stage 0 drive strength

inline uint8_t get_FREQA_DS1() volatile#

Get FREQA’s DS1 field.

Stage 1 drive strength

inline void set_FREQA_DS1(uint8_t value) volatile#

Set FREQA’s DS1 field.

Stage 1 drive strength

inline uint8_t get_FREQA_DS2() volatile#

Get FREQA’s DS2 field.

Stage 2 drive strength

inline void set_FREQA_DS2(uint8_t value) volatile#

Set FREQA’s DS2 field.

Stage 2 drive strength

inline uint8_t get_FREQA_DS3() volatile#

Get FREQA’s DS3 field.

Stage 3 drive strength

inline void set_FREQA_DS3(uint8_t value) volatile#

Set FREQA’s DS3 field.

Stage 3 drive strength

inline ROSC_FREQA_PASSWD get_FREQA_PASSWD() volatile#

Get FREQA’s PASSWD field.

Set to 0x9696 to apply the settings

Any other value in this field will set all drive strengths to 0

inline void set_FREQA_PASSWD(ROSC_FREQA_PASSWD value) volatile#

Set FREQA’s PASSWD field.

Set to 0x9696 to apply the settings

Any other value in this field will set all drive strengths to 0

inline void get_FREQA(uint8_t &DS0, uint8_t &DS1, uint8_t &DS2, uint8_t &DS3, ROSC_FREQA_PASSWD &PASSWD) volatile#

Get all of FREQA’s bit fields.

(read-write) The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage

The drive strength has 4 levels determined by the number of bits set

Increasing the number of bits set increases the drive strength and increases the oscillation frequency

0 bits set is the default drive strength

1 bit set doubles the drive strength

2 bits set triples drive strength

3 bits set quadruples drive strength

inline void set_FREQA(uint8_t DS0, uint8_t DS1, uint8_t DS2, uint8_t DS3, ROSC_FREQA_PASSWD PASSWD) volatile#

Set all of FREQA’s bit fields.

(read-write) The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage

The drive strength has 4 levels determined by the number of bits set

Increasing the number of bits set increases the drive strength and increases the oscillation frequency

0 bits set is the default drive strength

1 bit set doubles the drive strength

2 bits set triples drive strength

3 bits set quadruples drive strength

inline uint8_t get_FREQB_DS4() volatile#

Get FREQB’s DS4 field.

Stage 4 drive strength

inline void set_FREQB_DS4(uint8_t value) volatile#

Set FREQB’s DS4 field.

Stage 4 drive strength

inline uint8_t get_FREQB_DS5() volatile#

Get FREQB’s DS5 field.

Stage 5 drive strength

inline void set_FREQB_DS5(uint8_t value) volatile#

Set FREQB’s DS5 field.

Stage 5 drive strength

inline uint8_t get_FREQB_DS6() volatile#

Get FREQB’s DS6 field.

Stage 6 drive strength

inline void set_FREQB_DS6(uint8_t value) volatile#

Set FREQB’s DS6 field.

Stage 6 drive strength

inline uint8_t get_FREQB_DS7() volatile#

Get FREQB’s DS7 field.

Stage 7 drive strength

inline void set_FREQB_DS7(uint8_t value) volatile#

Set FREQB’s DS7 field.

Stage 7 drive strength

inline ROSC_FREQB_PASSWD get_FREQB_PASSWD() volatile#

Get FREQB’s PASSWD field.

Set to 0x9696 to apply the settings

Any other value in this field will set all drive strengths to 0

inline void set_FREQB_PASSWD(ROSC_FREQB_PASSWD value) volatile#

Set FREQB’s PASSWD field.

Set to 0x9696 to apply the settings

Any other value in this field will set all drive strengths to 0

inline void get_FREQB(uint8_t &DS4, uint8_t &DS5, uint8_t &DS6, uint8_t &DS7, ROSC_FREQB_PASSWD &PASSWD) volatile#

Get all of FREQB’s bit fields.

(read-write) For a detailed description see freqa register

inline void set_FREQB(uint8_t DS4, uint8_t DS5, uint8_t DS6, uint8_t DS7, ROSC_FREQB_PASSWD PASSWD) volatile#

Set all of FREQB’s bit fields.

(read-write) For a detailed description see freqa register

inline ROSC_DIV_DIV get_DIV_DIV() volatile#

Get DIV’s DIV field.

set to 0xaa0 + div where

div = 0 divides by 32

div = 1-31 divides by div

any other value sets div=31

this register resets to div=16

inline void set_DIV_DIV(ROSC_DIV_DIV value) volatile#

Set DIV’s DIV field.

set to 0xaa0 + div where

div = 0 divides by 32

div = 1-31 divides by div

any other value sets div=31

this register resets to div=16

inline uint8_t get_PHASE_SHIFT() volatile#

Get PHASE’s SHIFT field.

phase shift the phase-shifted output by SHIFT input clocks

this can be changed on-the-fly

must be set to 0 before setting div=1

inline void set_PHASE_SHIFT(uint8_t value) volatile#

Set PHASE’s SHIFT field.

phase shift the phase-shifted output by SHIFT input clocks

this can be changed on-the-fly

must be set to 0 before setting div=1

inline bool get_PHASE_FLIP() volatile#

Get PHASE’s FLIP bit.

invert the phase-shifted output

this is ignored when div=1

inline void set_PHASE_FLIP() volatile#

Set PHASE’s FLIP bit.

invert the phase-shifted output

this is ignored when div=1

inline void clear_PHASE_FLIP() volatile#

Clear PHASE’s FLIP bit.

invert the phase-shifted output

this is ignored when div=1

inline void toggle_PHASE_FLIP() volatile#

Toggle PHASE’s FLIP bit.

invert the phase-shifted output

this is ignored when div=1

inline bool get_PHASE_ENABLE() volatile#

Get PHASE’s ENABLE bit.

enable the phase-shifted output

this can be changed on-the-fly

inline void set_PHASE_ENABLE() volatile#

Set PHASE’s ENABLE bit.

enable the phase-shifted output

this can be changed on-the-fly

inline void clear_PHASE_ENABLE() volatile#

Clear PHASE’s ENABLE bit.

enable the phase-shifted output

this can be changed on-the-fly

inline void toggle_PHASE_ENABLE() volatile#

Toggle PHASE’s ENABLE bit.

enable the phase-shifted output

this can be changed on-the-fly

inline uint8_t get_PHASE_PASSWD() volatile#

Get PHASE’s PASSWD field.

set to 0xaa

any other value enables the output with shift=0

inline void set_PHASE_PASSWD(uint8_t value) volatile#

Set PHASE’s PASSWD field.

set to 0xaa

any other value enables the output with shift=0

inline void get_PHASE(uint8_t &SHIFT, bool &FLIP, bool &ENABLE, uint8_t &PASSWD) volatile#

Get all of PHASE’s bit fields.

(read-write) Controls the phase shifted output

inline void set_PHASE(uint8_t SHIFT, bool FLIP, bool ENABLE, uint8_t PASSWD) volatile#

Set all of PHASE’s bit fields.

(read-write) Controls the phase shifted output

inline bool get_STATUS_ENABLED() volatile#

Get STATUS’s ENABLED bit.

Oscillator is enabled but not necessarily running and stable

this resets to 0 but transitions to 1 during chip startup

inline bool get_STATUS_DIV_RUNNING() volatile#

Get STATUS’s DIV_RUNNING bit.

post-divider is running

this resets to 0 but transitions to 1 during chip startup

inline bool get_STATUS_BADWRITE() volatile#

Get STATUS’s BADWRITE bit.

An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT

inline void set_STATUS_BADWRITE() volatile#

Set STATUS’s BADWRITE bit.

An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT

inline void clear_STATUS_BADWRITE() volatile#

Clear STATUS’s BADWRITE bit.

An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT

inline void toggle_STATUS_BADWRITE() volatile#

Toggle STATUS’s BADWRITE bit.

An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT

inline bool get_STATUS_STABLE() volatile#

Get STATUS’s STABLE bit.

Oscillator is running and stable

inline void get_STATUS(bool &ENABLED, bool &DIV_RUNNING, bool &BADWRITE, bool &STABLE) volatile#

Get all of STATUS’s bit fields.

(read-write) Ring Oscillator Status

inline bool get_RANDOMBIT_RANDOMBIT() volatile#

Get RANDOMBIT’s RANDOMBIT bit.

inline uint8_t get_COUNT_COUNT() volatile#

Get COUNT’s COUNT field.

inline void set_COUNT_COUNT(uint8_t value) volatile#

Set COUNT’s COUNT field.

Public Members

uint32_t CTRL#

(read-write) Ring Oscillator control

uint32_t FREQA#

(read-write) The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage

The drive strength has 4 levels determined by the number of bits set

Increasing the number of bits set increases the drive strength and increases the oscillation frequency

0 bits set is the default drive strength

1 bit set doubles the drive strength

2 bits set triples drive strength

3 bits set quadruples drive strength

uint32_t FREQB#

(read-write) For a detailed description see freqa register

uint32_t DORMANT#

(read-write) Ring Oscillator pause control

This is used to save power by pausing the ROSC

On power-up this field is initialised to WAKE

An invalid write will also select WAKE

Warning: setup the irq before selecting dormant mode

uint32_t DIV#

(read-write) Controls the output divider

uint32_t PHASE#

(read-write) Controls the phase shifted output

uint32_t STATUS#

(read-write) Ring Oscillator Status

const uint32_t RANDOMBIT = {}#

(read-only) This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency

uint32_t COUNT#

(read-write) A down counter running at the ROSC frequency which counts to zero and stops.

To start the counter write a non-zero value.

Can be used for short software pauses when setting up time sensitive hardware.

Public Static Attributes

static constexpr std::size_t size = 36#

rosc’s size in bytes.