Struct pll_sys#

Struct Documentation#

struct pll_sys#

Public Functions

inline uint8_t get_CS_REFDIV() volatile#

Get CS’s REFDIV field.

Divides the PLL input reference clock.

Behaviour is undefined for div=0.

PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.

inline void set_CS_REFDIV(uint8_t value) volatile#

Set CS’s REFDIV field.

Divides the PLL input reference clock.

Behaviour is undefined for div=0.

PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.

inline bool get_CS_BYPASS() volatile#

Get CS’s BYPASS bit.

Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.

inline void set_CS_BYPASS() volatile#

Set CS’s BYPASS bit.

Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.

inline void clear_CS_BYPASS() volatile#

Clear CS’s BYPASS bit.

Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.

inline void toggle_CS_BYPASS() volatile#

Toggle CS’s BYPASS bit.

Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.

inline bool get_CS_LOCK() volatile#

Get CS’s LOCK bit.

PLL is locked

inline void get_CS(uint8_t &REFDIV, bool &BYPASS, bool &LOCK) volatile#

Get all of CS’s bit fields.

(read-write) Control and Status

GENERAL CONSTRAINTS:

Reference clock frequency min=5MHz, max=800MHz

Feedback divider min=16, max=320

VCO frequency min=750MHz, max=1600MHz

inline void set_CS(uint8_t REFDIV, bool BYPASS) volatile#

Set all of CS’s bit fields.

(read-write) Control and Status

GENERAL CONSTRAINTS:

Reference clock frequency min=5MHz, max=800MHz

Feedback divider min=16, max=320

VCO frequency min=750MHz, max=1600MHz

inline bool get_PWR_PD() volatile#

Get PWR’s PD bit.

PLL powerdown

To save power set high when PLL output not required.

inline void set_PWR_PD() volatile#

Set PWR’s PD bit.

PLL powerdown

To save power set high when PLL output not required.

inline void clear_PWR_PD() volatile#

Clear PWR’s PD bit.

PLL powerdown

To save power set high when PLL output not required.

inline void toggle_PWR_PD() volatile#

Toggle PWR’s PD bit.

PLL powerdown

To save power set high when PLL output not required.

inline bool get_PWR_DSMPD() volatile#

Get PWR’s DSMPD bit.

PLL DSM powerdown

Nothing is achieved by setting this low.

inline void set_PWR_DSMPD() volatile#

Set PWR’s DSMPD bit.

PLL DSM powerdown

Nothing is achieved by setting this low.

inline void clear_PWR_DSMPD() volatile#

Clear PWR’s DSMPD bit.

PLL DSM powerdown

Nothing is achieved by setting this low.

inline void toggle_PWR_DSMPD() volatile#

Toggle PWR’s DSMPD bit.

PLL DSM powerdown

Nothing is achieved by setting this low.

inline bool get_PWR_POSTDIVPD() volatile#

Get PWR’s POSTDIVPD bit.

PLL post divider powerdown

To save power set high when PLL output not required or bypass=1.

inline void set_PWR_POSTDIVPD() volatile#

Set PWR’s POSTDIVPD bit.

PLL post divider powerdown

To save power set high when PLL output not required or bypass=1.

inline void clear_PWR_POSTDIVPD() volatile#

Clear PWR’s POSTDIVPD bit.

PLL post divider powerdown

To save power set high when PLL output not required or bypass=1.

inline void toggle_PWR_POSTDIVPD() volatile#

Toggle PWR’s POSTDIVPD bit.

PLL post divider powerdown

To save power set high when PLL output not required or bypass=1.

inline bool get_PWR_VCOPD() volatile#

Get PWR’s VCOPD bit.

PLL VCO powerdown

To save power set high when PLL output not required or bypass=1.

inline void set_PWR_VCOPD() volatile#

Set PWR’s VCOPD bit.

PLL VCO powerdown

To save power set high when PLL output not required or bypass=1.

inline void clear_PWR_VCOPD() volatile#

Clear PWR’s VCOPD bit.

PLL VCO powerdown

To save power set high when PLL output not required or bypass=1.

inline void toggle_PWR_VCOPD() volatile#

Toggle PWR’s VCOPD bit.

PLL VCO powerdown

To save power set high when PLL output not required or bypass=1.

inline void get_PWR(bool &PD, bool &DSMPD, bool &POSTDIVPD, bool &VCOPD) volatile#

Get all of PWR’s bit fields.

(read-write) Controls the PLL power modes.

inline void set_PWR(bool PD, bool DSMPD, bool POSTDIVPD, bool VCOPD) volatile#

Set all of PWR’s bit fields.

(read-write) Controls the PLL power modes.

inline uint16_t get_FBDIV_INT_FBDIV_INT() volatile#

Get FBDIV_INT’s FBDIV_INT field.

see ctrl reg description for constraints

inline void set_FBDIV_INT_FBDIV_INT(uint16_t value) volatile#

Set FBDIV_INT’s FBDIV_INT field.

see ctrl reg description for constraints

inline uint8_t get_PRIM_POSTDIV2() volatile#

Get PRIM’s POSTDIV2 field.

divide by 1-7

inline void set_PRIM_POSTDIV2(uint8_t value) volatile#

Set PRIM’s POSTDIV2 field.

divide by 1-7

inline uint8_t get_PRIM_POSTDIV1() volatile#

Get PRIM’s POSTDIV1 field.

divide by 1-7

inline void set_PRIM_POSTDIV1(uint8_t value) volatile#

Set PRIM’s POSTDIV1 field.

divide by 1-7

inline void get_PRIM(uint8_t &POSTDIV2, uint8_t &POSTDIV1) volatile#

Get all of PRIM’s bit fields.

(read-write) Controls the PLL post dividers for the primary output

(note: this PLL does not have a secondary output)

the primary output is driven from VCO divided by postdiv1*postdiv2

inline void set_PRIM(uint8_t POSTDIV2, uint8_t POSTDIV1) volatile#

Set all of PRIM’s bit fields.

(read-write) Controls the PLL post dividers for the primary output

(note: this PLL does not have a secondary output)

the primary output is driven from VCO divided by postdiv1*postdiv2

Public Members

uint32_t CS#

(read-write) Control and Status

GENERAL CONSTRAINTS:

Reference clock frequency min=5MHz, max=800MHz

Feedback divider min=16, max=320

VCO frequency min=750MHz, max=1600MHz

uint32_t PWR#

(read-write) Controls the PLL power modes.

uint32_t FBDIV_INT#

(read-write) Feedback divisor

(note: this PLL does not support fractional division)

uint32_t PRIM#

(read-write) Controls the PLL post dividers for the primary output

(note: this PLL does not have a secondary output)

the primary output is driven from VCO divided by postdiv1*postdiv2

Public Static Attributes

static constexpr std::size_t size = 16#

pll_sys’s size in bytes.