Struct spi0#

Defined in File spi0.h

Struct Documentation#

struct spi0#

Public Functions

inline uint8_t get_SSPCR0_DSS() volatile#

Get SSPCR0’s DSS field.

Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.

inline void set_SSPCR0_DSS(uint8_t value) volatile#

Set SSPCR0’s DSS field.

inline uint8_t get_SSPCR0_FRF() volatile#

Get SSPCR0’s FRF field.

Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.

inline void set_SSPCR0_FRF(uint8_t value) volatile#

Set SSPCR0’s FRF field.

Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.

inline bool get_SSPCR0_SPO() volatile#

Get SSPCR0’s SPO bit.

SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.

inline void set_SSPCR0_SPO() volatile#

Set SSPCR0’s SPO bit.

SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.

inline void clear_SSPCR0_SPO() volatile#

Clear SSPCR0’s SPO bit.

SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.

inline void toggle_SSPCR0_SPO() volatile#

Toggle SSPCR0’s SPO bit.

SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.

inline bool get_SSPCR0_SPH() volatile#

Get SSPCR0’s SPH bit.

SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.

inline void set_SSPCR0_SPH() volatile#

Set SSPCR0’s SPH bit.

SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.

inline void clear_SSPCR0_SPH() volatile#

Clear SSPCR0’s SPH bit.

SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.

inline void toggle_SSPCR0_SPH() volatile#

Toggle SSPCR0’s SPH bit.

SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.

inline uint8_t get_SSPCR0_SCR() volatile#

Get SSPCR0’s SCR field.

Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.

inline void set_SSPCR0_SCR(uint8_t value) volatile#

Set SSPCR0’s SCR field.

inline void get_SSPCR0(uint8_t &DSS, uint8_t &FRF, bool &SPO, bool &SPH, uint8_t &SCR) volatile#

Get all of SSPCR0’s bit fields.

(read-write) Control register 0, SSPCR0 on page 3-4

inline void set_SSPCR0(uint8_t DSS, uint8_t FRF, bool SPO, bool SPH, uint8_t SCR) volatile#

Set all of SSPCR0’s bit fields.

(read-write) Control register 0, SSPCR0 on page 3-4

inline bool get_SSPCR1_LBM() volatile#

Get SSPCR1’s LBM bit.

Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.

inline void set_SSPCR1_LBM() volatile#

Set SSPCR1’s LBM bit.

Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.

inline void clear_SSPCR1_LBM() volatile#

Clear SSPCR1’s LBM bit.

Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.

inline void toggle_SSPCR1_LBM() volatile#

Toggle SSPCR1’s LBM bit.

Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.

inline bool get_SSPCR1_SSE() volatile#

Get SSPCR1’s SSE bit.

Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.

inline void set_SSPCR1_SSE() volatile#

Set SSPCR1’s SSE bit.

Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.

inline void clear_SSPCR1_SSE() volatile#

Clear SSPCR1’s SSE bit.

Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.

inline void toggle_SSPCR1_SSE() volatile#

Toggle SSPCR1’s SSE bit.

Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.

inline bool get_SSPCR1_MS() volatile#

Get SSPCR1’s MS bit.

Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.

inline void set_SSPCR1_MS() volatile#

Set SSPCR1’s MS bit.

Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.

inline void clear_SSPCR1_MS() volatile#

Clear SSPCR1’s MS bit.

Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.

inline void toggle_SSPCR1_MS() volatile#

Toggle SSPCR1’s MS bit.

Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.

inline bool get_SSPCR1_SOD() volatile#

Get SSPCR1’s SOD bit.

Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.

inline void set_SSPCR1_SOD() volatile#

Set SSPCR1’s SOD bit.

inline void clear_SSPCR1_SOD() volatile#

Clear SSPCR1’s SOD bit.

inline void toggle_SSPCR1_SOD() volatile#

Toggle SSPCR1’s SOD bit.

inline void get_SSPCR1(bool &LBM, bool &SSE, bool &MS, bool &SOD) volatile#

Get all of SSPCR1’s bit fields.

(read-write) Control register 1, SSPCR1 on page 3-5

inline void set_SSPCR1(bool LBM, bool SSE, bool MS, bool SOD) volatile#

Set all of SSPCR1’s bit fields.

(read-write) Control register 1, SSPCR1 on page 3-5

inline uint16_t get_SSPDR_DATA() volatile#

Get SSPDR’s DATA field.

Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.

inline void set_SSPDR_DATA(uint16_t value) volatile#

Set SSPDR’s DATA field.

inline bool get_SSPSR_TFE() volatile#

Get SSPSR’s TFE bit.

Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.

inline bool get_SSPSR_TNF() volatile#

Get SSPSR’s TNF bit.

Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full.

inline bool get_SSPSR_RNE() volatile#

Get SSPSR’s RNE bit.

Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty.

inline bool get_SSPSR_RFF() volatile#

Get SSPSR’s RFF bit.

Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.

inline bool get_SSPSR_BSY() volatile#

Get SSPSR’s BSY bit.

PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.

inline void get_SSPSR(bool &TFE, bool &TNF, bool &RNE, bool &RFF, bool &BSY) volatile#

Get all of SSPSR’s bit fields.

(read-only) Status register, SSPSR on page 3-7

inline uint8_t get_SSPCPSR_CPSDVSR() volatile#

Get SSPCPSR’s CPSDVSR field.

Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.

inline void set_SSPCPSR_CPSDVSR(uint8_t value) volatile#

Set SSPCPSR’s CPSDVSR field.

Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.

inline bool get_SSPIMSC_RORIM() volatile#

Get SSPIMSC’s RORIM bit.

Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.

inline void set_SSPIMSC_RORIM() volatile#

Set SSPIMSC’s RORIM bit.

Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.

inline void clear_SSPIMSC_RORIM() volatile#

Clear SSPIMSC’s RORIM bit.

Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.

inline void toggle_SSPIMSC_RORIM() volatile#

Toggle SSPIMSC’s RORIM bit.

Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.

inline bool get_SSPIMSC_RTIM() volatile#

Get SSPIMSC’s RTIM bit.

Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.

inline void set_SSPIMSC_RTIM() volatile#

Set SSPIMSC’s RTIM bit.

Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.

inline void clear_SSPIMSC_RTIM() volatile#

Clear SSPIMSC’s RTIM bit.

Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.

inline void toggle_SSPIMSC_RTIM() volatile#

Toggle SSPIMSC’s RTIM bit.

Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.

inline bool get_SSPIMSC_RXIM() volatile#

Get SSPIMSC’s RXIM bit.

Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.

inline void set_SSPIMSC_RXIM() volatile#

Set SSPIMSC’s RXIM bit.

Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.

inline void clear_SSPIMSC_RXIM() volatile#

Clear SSPIMSC’s RXIM bit.

Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.

inline void toggle_SSPIMSC_RXIM() volatile#

Toggle SSPIMSC’s RXIM bit.

Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.

inline bool get_SSPIMSC_TXIM() volatile#

Get SSPIMSC’s TXIM bit.

Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.

inline void set_SSPIMSC_TXIM() volatile#

Set SSPIMSC’s TXIM bit.

Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.

inline void clear_SSPIMSC_TXIM() volatile#

Clear SSPIMSC’s TXIM bit.

Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.

inline void toggle_SSPIMSC_TXIM() volatile#

Toggle SSPIMSC’s TXIM bit.

Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.

inline void get_SSPIMSC(bool &RORIM, bool &RTIM, bool &RXIM, bool &TXIM) volatile#

Get all of SSPIMSC’s bit fields.

(read-write) Interrupt mask set or clear register, SSPIMSC on page 3-9

inline void set_SSPIMSC(bool RORIM, bool RTIM, bool RXIM, bool TXIM) volatile#

Set all of SSPIMSC’s bit fields.

(read-write) Interrupt mask set or clear register, SSPIMSC on page 3-9

inline bool get_SSPRIS_RORRIS() volatile#

Get SSPRIS’s RORRIS bit.

Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt

inline bool get_SSPRIS_RTRIS() volatile#

Get SSPRIS’s RTRIS bit.

Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt

inline bool get_SSPRIS_RXRIS() volatile#

Get SSPRIS’s RXRIS bit.

Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt

inline bool get_SSPRIS_TXRIS() volatile#

Get SSPRIS’s TXRIS bit.

Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt

inline void get_SSPRIS(bool &RORRIS, bool &RTRIS, bool &RXRIS, bool &TXRIS) volatile#

Get all of SSPRIS’s bit fields.

(read-only) Raw interrupt status register, SSPRIS on page 3-10

inline bool get_SSPMIS_RORMIS() volatile#

Get SSPMIS’s RORMIS bit.

Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt

inline bool get_SSPMIS_RTMIS() volatile#

Get SSPMIS’s RTMIS bit.

Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt

inline bool get_SSPMIS_RXMIS() volatile#

Get SSPMIS’s RXMIS bit.

Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt

inline bool get_SSPMIS_TXMIS() volatile#

Get SSPMIS’s TXMIS bit.

Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt

inline void get_SSPMIS(bool &RORMIS, bool &RTMIS, bool &RXMIS, bool &TXMIS) volatile#

Get all of SSPMIS’s bit fields.

(read-only) Masked interrupt status register, SSPMIS on page 3-11

inline bool get_SSPICR_RORIC() volatile#

Get SSPICR’s RORIC bit.

Clears the SSPRORINTR interrupt

inline void set_SSPICR_RORIC() volatile#

Set SSPICR’s RORIC bit.

Clears the SSPRORINTR interrupt

inline void clear_SSPICR_RORIC() volatile#

Clear SSPICR’s RORIC bit.

Clears the SSPRORINTR interrupt

inline void toggle_SSPICR_RORIC() volatile#

Toggle SSPICR’s RORIC bit.

Clears the SSPRORINTR interrupt

inline bool get_SSPICR_RTIC() volatile#

Get SSPICR’s RTIC bit.

Clears the SSPRTINTR interrupt

inline void set_SSPICR_RTIC() volatile#

Set SSPICR’s RTIC bit.

Clears the SSPRTINTR interrupt

inline void clear_SSPICR_RTIC() volatile#

Clear SSPICR’s RTIC bit.

Clears the SSPRTINTR interrupt

inline void toggle_SSPICR_RTIC() volatile#

Toggle SSPICR’s RTIC bit.

Clears the SSPRTINTR interrupt

inline void get_SSPICR(bool &RORIC, bool &RTIC) volatile#

Get all of SSPICR’s bit fields.

(read-write) Interrupt clear register, SSPICR on page 3-11

inline void set_SSPICR(bool RORIC, bool RTIC) volatile#

Set all of SSPICR’s bit fields.

(read-write) Interrupt clear register, SSPICR on page 3-11

inline bool get_SSPDMACR_RXDMAE() volatile#

Get SSPDMACR’s RXDMAE bit.

Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.

inline void set_SSPDMACR_RXDMAE() volatile#

Set SSPDMACR’s RXDMAE bit.

Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.

inline void clear_SSPDMACR_RXDMAE() volatile#

Clear SSPDMACR’s RXDMAE bit.

Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.

inline void toggle_SSPDMACR_RXDMAE() volatile#

Toggle SSPDMACR’s RXDMAE bit.

Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.

inline bool get_SSPDMACR_TXDMAE() volatile#

Get SSPDMACR’s TXDMAE bit.

Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.

inline void set_SSPDMACR_TXDMAE() volatile#

Set SSPDMACR’s TXDMAE bit.

Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.

inline void clear_SSPDMACR_TXDMAE() volatile#

Clear SSPDMACR’s TXDMAE bit.

Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.

inline void toggle_SSPDMACR_TXDMAE() volatile#

Toggle SSPDMACR’s TXDMAE bit.

Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.

inline void get_SSPDMACR(bool &RXDMAE, bool &TXDMAE) volatile#

Get all of SSPDMACR’s bit fields.

(read-write) DMA control register, SSPDMACR on page 3-12

inline void set_SSPDMACR(bool RXDMAE, bool TXDMAE) volatile#

Set all of SSPDMACR’s bit fields.

(read-write) DMA control register, SSPDMACR on page 3-12

inline uint8_t get_SSPPERIPHID0_PARTNUMBER0() volatile#

Get SSPPERIPHID0’s PARTNUMBER0 field.

These bits read back as 0x22

inline uint8_t get_SSPPERIPHID1_PARTNUMBER1() volatile#

Get SSPPERIPHID1’s PARTNUMBER1 field.

These bits read back as 0x0

inline uint8_t get_SSPPERIPHID1_DESIGNER0() volatile#

Get SSPPERIPHID1’s DESIGNER0 field.

These bits read back as 0x1

inline void get_SSPPERIPHID1(uint8_t &PARTNUMBER1, uint8_t &DESIGNER0) volatile#

Get all of SSPPERIPHID1’s bit fields.

(read-only) Peripheral identification registers, SSPPeriphID0-3 on page 3-13

inline uint8_t get_SSPPERIPHID2_DESIGNER1() volatile#

Get SSPPERIPHID2’s DESIGNER1 field.

These bits read back as 0x4

inline uint8_t get_SSPPERIPHID2_REVISION() volatile#

Get SSPPERIPHID2’s REVISION field.

These bits return the peripheral revision

inline void get_SSPPERIPHID2(uint8_t &DESIGNER1, uint8_t &REVISION) volatile#

Get all of SSPPERIPHID2’s bit fields.

(read-only) Peripheral identification registers, SSPPeriphID0-3 on page 3-13

inline uint8_t get_SSPPERIPHID3_CONFIGURATION() volatile#

Get SSPPERIPHID3’s CONFIGURATION field.

These bits read back as 0x00

inline uint8_t get_SSPPCELLID0_SSPPCELLID0() volatile#

Get SSPPCELLID0’s SSPPCELLID0 field.

These bits read back as 0x0D

inline uint8_t get_SSPPCELLID1_SSPPCELLID1() volatile#

Get SSPPCELLID1’s SSPPCELLID1 field.

These bits read back as 0xF0

inline uint8_t get_SSPPCELLID2_SSPPCELLID2() volatile#

Get SSPPCELLID2’s SSPPCELLID2 field.

These bits read back as 0x05

inline uint8_t get_SSPPCELLID3_SSPPCELLID3() volatile#

Get SSPPCELLID3’s SSPPCELLID3 field.

These bits read back as 0xB1

Public Members

uint32_t SSPCR0#: (read-write) Control register 0, SSPCR0 on page 3-4

uint32_t SSPCR1#: (read-write) Control register 1, SSPCR1 on page 3-5

uint32_t SSPDR#: (read-write) Data register, SSPDR on page 3-6

const uint32_t SSPSR = {}#: (read-only) Status register, SSPSR on page 3-7

uint32_t SSPCPSR#: (read-write) Clock prescale register, SSPCPSR on page 3-8

uint32_t SSPIMSC#: (read-write) Interrupt mask set or clear register, SSPIMSC on page 3-9

const uint32_t SSPRIS = {}#: (read-only) Raw interrupt status register, SSPRIS on page 3-10

const uint32_t SSPMIS = {}#: (read-only) Masked interrupt status register, SSPMIS on page 3-11

uint32_t SSPICR#: (read-write) Interrupt clear register, SSPICR on page 3-11

uint32_t SSPDMACR#: (read-write) DMA control register, SSPDMACR on page 3-12

const uint32_t reserved_padding0[reserved_padding0_length] = {}#

const uint32_t SSPPERIPHID0 = {}#: (read-only) Peripheral identification registers, SSPPeriphID0-3 on page 3-13

const uint32_t SSPPERIPHID1 = {}#: (read-only) Peripheral identification registers, SSPPeriphID0-3 on page 3-13

const uint32_t SSPPERIPHID2 = {}#: (read-only) Peripheral identification registers, SSPPeriphID0-3 on page 3-13

const uint32_t SSPPERIPHID3 = {}#: (read-only) Peripheral identification registers, SSPPeriphID0-3 on page 3-13

const uint32_t SSPPCELLID0 = {}#: (read-only) PrimeCell identification registers, SSPPCellID0-3 on page 3-16

const uint32_t SSPPCELLID1 = {}#: (read-only) PrimeCell identification registers, SSPPCellID0-3 on page 3-16

const uint32_t SSPPCELLID2 = {}#: (read-only) PrimeCell identification registers, SSPPCellID0-3 on page 3-16

const uint32_t SSPPCELLID3 = {}#: (read-only) PrimeCell identification registers, SSPPCellID0-3 on page 3-16

Public Static Attributes

static constexpr std::size_t size = 4096#: spi0’s size in bytes.

static constexpr std::size_t reserved_padding0_length = 1006#

Struct spi0

Contents

Struct spi0#

Struct Documentation#