Struct xip_ctrl#

Struct Documentation#

struct xip_ctrl#

QSPI flash execute-in-place block

Public Functions

inline bool get_CTRL_EN() volatile#

Get CTRL’s EN bit.

When 1, enable the cache. When the cache is disabled, all XIP accesses

will go straight to the flash, without querying the cache. When enabled,

cacheable XIP accesses will query the cache, and the flash will

not be accessed if the tag matches and the valid bit is set.

If the cache is enabled, cache-as-SRAM accesses have no effect on the

cache data RAM, and will produce a bus error response.

inline void set_CTRL_EN() volatile#

Set CTRL’s EN bit.

When 1, enable the cache. When the cache is disabled, all XIP accesses

will go straight to the flash, without querying the cache. When enabled,

cacheable XIP accesses will query the cache, and the flash will

not be accessed if the tag matches and the valid bit is set.

If the cache is enabled, cache-as-SRAM accesses have no effect on the

cache data RAM, and will produce a bus error response.

inline void clear_CTRL_EN() volatile#

Clear CTRL’s EN bit.

When 1, enable the cache. When the cache is disabled, all XIP accesses

will go straight to the flash, without querying the cache. When enabled,

cacheable XIP accesses will query the cache, and the flash will

not be accessed if the tag matches and the valid bit is set.

If the cache is enabled, cache-as-SRAM accesses have no effect on the

cache data RAM, and will produce a bus error response.

inline void toggle_CTRL_EN() volatile#

Toggle CTRL’s EN bit.

When 1, enable the cache. When the cache is disabled, all XIP accesses

will go straight to the flash, without querying the cache. When enabled,

cacheable XIP accesses will query the cache, and the flash will

not be accessed if the tag matches and the valid bit is set.

If the cache is enabled, cache-as-SRAM accesses have no effect on the

cache data RAM, and will produce a bus error response.

inline bool get_CTRL_ERR_BADWRITE() volatile#

Get CTRL’s ERR_BADWRITE bit.

When 1, writes to any alias other than 0x0 (caching, allocating)

will produce a bus fault. When 0, these writes are silently ignored.

In either case, writes to the 0x0 alias will deallocate on tag match,

as usual.

inline void set_CTRL_ERR_BADWRITE() volatile#

Set CTRL’s ERR_BADWRITE bit.

When 1, writes to any alias other than 0x0 (caching, allocating)

will produce a bus fault. When 0, these writes are silently ignored.

In either case, writes to the 0x0 alias will deallocate on tag match,

as usual.

inline void clear_CTRL_ERR_BADWRITE() volatile#

Clear CTRL’s ERR_BADWRITE bit.

When 1, writes to any alias other than 0x0 (caching, allocating)

will produce a bus fault. When 0, these writes are silently ignored.

In either case, writes to the 0x0 alias will deallocate on tag match,

as usual.

inline void toggle_CTRL_ERR_BADWRITE() volatile#

Toggle CTRL’s ERR_BADWRITE bit.

When 1, writes to any alias other than 0x0 (caching, allocating)

will produce a bus fault. When 0, these writes are silently ignored.

In either case, writes to the 0x0 alias will deallocate on tag match,

as usual.

inline bool get_CTRL_POWER_DOWN() volatile#

Get CTRL’s POWER_DOWN bit.

When 1, the cache memories are powered down. They retain state,

but can not be accessed. This reduces static power dissipation.

Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot

be enabled when powered down.

Cache-as-SRAM accesses will produce a bus error response when

the cache is powered down.

inline void set_CTRL_POWER_DOWN() volatile#

Set CTRL’s POWER_DOWN bit.

When 1, the cache memories are powered down. They retain state,

but can not be accessed. This reduces static power dissipation.

Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot

be enabled when powered down.

Cache-as-SRAM accesses will produce a bus error response when

the cache is powered down.

inline void clear_CTRL_POWER_DOWN() volatile#

Clear CTRL’s POWER_DOWN bit.

When 1, the cache memories are powered down. They retain state,

but can not be accessed. This reduces static power dissipation.

Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot

be enabled when powered down.

Cache-as-SRAM accesses will produce a bus error response when

the cache is powered down.

inline void toggle_CTRL_POWER_DOWN() volatile#

Toggle CTRL’s POWER_DOWN bit.

When 1, the cache memories are powered down. They retain state,

but can not be accessed. This reduces static power dissipation.

Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot

be enabled when powered down.

Cache-as-SRAM accesses will produce a bus error response when

the cache is powered down.

inline void get_CTRL(bool &EN, bool &ERR_BADWRITE, bool &POWER_DOWN) volatile#

Get all of CTRL’s bit fields.

(read-write) Cache control

inline void set_CTRL(bool EN, bool ERR_BADWRITE, bool POWER_DOWN) volatile#

Set all of CTRL’s bit fields.

(read-write) Cache control

inline bool get_FLUSH_FLUSH() volatile#

Get FLUSH’s FLUSH bit.

Write 1 to flush the cache. This clears the tag memory, but

the data memory retains its contents. (This means cache-as-SRAM

contents is not affected by flush or reset.)

Reading will hold the bus (stall the processor) until the flush

completes. Alternatively STAT can be polled until completion.

inline void set_FLUSH_FLUSH() volatile#

Set FLUSH’s FLUSH bit.

Write 1 to flush the cache. This clears the tag memory, but

the data memory retains its contents. (This means cache-as-SRAM

contents is not affected by flush or reset.)

Reading will hold the bus (stall the processor) until the flush

completes. Alternatively STAT can be polled until completion.

inline void clear_FLUSH_FLUSH() volatile#

Clear FLUSH’s FLUSH bit.

Write 1 to flush the cache. This clears the tag memory, but

the data memory retains its contents. (This means cache-as-SRAM

contents is not affected by flush or reset.)

Reading will hold the bus (stall the processor) until the flush

completes. Alternatively STAT can be polled until completion.

inline void toggle_FLUSH_FLUSH() volatile#

Toggle FLUSH’s FLUSH bit.

Write 1 to flush the cache. This clears the tag memory, but

the data memory retains its contents. (This means cache-as-SRAM

contents is not affected by flush or reset.)

Reading will hold the bus (stall the processor) until the flush

completes. Alternatively STAT can be polled until completion.

inline bool get_STAT_FLUSH_READY() volatile#

Get STAT’s FLUSH_READY bit.

Reads as 0 while a cache flush is in progress, and 1 otherwise.

The cache is flushed whenever the XIP block is reset, and also

when requested via the FLUSH register.

inline bool get_STAT_FIFO_EMPTY() volatile#

Get STAT’s FIFO_EMPTY bit.

When 1, indicates the XIP streaming FIFO is completely empty.

inline bool get_STAT_FIFO_FULL() volatile#

Get STAT’s FIFO_FULL bit.

When 1, indicates the XIP streaming FIFO is completely full.

The streaming FIFO is 2 entries deep, so the full and empty

flag allow its level to be ascertained.

inline void get_STAT(bool &FLUSH_READY, bool &FIFO_EMPTY, bool &FIFO_FULL) volatile#

Get all of STAT’s bit fields.

(read-only) Cache Status

inline uint32_t get_STREAM_ADDR_STREAM_ADDR() volatile#

Get STREAM_ADDR’s STREAM_ADDR field.

The address of the next word to be streamed from flash to the streaming FIFO.

Increments automatically after each flash access.

Write the initial access address here before starting a streaming read.

inline void set_STREAM_ADDR_STREAM_ADDR(uint32_t value) volatile#

Set STREAM_ADDR’s STREAM_ADDR field.

The address of the next word to be streamed from flash to the streaming FIFO.

Increments automatically after each flash access.

Write the initial access address here before starting a streaming read.

inline uint32_t get_STREAM_CTR_STREAM_CTR() volatile#

Get STREAM_CTR’s STREAM_CTR field.

Write a nonzero value to start a streaming read. This will then

progress in the background, using flash idle cycles to transfer

a linear data block from flash to the streaming FIFO.

Decrements automatically (1 at a time) as the stream

progresses, and halts on reaching 0.

Write 0 to halt an in-progress stream, and discard any in-flight

read, so that a new stream can immediately be started (after

draining the FIFO and reinitialising STREAM_ADDR)

inline void set_STREAM_CTR_STREAM_CTR(uint32_t value) volatile#

Set STREAM_CTR’s STREAM_CTR field.

Write a nonzero value to start a streaming read. This will then

progress in the background, using flash idle cycles to transfer

a linear data block from flash to the streaming FIFO.

Decrements automatically (1 at a time) as the stream

progresses, and halts on reaching 0.

Write 0 to halt an in-progress stream, and discard any in-flight

read, so that a new stream can immediately be started (after

draining the FIFO and reinitialising STREAM_ADDR)

Public Members

uint32_t CTRL#

(read-write) Cache control

uint32_t FLUSH#

(read-write) Cache Flush control

const uint32_t STAT = {}#

(read-only) Cache Status

uint32_t CTR_HIT#

(read-write) Cache Hit counter

A 32 bit saturating counter that increments upon each cache hit,

i.e. when an XIP access is serviced directly from cached data.

Write any value to clear.

uint32_t CTR_ACC#

(read-write) Cache Access counter

A 32 bit saturating counter that increments upon each XIP access,

whether the cache is hit or not. This includes noncacheable accesses.

Write any value to clear.

uint32_t STREAM_ADDR#

(read-write) FIFO stream address

uint32_t STREAM_CTR#

(read-write) FIFO stream control

uint32_t STREAM_FIFO#

(read-write) FIFO stream data

Streamed data is buffered here, for retrieval by the system DMA.

This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing

the DMA to bus stalls caused by other XIP traffic.

Public Static Attributes

static constexpr std::size_t size = 32#

xip_ctrl’s size in bytes.