Struct uart0

inline uint8_t get_UARTDR_DATA() volatile#

Get UARTDR’s DATA field.

Receive (read) data character. Transmit (write) data character.

inline void set_UARTDR_DATA(uint8_t value) volatile#

Set UARTDR’s DATA field.

Receive (read) data character. Transmit (write) data character.

inline bool get_UARTDR_FE() volatile#

Get UARTDR’s FE bit.

Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.

inline bool get_UARTDR_PE() volatile#

Get UARTDR’s PE bit.

Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO.

inline bool get_UARTDR_BE() volatile#

Get UARTDR’s BE bit.

Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.

inline bool get_UARTDR_OE() volatile#

Get UARTDR’s OE bit.

Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.

inline void get_UARTDR(uint8_t &DATA, bool &FE, bool &PE, bool &BE, bool &OE) volatile#

Get all of UARTDR’s bit fields.

(read-write) Data Register, UARTDR

inline bool get_UARTRSR_FE() volatile#

Get UARTRSR’s FE bit.

Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.

inline void set_UARTRSR_FE() volatile#

Set UARTRSR’s FE bit.

Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.

inline void clear_UARTRSR_FE() volatile#

Clear UARTRSR’s FE bit.

Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.

inline void toggle_UARTRSR_FE() volatile#

Toggle UARTRSR’s FE bit.

Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.

inline bool get_UARTRSR_PE() volatile#

Get UARTRSR’s PE bit.

Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.

inline void set_UARTRSR_PE() volatile#

Set UARTRSR’s PE bit.

Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.

inline void clear_UARTRSR_PE() volatile#

Clear UARTRSR’s PE bit.

Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.

inline void toggle_UARTRSR_PE() volatile#

Toggle UARTRSR’s PE bit.

Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.

inline bool get_UARTRSR_BE() volatile#

Get UARTRSR’s BE bit.

Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.

inline void set_UARTRSR_BE() volatile#

Set UARTRSR’s BE bit.

Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.

inline void clear_UARTRSR_BE() volatile#

Clear UARTRSR’s BE bit.

Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.

inline void toggle_UARTRSR_BE() volatile#

Toggle UARTRSR’s BE bit.

Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.

inline bool get_UARTRSR_OE() volatile#

Get UARTRSR’s OE bit.

Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.

inline void set_UARTRSR_OE() volatile#

Set UARTRSR’s OE bit.

Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.

inline void clear_UARTRSR_OE() volatile#

Clear UARTRSR’s OE bit.

Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.

inline void toggle_UARTRSR_OE() volatile#

Toggle UARTRSR’s OE bit.

Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.

inline void get_UARTRSR(bool &FE, bool &PE, bool &BE, bool &OE) volatile#

Get all of UARTRSR’s bit fields.

(read-write) Receive Status Register/Error Clear Register, UARTRSR/UARTECR

inline void set_UARTRSR(bool FE, bool PE, bool BE, bool OE) volatile#

Set all of UARTRSR’s bit fields.

(read-write) Receive Status Register/Error Clear Register, UARTRSR/UARTECR

inline bool get_UARTFR_CTS() volatile#

Get UARTFR’s CTS bit.

Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW.

inline bool get_UARTFR_DSR() volatile#

Get UARTFR’s DSR bit.

Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW.

inline bool get_UARTFR_DCD() volatile#

Get UARTFR’s DCD bit.

Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.

inline bool get_UARTFR_BUSY() volatile#

Get UARTFR’s BUSY bit.

UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.

inline bool get_UARTFR_RXFE() volatile#

Get UARTFR’s RXFE bit.

Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.

inline bool get_UARTFR_TXFF() volatile#

Get UARTFR’s TXFF bit.

Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.

inline bool get_UARTFR_RXFF() volatile#

Get UARTFR’s RXFF bit.

Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.

inline bool get_UARTFR_TXFE() volatile#

Get UARTFR’s TXFE bit.

Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.

inline bool get_UARTFR_RI() volatile#

Get UARTFR’s RI bit.

Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW.

inline void get_UARTFR(bool &CTS, bool &DSR, bool &DCD, bool &BUSY, bool &RXFE, bool &TXFF, bool &RXFF, bool &TXFE, bool &RI) volatile#

Get all of UARTFR’s bit fields.

(read-only) Flag Register, UARTFR

inline uint8_t get_UARTILPR_ILPDVSR() volatile#

Get UARTILPR’s ILPDVSR field.

8-bit low-power divisor value. These bits are cleared to 0 at reset.

inline void set_UARTILPR_ILPDVSR(uint8_t value) volatile#

Set UARTILPR’s ILPDVSR field.

8-bit low-power divisor value. These bits are cleared to 0 at reset.

inline uint16_t get_UARTIBRD_BAUD_DIVINT() volatile#

Get UARTIBRD’s BAUD_DIVINT field.

The integer baud rate divisor. These bits are cleared to 0 on reset.

inline void set_UARTIBRD_BAUD_DIVINT(uint16_t value) volatile#

Set UARTIBRD’s BAUD_DIVINT field.

The integer baud rate divisor. These bits are cleared to 0 on reset.

inline uint8_t get_UARTFBRD_BAUD_DIVFRAC() volatile#

Get UARTFBRD’s BAUD_DIVFRAC field.

The fractional baud rate divisor. These bits are cleared to 0 on reset.

inline void set_UARTFBRD_BAUD_DIVFRAC(uint8_t value) volatile#

Set UARTFBRD’s BAUD_DIVFRAC field.

The fractional baud rate divisor. These bits are cleared to 0 on reset.

inline bool get_UARTLCR_H_BRK() volatile#

Get UARTLCR_H’s BRK bit.

Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.

inline void set_UARTLCR_H_BRK() volatile#

Set UARTLCR_H’s BRK bit.

Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.

inline void clear_UARTLCR_H_BRK() volatile#

Clear UARTLCR_H’s BRK bit.

Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.

inline void toggle_UARTLCR_H_BRK() volatile#

Toggle UARTLCR_H’s BRK bit.

Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.

inline bool get_UARTLCR_H_PEN() volatile#

Get UARTLCR_H’s PEN bit.

Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.

inline void set_UARTLCR_H_PEN() volatile#

Set UARTLCR_H’s PEN bit.

Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.

inline void clear_UARTLCR_H_PEN() volatile#

Clear UARTLCR_H’s PEN bit.

Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.

inline void toggle_UARTLCR_H_PEN() volatile#

Toggle UARTLCR_H’s PEN bit.

Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.

inline bool get_UARTLCR_H_EPS() volatile#

Get UARTLCR_H’s EPS bit.

Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.

inline void set_UARTLCR_H_EPS() volatile#

Set UARTLCR_H’s EPS bit.

Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.

inline void clear_UARTLCR_H_EPS() volatile#

Clear UARTLCR_H’s EPS bit.

Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.

inline void toggle_UARTLCR_H_EPS() volatile#

Toggle UARTLCR_H’s EPS bit.

Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.

inline bool get_UARTLCR_H_STP2() volatile#

Get UARTLCR_H’s STP2 bit.

Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.

inline void set_UARTLCR_H_STP2() volatile#

Set UARTLCR_H’s STP2 bit.

Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.

inline void clear_UARTLCR_H_STP2() volatile#

Clear UARTLCR_H’s STP2 bit.

Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.

inline void toggle_UARTLCR_H_STP2() volatile#

Toggle UARTLCR_H’s STP2 bit.

Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.

inline bool get_UARTLCR_H_FEN() volatile#

Get UARTLCR_H’s FEN bit.

Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).

inline void set_UARTLCR_H_FEN() volatile#

Set UARTLCR_H’s FEN bit.

Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).

inline void clear_UARTLCR_H_FEN() volatile#

Clear UARTLCR_H’s FEN bit.

Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).

inline void toggle_UARTLCR_H_FEN() volatile#

Toggle UARTLCR_H’s FEN bit.

Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).

inline uint8_t get_UARTLCR_H_WLEN() volatile#

Get UARTLCR_H’s WLEN field.

Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.

inline void set_UARTLCR_H_WLEN(uint8_t value) volatile#

Set UARTLCR_H’s WLEN field.

Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.

inline bool get_UARTLCR_H_SPS() volatile#

Get UARTLCR_H’s SPS bit.

Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.

inline void set_UARTLCR_H_SPS() volatile#

Set UARTLCR_H’s SPS bit.

Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.

inline void clear_UARTLCR_H_SPS() volatile#

Clear UARTLCR_H’s SPS bit.

Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.

inline void toggle_UARTLCR_H_SPS() volatile#

Toggle UARTLCR_H’s SPS bit.

Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.

inline void get_UARTLCR_H(bool &BRK, bool &PEN, bool &EPS, bool &STP2, bool &FEN, uint8_t &WLEN, bool &SPS) volatile#

Get all of UARTLCR_H’s bit fields.

(read-write) Line Control Register, UARTLCR_H

inline void set_UARTLCR_H(bool BRK, bool PEN, bool EPS, bool STP2, bool FEN, uint8_t WLEN, bool SPS) volatile#

Set all of UARTLCR_H’s bit fields.

(read-write) Line Control Register, UARTLCR_H

inline bool get_UARTCR_UARTEN() volatile#

Get UARTCR’s UARTEN bit.

UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.

inline void set_UARTCR_UARTEN() volatile#

Set UARTCR’s UARTEN bit.

UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.

inline void clear_UARTCR_UARTEN() volatile#

Clear UARTCR’s UARTEN bit.

UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.

inline void toggle_UARTCR_UARTEN() volatile#

Toggle UARTCR’s UARTEN bit.

UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.

inline bool get_UARTCR_SIREN() volatile#

Get UARTCR’s SIREN bit.

SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.

inline void set_UARTCR_SIREN() volatile#

Set UARTCR’s SIREN bit.

SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.

inline void clear_UARTCR_SIREN() volatile#

Clear UARTCR’s SIREN bit.

SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.

inline void toggle_UARTCR_SIREN() volatile#

Toggle UARTCR’s SIREN bit.

SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.

inline bool get_UARTCR_SIRLP() volatile#

Get UARTCR’s SIRLP bit.

SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.

inline void set_UARTCR_SIRLP() volatile#

Set UARTCR’s SIRLP bit.

SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.

inline void clear_UARTCR_SIRLP() volatile#

Clear UARTCR’s SIRLP bit.

SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.

inline void toggle_UARTCR_SIRLP() volatile#

Toggle UARTCR’s SIRLP bit.

SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.

inline bool get_UARTCR_LBE() volatile#

Get UARTCR’s LBE bit.

Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.

inline void set_UARTCR_LBE() volatile#

Set UARTCR’s LBE bit.

Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.

inline void clear_UARTCR_LBE() volatile#

Clear UARTCR’s LBE bit.

Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.

inline void toggle_UARTCR_LBE() volatile#

Toggle UARTCR’s LBE bit.

Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.

inline bool get_UARTCR_TXE() volatile#

Get UARTCR’s TXE bit.

Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.

inline void set_UARTCR_TXE() volatile#

Set UARTCR’s TXE bit.

Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.

inline void clear_UARTCR_TXE() volatile#

Clear UARTCR’s TXE bit.

Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.

inline void toggle_UARTCR_TXE() volatile#

Toggle UARTCR’s TXE bit.

Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.

inline bool get_UARTCR_RXE() volatile#

Get UARTCR’s RXE bit.

Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.

inline void set_UARTCR_RXE() volatile#

Set UARTCR’s RXE bit.

Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.

inline void clear_UARTCR_RXE() volatile#

Clear UARTCR’s RXE bit.

Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.

inline void toggle_UARTCR_RXE() volatile#

Toggle UARTCR’s RXE bit.

Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.

inline bool get_UARTCR_DTR() volatile#

Get UARTCR’s DTR bit.

Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.

inline void set_UARTCR_DTR() volatile#

Set UARTCR’s DTR bit.

Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.

inline void clear_UARTCR_DTR() volatile#

Clear UARTCR’s DTR bit.

Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.

inline void toggle_UARTCR_DTR() volatile#

Toggle UARTCR’s DTR bit.

Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.

inline bool get_UARTCR_RTS() volatile#

Get UARTCR’s RTS bit.

Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.

inline void set_UARTCR_RTS() volatile#

Set UARTCR’s RTS bit.

Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.

inline void clear_UARTCR_RTS() volatile#

Clear UARTCR’s RTS bit.

Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.

inline void toggle_UARTCR_RTS() volatile#

Toggle UARTCR’s RTS bit.

Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.

inline bool get_UARTCR_OUT1() volatile#

Get UARTCR’s OUT1 bit.

This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).

inline void set_UARTCR_OUT1() volatile#

Set UARTCR’s OUT1 bit.

This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).

inline void clear_UARTCR_OUT1() volatile#

Clear UARTCR’s OUT1 bit.

This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).

inline void toggle_UARTCR_OUT1() volatile#

Toggle UARTCR’s OUT1 bit.

This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).

inline bool get_UARTCR_OUT2() volatile#

Get UARTCR’s OUT2 bit.

This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).

inline void set_UARTCR_OUT2() volatile#

Set UARTCR’s OUT2 bit.

This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).

inline void clear_UARTCR_OUT2() volatile#

Clear UARTCR’s OUT2 bit.

This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).

inline void toggle_UARTCR_OUT2() volatile#

Toggle UARTCR’s OUT2 bit.

This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).

inline bool get_UARTCR_RTSEN() volatile#

Get UARTCR’s RTSEN bit.

RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.

inline void set_UARTCR_RTSEN() volatile#

Set UARTCR’s RTSEN bit.

RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.

inline void clear_UARTCR_RTSEN() volatile#

Clear UARTCR’s RTSEN bit.

RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.

inline void toggle_UARTCR_RTSEN() volatile#

Toggle UARTCR’s RTSEN bit.

RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.

inline bool get_UARTCR_CTSEN() volatile#

Get UARTCR’s CTSEN bit.

CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.

inline void set_UARTCR_CTSEN() volatile#

Set UARTCR’s CTSEN bit.

CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.

inline void clear_UARTCR_CTSEN() volatile#

Clear UARTCR’s CTSEN bit.

CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.

inline void toggle_UARTCR_CTSEN() volatile#

Toggle UARTCR’s CTSEN bit.

CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.

inline void get_UARTCR(bool &UARTEN, bool &SIREN, bool &SIRLP, bool &LBE, bool &TXE, bool &RXE, bool &DTR, bool &RTS, bool &OUT1, bool &OUT2, bool &RTSEN, bool &CTSEN) volatile#

Get all of UARTCR’s bit fields.

(read-write) Control Register, UARTCR

inline void set_UARTCR(bool UARTEN, bool SIREN, bool SIRLP, bool LBE, bool TXE, bool RXE, bool DTR, bool RTS, bool OUT1, bool OUT2, bool RTSEN, bool CTSEN) volatile#

Set all of UARTCR’s bit fields.

(read-write) Control Register, UARTCR

inline uint8_t get_UARTIFLS_TXIFLSEL() volatile#

Get UARTIFLS’s TXIFLSEL field.

Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved.

inline void set_UARTIFLS_TXIFLSEL(uint8_t value) volatile#

Set UARTIFLS’s TXIFLSEL field.

Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved.

inline uint8_t get_UARTIFLS_RXIFLSEL() volatile#

Get UARTIFLS’s RXIFLSEL field.

Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved.

inline void set_UARTIFLS_RXIFLSEL(uint8_t value) volatile#

Set UARTIFLS’s RXIFLSEL field.

Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved.

inline void get_UARTIFLS(uint8_t &TXIFLSEL, uint8_t &RXIFLSEL) volatile#

Get all of UARTIFLS’s bit fields.

(read-write) Interrupt FIFO Level Select Register, UARTIFLS

inline void set_UARTIFLS(uint8_t TXIFLSEL, uint8_t RXIFLSEL) volatile#

Set all of UARTIFLS’s bit fields.

(read-write) Interrupt FIFO Level Select Register, UARTIFLS

inline bool get_UARTIMSC_RIMIM() volatile#

Get UARTIMSC’s RIMIM bit.

nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.

inline void set_UARTIMSC_RIMIM() volatile#

Set UARTIMSC’s RIMIM bit.

nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.

inline void clear_UARTIMSC_RIMIM() volatile#

Clear UARTIMSC’s RIMIM bit.

nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.

inline void toggle_UARTIMSC_RIMIM() volatile#

Toggle UARTIMSC’s RIMIM bit.

nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.

inline bool get_UARTIMSC_CTSMIM() volatile#

Get UARTIMSC’s CTSMIM bit.

nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.

inline void set_UARTIMSC_CTSMIM() volatile#

Set UARTIMSC’s CTSMIM bit.

nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.

inline void clear_UARTIMSC_CTSMIM() volatile#

Clear UARTIMSC’s CTSMIM bit.

nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.

inline void toggle_UARTIMSC_CTSMIM() volatile#

Toggle UARTIMSC’s CTSMIM bit.

nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.

inline bool get_UARTIMSC_DCDMIM() volatile#

Get UARTIMSC’s DCDMIM bit.

nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.

inline void set_UARTIMSC_DCDMIM() volatile#

Set UARTIMSC’s DCDMIM bit.

nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.

inline void clear_UARTIMSC_DCDMIM() volatile#

Clear UARTIMSC’s DCDMIM bit.

nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.

inline void toggle_UARTIMSC_DCDMIM() volatile#

Toggle UARTIMSC’s DCDMIM bit.

nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.

inline bool get_UARTIMSC_DSRMIM() volatile#

Get UARTIMSC’s DSRMIM bit.

nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.

inline void set_UARTIMSC_DSRMIM() volatile#

Set UARTIMSC’s DSRMIM bit.

nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.

inline void clear_UARTIMSC_DSRMIM() volatile#

Clear UARTIMSC’s DSRMIM bit.

nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.

inline void toggle_UARTIMSC_DSRMIM() volatile#

Toggle UARTIMSC’s DSRMIM bit.

nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.

inline bool get_UARTIMSC_RXIM() volatile#

Get UARTIMSC’s RXIM bit.

Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.

inline void set_UARTIMSC_RXIM() volatile#

Set UARTIMSC’s RXIM bit.

Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.

inline void clear_UARTIMSC_RXIM() volatile#

Clear UARTIMSC’s RXIM bit.

Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.

inline void toggle_UARTIMSC_RXIM() volatile#

Toggle UARTIMSC’s RXIM bit.

Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.

inline bool get_UARTIMSC_TXIM() volatile#

Get UARTIMSC’s TXIM bit.

Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.

inline void set_UARTIMSC_TXIM() volatile#

Set UARTIMSC’s TXIM bit.

Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.

inline void clear_UARTIMSC_TXIM() volatile#

Clear UARTIMSC’s TXIM bit.

Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.

inline void toggle_UARTIMSC_TXIM() volatile#

Toggle UARTIMSC’s TXIM bit.

Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.

inline bool get_UARTIMSC_RTIM() volatile#

Get UARTIMSC’s RTIM bit.

Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.

inline void set_UARTIMSC_RTIM() volatile#

Set UARTIMSC’s RTIM bit.

Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.

inline void clear_UARTIMSC_RTIM() volatile#

Clear UARTIMSC’s RTIM bit.

Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.

inline void toggle_UARTIMSC_RTIM() volatile#

Toggle UARTIMSC’s RTIM bit.

Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.

inline bool get_UARTIMSC_FEIM() volatile#

Get UARTIMSC’s FEIM bit.

Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.

inline void set_UARTIMSC_FEIM() volatile#

Set UARTIMSC’s FEIM bit.

Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.

inline void clear_UARTIMSC_FEIM() volatile#

Clear UARTIMSC’s FEIM bit.

Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.

inline void toggle_UARTIMSC_FEIM() volatile#

Toggle UARTIMSC’s FEIM bit.

Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.

inline bool get_UARTIMSC_PEIM() volatile#

Get UARTIMSC’s PEIM bit.

Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.

inline void set_UARTIMSC_PEIM() volatile#

Set UARTIMSC’s PEIM bit.

Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.

inline void clear_UARTIMSC_PEIM() volatile#

Clear UARTIMSC’s PEIM bit.

Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.

inline void toggle_UARTIMSC_PEIM() volatile#

Toggle UARTIMSC’s PEIM bit.

Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.

inline bool get_UARTIMSC_BEIM() volatile#

Get UARTIMSC’s BEIM bit.

Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.

inline void set_UARTIMSC_BEIM() volatile#

Set UARTIMSC’s BEIM bit.

Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.

inline void clear_UARTIMSC_BEIM() volatile#

Clear UARTIMSC’s BEIM bit.

Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.

inline void toggle_UARTIMSC_BEIM() volatile#

Toggle UARTIMSC’s BEIM bit.

Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.

inline bool get_UARTIMSC_OEIM() volatile#

Get UARTIMSC’s OEIM bit.

Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.

inline void set_UARTIMSC_OEIM() volatile#

Set UARTIMSC’s OEIM bit.

Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.

inline void clear_UARTIMSC_OEIM() volatile#

Clear UARTIMSC’s OEIM bit.

Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.

inline void toggle_UARTIMSC_OEIM() volatile#

Toggle UARTIMSC’s OEIM bit.

Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.

inline void get_UARTIMSC(bool &RIMIM, bool &CTSMIM, bool &DCDMIM, bool &DSRMIM, bool &RXIM, bool &TXIM, bool &RTIM, bool &FEIM, bool &PEIM, bool &BEIM, bool &OEIM) volatile#

Get all of UARTIMSC’s bit fields.

(read-write) Interrupt Mask Set/Clear Register, UARTIMSC

inline void set_UARTIMSC(bool RIMIM, bool CTSMIM, bool DCDMIM, bool DSRMIM, bool RXIM, bool TXIM, bool RTIM, bool FEIM, bool PEIM, bool BEIM, bool OEIM) volatile#

Set all of UARTIMSC’s bit fields.

(read-write) Interrupt Mask Set/Clear Register, UARTIMSC

inline bool get_UARTRIS_RIRMIS() volatile#

Get UARTRIS’s RIRMIS bit.

nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt.

inline bool get_UARTRIS_CTSRMIS() volatile#

Get UARTRIS’s CTSRMIS bit.

nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt.

inline bool get_UARTRIS_DCDRMIS() volatile#

Get UARTRIS’s DCDRMIS bit.

nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt.

inline bool get_UARTRIS_DSRRMIS() volatile#

Get UARTRIS’s DSRRMIS bit.

nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt.

inline bool get_UARTRIS_RXRIS() volatile#

Get UARTRIS’s RXRIS bit.

Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.

inline bool get_UARTRIS_TXRIS() volatile#

Get UARTRIS’s TXRIS bit.

Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.

inline bool get_UARTRIS_RTRIS() volatile#

Get UARTRIS’s RTRIS bit.

Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a

inline bool get_UARTRIS_FERIS() volatile#

Get UARTRIS’s FERIS bit.

Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.

inline bool get_UARTRIS_PERIS() volatile#

Get UARTRIS’s PERIS bit.

Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.

inline bool get_UARTRIS_BERIS() volatile#

Get UARTRIS’s BERIS bit.

Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.

inline bool get_UARTRIS_OERIS() volatile#

Get UARTRIS’s OERIS bit.

Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.

inline void get_UARTRIS(bool &RIRMIS, bool &CTSRMIS, bool &DCDRMIS, bool &DSRRMIS, bool &RXRIS, bool &TXRIS, bool &RTRIS, bool &FERIS, bool &PERIS, bool &BERIS, bool &OERIS) volatile#

Get all of UARTRIS’s bit fields.

(read-only) Raw Interrupt Status Register, UARTRIS

inline bool get_UARTMIS_RIMMIS() volatile#

Get UARTMIS’s RIMMIS bit.

nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.

inline bool get_UARTMIS_CTSMMIS() volatile#

Get UARTMIS’s CTSMMIS bit.

nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.

inline bool get_UARTMIS_DCDMMIS() volatile#

Get UARTMIS’s DCDMMIS bit.

nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.

inline bool get_UARTMIS_DSRMMIS() volatile#

Get UARTMIS’s DSRMMIS bit.

nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.

inline bool get_UARTMIS_RXMIS() volatile#

Get UARTMIS’s RXMIS bit.

Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.

inline bool get_UARTMIS_TXMIS() volatile#

Get UARTMIS’s TXMIS bit.

Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.

inline bool get_UARTMIS_RTMIS() volatile#

Get UARTMIS’s RTMIS bit.

Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.

inline bool get_UARTMIS_FEMIS() volatile#

Get UARTMIS’s FEMIS bit.

Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.

inline bool get_UARTMIS_PEMIS() volatile#

Get UARTMIS’s PEMIS bit.

Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.

inline bool get_UARTMIS_BEMIS() volatile#

Get UARTMIS’s BEMIS bit.

Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.

inline bool get_UARTMIS_OEMIS() volatile#

Get UARTMIS’s OEMIS bit.

Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.

inline void get_UARTMIS(bool &RIMMIS, bool &CTSMMIS, bool &DCDMMIS, bool &DSRMMIS, bool &RXMIS, bool &TXMIS, bool &RTMIS, bool &FEMIS, bool &PEMIS, bool &BEMIS, bool &OEMIS) volatile#

Get all of UARTMIS’s bit fields.

(read-only) Masked Interrupt Status Register, UARTMIS

inline bool get_UARTICR_RIMIC() volatile#

Get UARTICR’s RIMIC bit.

nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.

inline void set_UARTICR_RIMIC() volatile#

Set UARTICR’s RIMIC bit.

nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.

inline void clear_UARTICR_RIMIC() volatile#

Clear UARTICR’s RIMIC bit.

nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.

inline void toggle_UARTICR_RIMIC() volatile#

Toggle UARTICR’s RIMIC bit.

nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.

inline bool get_UARTICR_CTSMIC() volatile#

Get UARTICR’s CTSMIC bit.

nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.

inline void set_UARTICR_CTSMIC() volatile#

Set UARTICR’s CTSMIC bit.

nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.

inline void clear_UARTICR_CTSMIC() volatile#

Clear UARTICR’s CTSMIC bit.

nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.

inline void toggle_UARTICR_CTSMIC() volatile#

Toggle UARTICR’s CTSMIC bit.

nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.

inline bool get_UARTICR_DCDMIC() volatile#

Get UARTICR’s DCDMIC bit.

nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.

inline void set_UARTICR_DCDMIC() volatile#

Set UARTICR’s DCDMIC bit.

nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.

inline void clear_UARTICR_DCDMIC() volatile#

Clear UARTICR’s DCDMIC bit.

nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.

inline void toggle_UARTICR_DCDMIC() volatile#

Toggle UARTICR’s DCDMIC bit.

nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.

inline bool get_UARTICR_DSRMIC() volatile#

Get UARTICR’s DSRMIC bit.

nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.

inline void set_UARTICR_DSRMIC() volatile#

Set UARTICR’s DSRMIC bit.

nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.

inline void clear_UARTICR_DSRMIC() volatile#

Clear UARTICR’s DSRMIC bit.

nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.

inline void toggle_UARTICR_DSRMIC() volatile#

Toggle UARTICR’s DSRMIC bit.

nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.

inline bool get_UARTICR_RXIC() volatile#

Get UARTICR’s RXIC bit.

Receive interrupt clear. Clears the UARTRXINTR interrupt.

inline void set_UARTICR_RXIC() volatile#

Set UARTICR’s RXIC bit.

Receive interrupt clear. Clears the UARTRXINTR interrupt.

inline void clear_UARTICR_RXIC() volatile#

Clear UARTICR’s RXIC bit.

Receive interrupt clear. Clears the UARTRXINTR interrupt.

inline void toggle_UARTICR_RXIC() volatile#

Toggle UARTICR’s RXIC bit.

Receive interrupt clear. Clears the UARTRXINTR interrupt.

inline bool get_UARTICR_TXIC() volatile#

Get UARTICR’s TXIC bit.

Transmit interrupt clear. Clears the UARTTXINTR interrupt.

inline void set_UARTICR_TXIC() volatile#

Set UARTICR’s TXIC bit.

Transmit interrupt clear. Clears the UARTTXINTR interrupt.

inline void clear_UARTICR_TXIC() volatile#

Clear UARTICR’s TXIC bit.

Transmit interrupt clear. Clears the UARTTXINTR interrupt.

inline void toggle_UARTICR_TXIC() volatile#

Toggle UARTICR’s TXIC bit.

Transmit interrupt clear. Clears the UARTTXINTR interrupt.

inline bool get_UARTICR_RTIC() volatile#

Get UARTICR’s RTIC bit.

Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.

inline void set_UARTICR_RTIC() volatile#

Set UARTICR’s RTIC bit.

Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.

inline void clear_UARTICR_RTIC() volatile#

Clear UARTICR’s RTIC bit.

Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.

inline void toggle_UARTICR_RTIC() volatile#

Toggle UARTICR’s RTIC bit.

Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.

inline bool get_UARTICR_FEIC() volatile#

Get UARTICR’s FEIC bit.

Framing error interrupt clear. Clears the UARTFEINTR interrupt.

inline void set_UARTICR_FEIC() volatile#

Set UARTICR’s FEIC bit.

Framing error interrupt clear. Clears the UARTFEINTR interrupt.

inline void clear_UARTICR_FEIC() volatile#

Clear UARTICR’s FEIC bit.

Framing error interrupt clear. Clears the UARTFEINTR interrupt.

inline void toggle_UARTICR_FEIC() volatile#

Toggle UARTICR’s FEIC bit.

Framing error interrupt clear. Clears the UARTFEINTR interrupt.

inline bool get_UARTICR_PEIC() volatile#

Get UARTICR’s PEIC bit.

Parity error interrupt clear. Clears the UARTPEINTR interrupt.

inline void set_UARTICR_PEIC() volatile#

Set UARTICR’s PEIC bit.

Parity error interrupt clear. Clears the UARTPEINTR interrupt.

inline void clear_UARTICR_PEIC() volatile#

Clear UARTICR’s PEIC bit.

Parity error interrupt clear. Clears the UARTPEINTR interrupt.

inline void toggle_UARTICR_PEIC() volatile#

Toggle UARTICR’s PEIC bit.

Parity error interrupt clear. Clears the UARTPEINTR interrupt.

inline bool get_UARTICR_BEIC() volatile#

Get UARTICR’s BEIC bit.

Break error interrupt clear. Clears the UARTBEINTR interrupt.

inline void set_UARTICR_BEIC() volatile#

Set UARTICR’s BEIC bit.

Break error interrupt clear. Clears the UARTBEINTR interrupt.

inline void clear_UARTICR_BEIC() volatile#

Clear UARTICR’s BEIC bit.

Break error interrupt clear. Clears the UARTBEINTR interrupt.

inline void toggle_UARTICR_BEIC() volatile#

Toggle UARTICR’s BEIC bit.

Break error interrupt clear. Clears the UARTBEINTR interrupt.

inline bool get_UARTICR_OEIC() volatile#

Get UARTICR’s OEIC bit.

Overrun error interrupt clear. Clears the UARTOEINTR interrupt.

inline void set_UARTICR_OEIC() volatile#

Set UARTICR’s OEIC bit.

Overrun error interrupt clear. Clears the UARTOEINTR interrupt.

inline void clear_UARTICR_OEIC() volatile#

Clear UARTICR’s OEIC bit.

Overrun error interrupt clear. Clears the UARTOEINTR interrupt.

inline void toggle_UARTICR_OEIC() volatile#

Toggle UARTICR’s OEIC bit.

Overrun error interrupt clear. Clears the UARTOEINTR interrupt.

inline void get_UARTICR(bool &RIMIC, bool &CTSMIC, bool &DCDMIC, bool &DSRMIC, bool &RXIC, bool &TXIC, bool &RTIC, bool &FEIC, bool &PEIC, bool &BEIC, bool &OEIC) volatile#

Get all of UARTICR’s bit fields.

(read-write) Interrupt Clear Register, UARTICR

inline void set_UARTICR(bool RIMIC, bool CTSMIC, bool DCDMIC, bool DSRMIC, bool RXIC, bool TXIC, bool RTIC, bool FEIC, bool PEIC, bool BEIC, bool OEIC) volatile#

Set all of UARTICR’s bit fields.

(read-write) Interrupt Clear Register, UARTICR

inline bool get_UARTDMACR_RXDMAE() volatile#

Get UARTDMACR’s RXDMAE bit.

Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.

inline void set_UARTDMACR_RXDMAE() volatile#

Set UARTDMACR’s RXDMAE bit.

Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.

inline void clear_UARTDMACR_RXDMAE() volatile#

Clear UARTDMACR’s RXDMAE bit.

Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.

inline void toggle_UARTDMACR_RXDMAE() volatile#

Toggle UARTDMACR’s RXDMAE bit.

Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.

inline bool get_UARTDMACR_TXDMAE() volatile#

Get UARTDMACR’s TXDMAE bit.

Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.

inline void set_UARTDMACR_TXDMAE() volatile#

Set UARTDMACR’s TXDMAE bit.

Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.

inline void clear_UARTDMACR_TXDMAE() volatile#

Clear UARTDMACR’s TXDMAE bit.

Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.

inline void toggle_UARTDMACR_TXDMAE() volatile#

Toggle UARTDMACR’s TXDMAE bit.

Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.

inline bool get_UARTDMACR_DMAONERR() volatile#

Get UARTDMACR’s DMAONERR bit.

DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.

inline void set_UARTDMACR_DMAONERR() volatile#

Set UARTDMACR’s DMAONERR bit.

DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.

inline void clear_UARTDMACR_DMAONERR() volatile#

Clear UARTDMACR’s DMAONERR bit.

DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.

inline void toggle_UARTDMACR_DMAONERR() volatile#

Toggle UARTDMACR’s DMAONERR bit.

DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.

inline void get_UARTDMACR(bool &RXDMAE, bool &TXDMAE, bool &DMAONERR) volatile#

Get all of UARTDMACR’s bit fields.

(read-write) DMA Control Register, UARTDMACR

inline void set_UARTDMACR(bool RXDMAE, bool TXDMAE, bool DMAONERR) volatile#

Set all of UARTDMACR’s bit fields.

(read-write) DMA Control Register, UARTDMACR

inline uint8_t get_UARTPERIPHID0_PARTNUMBER0() volatile#

Get UARTPERIPHID0’s PARTNUMBER0 field.

These bits read back as 0x11

inline uint8_t get_UARTPERIPHID1_PARTNUMBER1() volatile#

Get UARTPERIPHID1’s PARTNUMBER1 field.

These bits read back as 0x0

inline uint8_t get_UARTPERIPHID1_DESIGNER0() volatile#

Get UARTPERIPHID1’s DESIGNER0 field.

These bits read back as 0x1

inline void get_UARTPERIPHID1(uint8_t &PARTNUMBER1, uint8_t &DESIGNER0) volatile#

Get all of UARTPERIPHID1’s bit fields.

(read-only) UARTPeriphID1 Register

inline uint8_t get_UARTPERIPHID2_DESIGNER1() volatile#

Get UARTPERIPHID2’s DESIGNER1 field.

These bits read back as 0x4

inline uint8_t get_UARTPERIPHID2_REVISION() volatile#

Get UARTPERIPHID2’s REVISION field.

This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3

inline void get_UARTPERIPHID2(uint8_t &DESIGNER1, uint8_t &REVISION) volatile#

Get all of UARTPERIPHID2’s bit fields.

(read-only) UARTPeriphID2 Register

inline uint8_t get_UARTPERIPHID3_CONFIGURATION() volatile#

Get UARTPERIPHID3’s CONFIGURATION field.

These bits read back as 0x00

inline uint8_t get_UARTPCELLID0_UARTPCELLID0() volatile#

Get UARTPCELLID0’s UARTPCELLID0 field.

These bits read back as 0x0D

inline uint8_t get_UARTPCELLID1_UARTPCELLID1() volatile#

Get UARTPCELLID1’s UARTPCELLID1 field.

These bits read back as 0xF0

inline uint8_t get_UARTPCELLID2_UARTPCELLID2() volatile#

Get UARTPCELLID2’s UARTPCELLID2 field.

These bits read back as 0x05

inline uint8_t get_UARTPCELLID3_UARTPCELLID3() volatile#

Get UARTPCELLID3’s UARTPCELLID3 field.

These bits read back as 0xB1

Contents

Struct uart0#

Struct Documentation#