Struct sio#

Defined in File sio.h

Struct Documentation#

struct sio#

Single-cycle IO block

Provides core-local and inter-core hardware for the two processors, with single-cycle access.

Public Functions

inline uint32_t get_GPIO_IN_GPIO_IN() volatile#

Get GPIO_IN’s GPIO_IN field.

Input value for GPIO0…29

inline uint8_t get_GPIO_HI_IN_GPIO_HI_IN() volatile#

Get GPIO_HI_IN’s GPIO_HI_IN field.

Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3

inline uint32_t get_GPIO_OUT_GPIO_OUT() volatile#

Get GPIO_OUT’s GPIO_OUT field.

Set output level (1/0 -> high/low) for GPIO0…29.

Reading back gives the last value written, NOT the input value from the pins.

If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),

the result is as though the write from core 0 took place first,

and the write from core 1 was then applied to that intermediate result.

inline void set_GPIO_OUT_GPIO_OUT(uint32_t value) volatile#

Set GPIO_OUT’s GPIO_OUT field.

Set output level (1/0 -> high/low) for GPIO0…29.

Reading back gives the last value written, NOT the input value from the pins.

If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),

the result is as though the write from core 0 took place first,

and the write from core 1 was then applied to that intermediate result.

inline void set_GPIO_OUT_SET_GPIO_OUT_SET(uint32_t value) volatile#

Set GPIO_OUT_SET’s GPIO_OUT_SET field.

Perform an atomic bit-set on GPIO_OUT, i.e. GPIO_OUT |= wdata

inline void set_GPIO_OUT_CLR_GPIO_OUT_CLR(uint32_t value) volatile#

Set GPIO_OUT_CLR’s GPIO_OUT_CLR field.

Perform an atomic bit-clear on GPIO_OUT, i.e. GPIO_OUT &= ~wdata

inline void set_GPIO_OUT_XOR_GPIO_OUT_XOR(uint32_t value) volatile#

Set GPIO_OUT_XOR’s GPIO_OUT_XOR field.

Perform an atomic bitwise XOR on GPIO_OUT, i.e. GPIO_OUT ^= wdata

inline uint32_t get_GPIO_OE_GPIO_OE() volatile#

Get GPIO_OE’s GPIO_OE field.

Set output enable (1/0 -> output/input) for GPIO0…29.

Reading back gives the last value written.

If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),

the result is as though the write from core 0 took place first,

and the write from core 1 was then applied to that intermediate result.

inline void set_GPIO_OE_GPIO_OE(uint32_t value) volatile#

Set GPIO_OE’s GPIO_OE field.

Set output enable (1/0 -> output/input) for GPIO0…29.

Reading back gives the last value written.

If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),

the result is as though the write from core 0 took place first,

and the write from core 1 was then applied to that intermediate result.

inline void set_GPIO_OE_SET_GPIO_OE_SET(uint32_t value) volatile#

Set GPIO_OE_SET’s GPIO_OE_SET field.

Perform an atomic bit-set on GPIO_OE, i.e. GPIO_OE |= wdata

inline void set_GPIO_OE_CLR_GPIO_OE_CLR(uint32_t value) volatile#

Set GPIO_OE_CLR’s GPIO_OE_CLR field.

Perform an atomic bit-clear on GPIO_OE, i.e. GPIO_OE &= ~wdata

inline void set_GPIO_OE_XOR_GPIO_OE_XOR(uint32_t value) volatile#

Set GPIO_OE_XOR’s GPIO_OE_XOR field.

Perform an atomic bitwise XOR on GPIO_OE, i.e. GPIO_OE ^= wdata

inline uint8_t get_GPIO_HI_OUT_GPIO_HI_OUT() volatile#

Get GPIO_HI_OUT’s GPIO_HI_OUT field.

Set output level (1/0 -> high/low) for QSPI IO0…5.

Reading back gives the last value written, NOT the input value from the pins.

If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),

the result is as though the write from core 0 took place first,

and the write from core 1 was then applied to that intermediate result.

inline void set_GPIO_HI_OUT_GPIO_HI_OUT(uint8_t value) volatile#

Set GPIO_HI_OUT’s GPIO_HI_OUT field.

Set output level (1/0 -> high/low) for QSPI IO0…5.

Reading back gives the last value written, NOT the input value from the pins.

If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),

the result is as though the write from core 0 took place first,

and the write from core 1 was then applied to that intermediate result.

inline void set_GPIO_HI_OUT_SET_GPIO_HI_OUT_SET(uint8_t value) volatile#

Set GPIO_HI_OUT_SET’s GPIO_HI_OUT_SET field.

Perform an atomic bit-set on GPIO_HI_OUT, i.e. GPIO_HI_OUT |= wdata

inline void set_GPIO_HI_OUT_CLR_GPIO_HI_OUT_CLR(uint8_t value) volatile#

Set GPIO_HI_OUT_CLR’s GPIO_HI_OUT_CLR field.

Perform an atomic bit-clear on GPIO_HI_OUT, i.e. GPIO_HI_OUT &= ~wdata

inline void set_GPIO_HI_OUT_XOR_GPIO_HI_OUT_XOR(uint8_t value) volatile#

Set GPIO_HI_OUT_XOR’s GPIO_HI_OUT_XOR field.

Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. GPIO_HI_OUT ^= wdata

inline uint8_t get_GPIO_HI_OE_GPIO_HI_OE() volatile#

Get GPIO_HI_OE’s GPIO_HI_OE field.

Set output enable (1/0 -> output/input) for QSPI IO0…5.

Reading back gives the last value written.

If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),

the result is as though the write from core 0 took place first,

and the write from core 1 was then applied to that intermediate result.

inline void set_GPIO_HI_OE_GPIO_HI_OE(uint8_t value) volatile#

Set GPIO_HI_OE’s GPIO_HI_OE field.

Set output enable (1/0 -> output/input) for QSPI IO0…5.

Reading back gives the last value written.

If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),

the result is as though the write from core 0 took place first,

and the write from core 1 was then applied to that intermediate result.

inline void set_GPIO_HI_OE_SET_GPIO_HI_OE_SET(uint8_t value) volatile#

Set GPIO_HI_OE_SET’s GPIO_HI_OE_SET field.

Perform an atomic bit-set on GPIO_HI_OE, i.e. GPIO_HI_OE |= wdata

inline void set_GPIO_HI_OE_CLR_GPIO_HI_OE_CLR(uint8_t value) volatile#

Set GPIO_HI_OE_CLR’s GPIO_HI_OE_CLR field.

Perform an atomic bit-clear on GPIO_HI_OE, i.e. GPIO_HI_OE &= ~wdata

inline void set_GPIO_HI_OE_XOR_GPIO_HI_OE_XOR(uint8_t value) volatile#

Set GPIO_HI_OE_XOR’s GPIO_HI_OE_XOR field.

Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. GPIO_HI_OE ^= wdata

inline bool get_FIFO_ST_VLD() volatile#

Get FIFO_ST’s VLD bit.

Value is 1 if this core’s RX FIFO is not empty (i.e. if FIFO_RD is valid)

inline bool get_FIFO_ST_RDY() volatile#

Get FIFO_ST’s RDY bit.

Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR is ready for more data)

inline bool get_FIFO_ST_WOF() volatile#

Get FIFO_ST’s WOF bit.

Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.

inline void set_FIFO_ST_WOF() volatile#

Set FIFO_ST’s WOF bit.

Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.

inline void clear_FIFO_ST_WOF() volatile#

Clear FIFO_ST’s WOF bit.

Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.

inline void toggle_FIFO_ST_WOF() volatile#

Toggle FIFO_ST’s WOF bit.

Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.

inline bool get_FIFO_ST_ROE() volatile#

Get FIFO_ST’s ROE bit.

Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.

inline void set_FIFO_ST_ROE() volatile#

Set FIFO_ST’s ROE bit.

Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.

inline void clear_FIFO_ST_ROE() volatile#

Clear FIFO_ST’s ROE bit.

Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.

inline void toggle_FIFO_ST_ROE() volatile#

Toggle FIFO_ST’s ROE bit.

Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.

inline void get_FIFO_ST(bool &VLD, bool &RDY, bool &WOF, bool &ROE) volatile#

Get all of FIFO_ST’s bit fields.

(read-write) Status register for inter-core FIFOs (mailboxes).

There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.

Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).

Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).

The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.

inline void set_FIFO_ST(bool WOF, bool ROE) volatile#

Set all of FIFO_ST’s bit fields.

(read-write) Status register for inter-core FIFOs (mailboxes).

There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.

Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).

Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).

The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.

inline bool get_DIV_CSR_READY() volatile#

Get DIV_CSR’s READY bit.

Reads as 0 when a calculation is in progress, 1 otherwise.

Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no

matter if one is already in progress.

Writing to a result register will immediately terminate any in-progress calculation

and set the READY and DIRTY flags.

inline bool get_DIV_CSR_DIRTY() volatile#

Get DIV_CSR’s DIRTY bit.

Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.

Software can use this flag to make save/restore more efficient (skip if not DIRTY).

If the flag is used in this way, it’s recommended to either read QUOTIENT only,

or REMAINDER and then QUOTIENT, to prevent data loss on context switch.

inline void get_DIV_CSR(bool &READY, bool &DIRTY) volatile#

Get all of DIV_CSR’s bit fields.

(read-only) Control and status register for divider.

inline uint8_t get_INTERP0_CTRL_LANE0_SHIFT() volatile#

Get INTERP0_CTRL_LANE0’s SHIFT field.

Logical right-shift applied to accumulator before masking

inline void set_INTERP0_CTRL_LANE0_SHIFT(uint8_t value) volatile#

Set INTERP0_CTRL_LANE0’s SHIFT field.

Logical right-shift applied to accumulator before masking

inline uint8_t get_INTERP0_CTRL_LANE0_MASK_LSB() volatile#

Get INTERP0_CTRL_LANE0’s MASK_LSB field.

The least-significant bit allowed to pass by the mask (inclusive)

inline void set_INTERP0_CTRL_LANE0_MASK_LSB(uint8_t value) volatile#

Set INTERP0_CTRL_LANE0’s MASK_LSB field.

The least-significant bit allowed to pass by the mask (inclusive)

inline uint8_t get_INTERP0_CTRL_LANE0_MASK_MSB() volatile#

Get INTERP0_CTRL_LANE0’s MASK_MSB field.

The most-significant bit allowed to pass by the mask (inclusive)

Setting MSB < LSB may cause chip to turn inside-out

inline void set_INTERP0_CTRL_LANE0_MASK_MSB(uint8_t value) volatile#

Set INTERP0_CTRL_LANE0’s MASK_MSB field.

The most-significant bit allowed to pass by the mask (inclusive)

Setting MSB < LSB may cause chip to turn inside-out

inline bool get_INTERP0_CTRL_LANE0_SIGNED() volatile#

Get INTERP0_CTRL_LANE0’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

inline void set_INTERP0_CTRL_LANE0_SIGNED() volatile#

Set INTERP0_CTRL_LANE0’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

inline void clear_INTERP0_CTRL_LANE0_SIGNED() volatile#

Clear INTERP0_CTRL_LANE0’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

inline void toggle_INTERP0_CTRL_LANE0_SIGNED() volatile#

Toggle INTERP0_CTRL_LANE0’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

inline bool get_INTERP0_CTRL_LANE0_CROSS_INPUT() volatile#

Get INTERP0_CTRL_LANE0’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline void set_INTERP0_CTRL_LANE0_CROSS_INPUT() volatile#

Set INTERP0_CTRL_LANE0’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline void clear_INTERP0_CTRL_LANE0_CROSS_INPUT() volatile#

Clear INTERP0_CTRL_LANE0’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline void toggle_INTERP0_CTRL_LANE0_CROSS_INPUT() volatile#

Toggle INTERP0_CTRL_LANE0’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline bool get_INTERP0_CTRL_LANE0_CROSS_RESULT() volatile#

Get INTERP0_CTRL_LANE0’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline void set_INTERP0_CTRL_LANE0_CROSS_RESULT() volatile#

Set INTERP0_CTRL_LANE0’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline void clear_INTERP0_CTRL_LANE0_CROSS_RESULT() volatile#

Clear INTERP0_CTRL_LANE0’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline void toggle_INTERP0_CTRL_LANE0_CROSS_RESULT() volatile#

Toggle INTERP0_CTRL_LANE0’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline bool get_INTERP0_CTRL_LANE0_ADD_RAW() volatile#

Get INTERP0_CTRL_LANE0’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

inline void set_INTERP0_CTRL_LANE0_ADD_RAW() volatile#

Set INTERP0_CTRL_LANE0’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

inline void clear_INTERP0_CTRL_LANE0_ADD_RAW() volatile#

Clear INTERP0_CTRL_LANE0’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

inline void toggle_INTERP0_CTRL_LANE0_ADD_RAW() volatile#

Toggle INTERP0_CTRL_LANE0’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

inline uint8_t get_INTERP0_CTRL_LANE0_FORCE_MSB() volatile#

Get INTERP0_CTRL_LANE0’s FORCE_MSB field.

ORed into bits 29:28 of the lane result presented to the processor on the bus.

No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence

of pointers into flash or SRAM.

inline void set_INTERP0_CTRL_LANE0_FORCE_MSB(uint8_t value) volatile#

Set INTERP0_CTRL_LANE0’s FORCE_MSB field.

ORed into bits 29:28 of the lane result presented to the processor on the bus.

No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence

of pointers into flash or SRAM.

inline bool get_INTERP0_CTRL_LANE0_BLEND() volatile#

Get INTERP0_CTRL_LANE0’s BLEND bit.

Only present on INTERP0 on each core. If BLEND mode is enabled:

LANE1 result is a linear interpolation between BASE0 and BASE1, controlled

by the 8 LSBs of lane 1 shift and mask value (a fractional number between
0 and 255/256ths)
LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)
FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)

LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.

inline void set_INTERP0_CTRL_LANE0_BLEND() volatile#

Set INTERP0_CTRL_LANE0’s BLEND bit.

Only present on INTERP0 on each core. If BLEND mode is enabled:

LANE1 result is a linear interpolation between BASE0 and BASE1, controlled

by the 8 LSBs of lane 1 shift and mask value (a fractional number between
0 and 255/256ths)
LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)
FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)

LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.

inline void clear_INTERP0_CTRL_LANE0_BLEND() volatile#

Clear INTERP0_CTRL_LANE0’s BLEND bit.

Only present on INTERP0 on each core. If BLEND mode is enabled:

LANE1 result is a linear interpolation between BASE0 and BASE1, controlled

by the 8 LSBs of lane 1 shift and mask value (a fractional number between
0 and 255/256ths)
LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)
FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)

LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.

inline void toggle_INTERP0_CTRL_LANE0_BLEND() volatile#

Toggle INTERP0_CTRL_LANE0’s BLEND bit.

Only present on INTERP0 on each core. If BLEND mode is enabled:

LANE1 result is a linear interpolation between BASE0 and BASE1, controlled

by the 8 LSBs of lane 1 shift and mask value (a fractional number between
0 and 255/256ths)
LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)
FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)

LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.

inline bool get_INTERP0_CTRL_LANE0_OVERF0() volatile#

Get INTERP0_CTRL_LANE0’s OVERF0 bit.

Indicates if any masked-off MSBs in ACCUM0 are set.

inline bool get_INTERP0_CTRL_LANE0_OVERF1() volatile#

Get INTERP0_CTRL_LANE0’s OVERF1 bit.

Indicates if any masked-off MSBs in ACCUM1 are set.

inline bool get_INTERP0_CTRL_LANE0_OVERF() volatile#

Get INTERP0_CTRL_LANE0’s OVERF bit.

Set if either OVERF0 or OVERF1 is set.

inline void get_INTERP0_CTRL_LANE0(uint8_t &SHIFT, uint8_t &MASK_LSB, uint8_t &MASK_MSB, bool &SIGNED, bool &CROSS_INPUT, bool &CROSS_RESULT, bool &ADD_RAW, uint8_t &FORCE_MSB, bool &BLEND, bool &OVERF0, bool &OVERF1, bool &OVERF) volatile#

Get all of INTERP0_CTRL_LANE0’s bit fields.

(read-write) Control register for lane 0

inline void set_INTERP0_CTRL_LANE0(uint8_t SHIFT, uint8_t MASK_LSB, uint8_t MASK_MSB, bool SIGNED, bool CROSS_INPUT, bool CROSS_RESULT, bool ADD_RAW, uint8_t FORCE_MSB, bool BLEND) volatile#

Set all of INTERP0_CTRL_LANE0’s bit fields.

(read-write) Control register for lane 0

inline uint8_t get_INTERP0_CTRL_LANE1_SHIFT() volatile#

Get INTERP0_CTRL_LANE1’s SHIFT field.

Logical right-shift applied to accumulator before masking

inline void set_INTERP0_CTRL_LANE1_SHIFT(uint8_t value) volatile#

Set INTERP0_CTRL_LANE1’s SHIFT field.

Logical right-shift applied to accumulator before masking

inline uint8_t get_INTERP0_CTRL_LANE1_MASK_LSB() volatile#

Get INTERP0_CTRL_LANE1’s MASK_LSB field.

The least-significant bit allowed to pass by the mask (inclusive)

inline void set_INTERP0_CTRL_LANE1_MASK_LSB(uint8_t value) volatile#

Set INTERP0_CTRL_LANE1’s MASK_LSB field.

The least-significant bit allowed to pass by the mask (inclusive)

inline uint8_t get_INTERP0_CTRL_LANE1_MASK_MSB() volatile#

Get INTERP0_CTRL_LANE1’s MASK_MSB field.

The most-significant bit allowed to pass by the mask (inclusive)

Setting MSB < LSB may cause chip to turn inside-out

inline void set_INTERP0_CTRL_LANE1_MASK_MSB(uint8_t value) volatile#

Set INTERP0_CTRL_LANE1’s MASK_MSB field.

The most-significant bit allowed to pass by the mask (inclusive)

Setting MSB < LSB may cause chip to turn inside-out

inline bool get_INTERP0_CTRL_LANE1_SIGNED() volatile#

Get INTERP0_CTRL_LANE1’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.

inline void set_INTERP0_CTRL_LANE1_SIGNED() volatile#

Set INTERP0_CTRL_LANE1’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.

inline void clear_INTERP0_CTRL_LANE1_SIGNED() volatile#

Clear INTERP0_CTRL_LANE1’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.

inline void toggle_INTERP0_CTRL_LANE1_SIGNED() volatile#

Toggle INTERP0_CTRL_LANE1’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.

inline bool get_INTERP0_CTRL_LANE1_CROSS_INPUT() volatile#

Get INTERP0_CTRL_LANE1’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline void set_INTERP0_CTRL_LANE1_CROSS_INPUT() volatile#

Set INTERP0_CTRL_LANE1’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline void clear_INTERP0_CTRL_LANE1_CROSS_INPUT() volatile#

Clear INTERP0_CTRL_LANE1’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline void toggle_INTERP0_CTRL_LANE1_CROSS_INPUT() volatile#

Toggle INTERP0_CTRL_LANE1’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline bool get_INTERP0_CTRL_LANE1_CROSS_RESULT() volatile#

Get INTERP0_CTRL_LANE1’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline void set_INTERP0_CTRL_LANE1_CROSS_RESULT() volatile#

Set INTERP0_CTRL_LANE1’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline void clear_INTERP0_CTRL_LANE1_CROSS_RESULT() volatile#

Clear INTERP0_CTRL_LANE1’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline void toggle_INTERP0_CTRL_LANE1_CROSS_RESULT() volatile#

Toggle INTERP0_CTRL_LANE1’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline bool get_INTERP0_CTRL_LANE1_ADD_RAW() volatile#

Get INTERP0_CTRL_LANE1’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.

inline void set_INTERP0_CTRL_LANE1_ADD_RAW() volatile#

Set INTERP0_CTRL_LANE1’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.

inline void clear_INTERP0_CTRL_LANE1_ADD_RAW() volatile#

Clear INTERP0_CTRL_LANE1’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.

inline void toggle_INTERP0_CTRL_LANE1_ADD_RAW() volatile#

Toggle INTERP0_CTRL_LANE1’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.

inline uint8_t get_INTERP0_CTRL_LANE1_FORCE_MSB() volatile#

Get INTERP0_CTRL_LANE1’s FORCE_MSB field.

ORed into bits 29:28 of the lane result presented to the processor on the bus.

No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence

of pointers into flash or SRAM.

inline void set_INTERP0_CTRL_LANE1_FORCE_MSB(uint8_t value) volatile#

Set INTERP0_CTRL_LANE1’s FORCE_MSB field.

ORed into bits 29:28 of the lane result presented to the processor on the bus.

No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence

of pointers into flash or SRAM.

inline void get_INTERP0_CTRL_LANE1(uint8_t &SHIFT, uint8_t &MASK_LSB, uint8_t &MASK_MSB, bool &SIGNED, bool &CROSS_INPUT, bool &CROSS_RESULT, bool &ADD_RAW, uint8_t &FORCE_MSB) volatile#

Get all of INTERP0_CTRL_LANE1’s bit fields.

(read-write) Control register for lane 1

inline void set_INTERP0_CTRL_LANE1(uint8_t SHIFT, uint8_t MASK_LSB, uint8_t MASK_MSB, bool SIGNED, bool CROSS_INPUT, bool CROSS_RESULT, bool ADD_RAW, uint8_t FORCE_MSB) volatile#

Set all of INTERP0_CTRL_LANE1’s bit fields.

(read-write) Control register for lane 1

inline uint32_t get_INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD() volatile#: Get INTERP0_ACCUM0_ADD’s INTERP0_ACCUM0_ADD field.

inline void set_INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD(uint32_t value) volatile#: Set INTERP0_ACCUM0_ADD’s INTERP0_ACCUM0_ADD field.

inline uint32_t get_INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD() volatile#: Get INTERP0_ACCUM1_ADD’s INTERP0_ACCUM1_ADD field.

inline void set_INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD(uint32_t value) volatile#: Set INTERP0_ACCUM1_ADD’s INTERP0_ACCUM1_ADD field.

inline uint8_t get_INTERP1_CTRL_LANE0_SHIFT() volatile#

Get INTERP1_CTRL_LANE0’s SHIFT field.

Logical right-shift applied to accumulator before masking

inline void set_INTERP1_CTRL_LANE0_SHIFT(uint8_t value) volatile#

Set INTERP1_CTRL_LANE0’s SHIFT field.

Logical right-shift applied to accumulator before masking

inline uint8_t get_INTERP1_CTRL_LANE0_MASK_LSB() volatile#

Get INTERP1_CTRL_LANE0’s MASK_LSB field.

The least-significant bit allowed to pass by the mask (inclusive)

inline void set_INTERP1_CTRL_LANE0_MASK_LSB(uint8_t value) volatile#

Set INTERP1_CTRL_LANE0’s MASK_LSB field.

The least-significant bit allowed to pass by the mask (inclusive)

inline uint8_t get_INTERP1_CTRL_LANE0_MASK_MSB() volatile#

Get INTERP1_CTRL_LANE0’s MASK_MSB field.

The most-significant bit allowed to pass by the mask (inclusive)

Setting MSB < LSB may cause chip to turn inside-out

inline void set_INTERP1_CTRL_LANE0_MASK_MSB(uint8_t value) volatile#

Set INTERP1_CTRL_LANE0’s MASK_MSB field.

The most-significant bit allowed to pass by the mask (inclusive)

Setting MSB < LSB may cause chip to turn inside-out

inline bool get_INTERP1_CTRL_LANE0_SIGNED() volatile#

Get INTERP1_CTRL_LANE0’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

inline void set_INTERP1_CTRL_LANE0_SIGNED() volatile#

Set INTERP1_CTRL_LANE0’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

inline void clear_INTERP1_CTRL_LANE0_SIGNED() volatile#

Clear INTERP1_CTRL_LANE0’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

inline void toggle_INTERP1_CTRL_LANE0_SIGNED() volatile#

Toggle INTERP1_CTRL_LANE0’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

inline bool get_INTERP1_CTRL_LANE0_CROSS_INPUT() volatile#

Get INTERP1_CTRL_LANE0’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline void set_INTERP1_CTRL_LANE0_CROSS_INPUT() volatile#

Set INTERP1_CTRL_LANE0’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline void clear_INTERP1_CTRL_LANE0_CROSS_INPUT() volatile#

Clear INTERP1_CTRL_LANE0’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline void toggle_INTERP1_CTRL_LANE0_CROSS_INPUT() volatile#

Toggle INTERP1_CTRL_LANE0’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline bool get_INTERP1_CTRL_LANE0_CROSS_RESULT() volatile#

Get INTERP1_CTRL_LANE0’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline void set_INTERP1_CTRL_LANE0_CROSS_RESULT() volatile#

Set INTERP1_CTRL_LANE0’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline void clear_INTERP1_CTRL_LANE0_CROSS_RESULT() volatile#

Clear INTERP1_CTRL_LANE0’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline void toggle_INTERP1_CTRL_LANE0_CROSS_RESULT() volatile#

Toggle INTERP1_CTRL_LANE0’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline bool get_INTERP1_CTRL_LANE0_ADD_RAW() volatile#

Get INTERP1_CTRL_LANE0’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

inline void set_INTERP1_CTRL_LANE0_ADD_RAW() volatile#

Set INTERP1_CTRL_LANE0’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

inline void clear_INTERP1_CTRL_LANE0_ADD_RAW() volatile#

Clear INTERP1_CTRL_LANE0’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

inline void toggle_INTERP1_CTRL_LANE0_ADD_RAW() volatile#

Toggle INTERP1_CTRL_LANE0’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

inline uint8_t get_INTERP1_CTRL_LANE0_FORCE_MSB() volatile#

Get INTERP1_CTRL_LANE0’s FORCE_MSB field.

ORed into bits 29:28 of the lane result presented to the processor on the bus.

No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence

of pointers into flash or SRAM.

inline void set_INTERP1_CTRL_LANE0_FORCE_MSB(uint8_t value) volatile#

Set INTERP1_CTRL_LANE0’s FORCE_MSB field.

ORed into bits 29:28 of the lane result presented to the processor on the bus.

No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence

of pointers into flash or SRAM.

inline bool get_INTERP1_CTRL_LANE0_CLAMP() volatile#

Get INTERP1_CTRL_LANE0’s CLAMP bit.

Only present on INTERP1 on each core. If CLAMP mode is enabled:

LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of

BASE0 and an upper bound of BASE1.
Signedness of these comparisons is determined by LANE0_CTRL_SIGNED

inline void set_INTERP1_CTRL_LANE0_CLAMP() volatile#

Set INTERP1_CTRL_LANE0’s CLAMP bit.

Only present on INTERP1 on each core. If CLAMP mode is enabled:

LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of

BASE0 and an upper bound of BASE1.
Signedness of these comparisons is determined by LANE0_CTRL_SIGNED

inline void clear_INTERP1_CTRL_LANE0_CLAMP() volatile#

Clear INTERP1_CTRL_LANE0’s CLAMP bit.

Only present on INTERP1 on each core. If CLAMP mode is enabled:

LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of

BASE0 and an upper bound of BASE1.
Signedness of these comparisons is determined by LANE0_CTRL_SIGNED

inline void toggle_INTERP1_CTRL_LANE0_CLAMP() volatile#

Toggle INTERP1_CTRL_LANE0’s CLAMP bit.

Only present on INTERP1 on each core. If CLAMP mode is enabled:

LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of

BASE0 and an upper bound of BASE1.
Signedness of these comparisons is determined by LANE0_CTRL_SIGNED

inline bool get_INTERP1_CTRL_LANE0_OVERF0() volatile#

Get INTERP1_CTRL_LANE0’s OVERF0 bit.

Indicates if any masked-off MSBs in ACCUM0 are set.

inline bool get_INTERP1_CTRL_LANE0_OVERF1() volatile#

Get INTERP1_CTRL_LANE0’s OVERF1 bit.

Indicates if any masked-off MSBs in ACCUM1 are set.

inline bool get_INTERP1_CTRL_LANE0_OVERF() volatile#

Get INTERP1_CTRL_LANE0’s OVERF bit.

Set if either OVERF0 or OVERF1 is set.

inline void get_INTERP1_CTRL_LANE0(uint8_t &SHIFT, uint8_t &MASK_LSB, uint8_t &MASK_MSB, bool &SIGNED, bool &CROSS_INPUT, bool &CROSS_RESULT, bool &ADD_RAW, uint8_t &FORCE_MSB, bool &CLAMP, bool &OVERF0, bool &OVERF1, bool &OVERF) volatile#

Get all of INTERP1_CTRL_LANE0’s bit fields.

(read-write) Control register for lane 0

inline void set_INTERP1_CTRL_LANE0(uint8_t SHIFT, uint8_t MASK_LSB, uint8_t MASK_MSB, bool SIGNED, bool CROSS_INPUT, bool CROSS_RESULT, bool ADD_RAW, uint8_t FORCE_MSB, bool CLAMP) volatile#

Set all of INTERP1_CTRL_LANE0’s bit fields.

(read-write) Control register for lane 0

inline uint8_t get_INTERP1_CTRL_LANE1_SHIFT() volatile#

Get INTERP1_CTRL_LANE1’s SHIFT field.

Logical right-shift applied to accumulator before masking

inline void set_INTERP1_CTRL_LANE1_SHIFT(uint8_t value) volatile#

Set INTERP1_CTRL_LANE1’s SHIFT field.

Logical right-shift applied to accumulator before masking

inline uint8_t get_INTERP1_CTRL_LANE1_MASK_LSB() volatile#

Get INTERP1_CTRL_LANE1’s MASK_LSB field.

The least-significant bit allowed to pass by the mask (inclusive)

inline void set_INTERP1_CTRL_LANE1_MASK_LSB(uint8_t value) volatile#

Set INTERP1_CTRL_LANE1’s MASK_LSB field.

The least-significant bit allowed to pass by the mask (inclusive)

inline uint8_t get_INTERP1_CTRL_LANE1_MASK_MSB() volatile#

Get INTERP1_CTRL_LANE1’s MASK_MSB field.

The most-significant bit allowed to pass by the mask (inclusive)

Setting MSB < LSB may cause chip to turn inside-out

inline void set_INTERP1_CTRL_LANE1_MASK_MSB(uint8_t value) volatile#

Set INTERP1_CTRL_LANE1’s MASK_MSB field.

The most-significant bit allowed to pass by the mask (inclusive)

Setting MSB < LSB may cause chip to turn inside-out

inline bool get_INTERP1_CTRL_LANE1_SIGNED() volatile#

Get INTERP1_CTRL_LANE1’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.

inline void set_INTERP1_CTRL_LANE1_SIGNED() volatile#

Set INTERP1_CTRL_LANE1’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.

inline void clear_INTERP1_CTRL_LANE1_SIGNED() volatile#

Clear INTERP1_CTRL_LANE1’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.

inline void toggle_INTERP1_CTRL_LANE1_SIGNED() volatile#

Toggle INTERP1_CTRL_LANE1’s SIGNED bit.

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits

before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.

inline bool get_INTERP1_CTRL_LANE1_CROSS_INPUT() volatile#

Get INTERP1_CTRL_LANE1’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline void set_INTERP1_CTRL_LANE1_CROSS_INPUT() volatile#

Set INTERP1_CTRL_LANE1’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline void clear_INTERP1_CTRL_LANE1_CROSS_INPUT() volatile#

Clear INTERP1_CTRL_LANE1’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline void toggle_INTERP1_CTRL_LANE1_CROSS_INPUT() volatile#

Toggle INTERP1_CTRL_LANE1’s CROSS_INPUT bit.

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.

Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

inline bool get_INTERP1_CTRL_LANE1_CROSS_RESULT() volatile#

Get INTERP1_CTRL_LANE1’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline void set_INTERP1_CTRL_LANE1_CROSS_RESULT() volatile#

Set INTERP1_CTRL_LANE1’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline void clear_INTERP1_CTRL_LANE1_CROSS_RESULT() volatile#

Clear INTERP1_CTRL_LANE1’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline void toggle_INTERP1_CTRL_LANE1_CROSS_RESULT() volatile#

Toggle INTERP1_CTRL_LANE1’s CROSS_RESULT bit.

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

inline bool get_INTERP1_CTRL_LANE1_ADD_RAW() volatile#

Get INTERP1_CTRL_LANE1’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.

inline void set_INTERP1_CTRL_LANE1_ADD_RAW() volatile#

Set INTERP1_CTRL_LANE1’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.

inline void clear_INTERP1_CTRL_LANE1_ADD_RAW() volatile#

Clear INTERP1_CTRL_LANE1’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.

inline void toggle_INTERP1_CTRL_LANE1_ADD_RAW() volatile#

Toggle INTERP1_CTRL_LANE1’s ADD_RAW bit.

If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.

inline uint8_t get_INTERP1_CTRL_LANE1_FORCE_MSB() volatile#

Get INTERP1_CTRL_LANE1’s FORCE_MSB field.

ORed into bits 29:28 of the lane result presented to the processor on the bus.

No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence

of pointers into flash or SRAM.

inline void set_INTERP1_CTRL_LANE1_FORCE_MSB(uint8_t value) volatile#

Set INTERP1_CTRL_LANE1’s FORCE_MSB field.

ORed into bits 29:28 of the lane result presented to the processor on the bus.

No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence

of pointers into flash or SRAM.

inline void get_INTERP1_CTRL_LANE1(uint8_t &SHIFT, uint8_t &MASK_LSB, uint8_t &MASK_MSB, bool &SIGNED, bool &CROSS_INPUT, bool &CROSS_RESULT, bool &ADD_RAW, uint8_t &FORCE_MSB) volatile#

Get all of INTERP1_CTRL_LANE1’s bit fields.

(read-write) Control register for lane 1

inline void set_INTERP1_CTRL_LANE1(uint8_t SHIFT, uint8_t MASK_LSB, uint8_t MASK_MSB, bool SIGNED, bool CROSS_INPUT, bool CROSS_RESULT, bool ADD_RAW, uint8_t FORCE_MSB) volatile#

Set all of INTERP1_CTRL_LANE1’s bit fields.

(read-write) Control register for lane 1

inline uint32_t get_INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD() volatile#: Get INTERP1_ACCUM0_ADD’s INTERP1_ACCUM0_ADD field.

inline void set_INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD(uint32_t value) volatile#: Set INTERP1_ACCUM0_ADD’s INTERP1_ACCUM0_ADD field.

inline uint32_t get_INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD() volatile#: Get INTERP1_ACCUM1_ADD’s INTERP1_ACCUM1_ADD field.

inline void set_INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD(uint32_t value) volatile#: Set INTERP1_ACCUM1_ADD’s INTERP1_ACCUM1_ADD field.

Public Members

uint32_t CPUID#

(read-write) Processor core identifier

Value is 0 when read from processor core 0, and 1 when read from processor core 1.

const uint32_t GPIO_IN = {}#: (read-only) Input value for GPIO pins

const uint32_t GPIO_HI_IN = {}#: (read-only) Input value for QSPI pins

const uint32_t reserved_padding0 = {}#

uint32_t GPIO_OUT#: (read-write) GPIO output value

uint32_t GPIO_OUT_SET#: (write-only) GPIO output value set

uint32_t GPIO_OUT_CLR#: (write-only) GPIO output value clear

uint32_t GPIO_OUT_XOR#: (write-only) GPIO output value XOR

uint32_t GPIO_OE#: (read-write) GPIO output enable

uint32_t GPIO_OE_SET#: (write-only) GPIO output enable set

uint32_t GPIO_OE_CLR#: (write-only) GPIO output enable clear

uint32_t GPIO_OE_XOR#: (write-only) GPIO output enable XOR

uint32_t GPIO_HI_OUT#: (read-write) QSPI output value

uint32_t GPIO_HI_OUT_SET#: (write-only) QSPI output value set

uint32_t GPIO_HI_OUT_CLR#: (write-only) QSPI output value clear

uint32_t GPIO_HI_OUT_XOR#: (write-only) QSPI output value XOR

uint32_t GPIO_HI_OE#: (read-write) QSPI output enable

uint32_t GPIO_HI_OE_SET#: (write-only) QSPI output enable set

uint32_t GPIO_HI_OE_CLR#: (write-only) QSPI output enable clear

uint32_t GPIO_HI_OE_XOR#: (write-only) QSPI output enable XOR

uint32_t FIFO_ST#

(read-write) Status register for inter-core FIFOs (mailboxes).

There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.

Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).

Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).

The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.

uint32_t FIFO_WR#: (read-write) Write access to this core’s TX FIFO

uint32_t FIFO_RD#: (read-write) Read access to this core’s RX FIFO

uint32_t SPINLOCK_ST#

(read-write) Spinlock state

A bitmap containing the state of all 32 spinlocks (1=locked).

Mainly intended for debugging.

uint32_t DIV_UDIVIDEND#

(read-write) Divider unsigned dividend

Write to the DIVIDEND operand of the divider, i.e. the p in

p / q

Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.

UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an

unsigned calculation, and the S alias starts a signed calculation.

uint32_t DIV_UDIVISOR#

(read-write) Divider unsigned divisor

Write to the DIVISOR operand of the divider, i.e. the q in

p / q

Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.

UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an

unsigned calculation, and the S alias starts a signed calculation.

uint32_t DIV_SDIVIDEND#

(read-write) Divider signed dividend

The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.

uint32_t DIV_SDIVISOR#

(read-write) Divider signed divisor

The same as UDIVISOR, but starts a signed calculation, rather than unsigned.

uint32_t DIV_QUOTIENT#

(read-write) Divider result quotient

The result of

DIVIDEND / DIVISOR

(division). Contents undefined while CSR_READY is low.

For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.

This register can be written to directly, for context save/restore purposes. This halts any

in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.

Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order

REMAINDER, QUOTIENT if CSR_DIRTY is used.

uint32_t DIV_REMAINDER#

(read-write) Divider result remainder

The result of

DIVIDEND % DIVISOR

(modulo). Contents undefined while CSR_READY is low.

For signed calculations, REMAINDER is negative only when DIVIDEND is negative.

This register can be written to directly, for context save/restore purposes. This halts any

in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.

const uint32_t DIV_CSR = {}#: (read-only) Control and status register for divider.

const uint32_t reserved_padding1 = {}#

uint32_t INTERP0_ACCUM0#: (read-write) Read/write access to accumulator 0

uint32_t INTERP0_ACCUM1#: (read-write) Read/write access to accumulator 1

uint32_t INTERP0_BASE0#: (read-write) Read/write access to BASE0 register.

uint32_t INTERP0_BASE1#: (read-write) Read/write access to BASE1 register.

uint32_t INTERP0_BASE2#: (read-write) Read/write access to BASE2 register.

uint32_t INTERP0_POP_LANE0#: (read-write) Read LANE0 result, and simultaneously write lane results to both accumulators (POP).

uint32_t INTERP0_POP_LANE1#: (read-write) Read LANE1 result, and simultaneously write lane results to both accumulators (POP).

uint32_t INTERP0_POP_FULL#: (read-write) Read FULL result, and simultaneously write lane results to both accumulators (POP).

uint32_t INTERP0_PEEK_LANE0#: (read-write) Read LANE0 result, without altering any internal state (PEEK).

uint32_t INTERP0_PEEK_LANE1#: (read-write) Read LANE1 result, without altering any internal state (PEEK).

uint32_t INTERP0_PEEK_FULL#: (read-write) Read FULL result, without altering any internal state (PEEK).

uint32_t INTERP0_CTRL_LANE0#: (read-write) Control register for lane 0

uint32_t INTERP0_CTRL_LANE1#: (read-write) Control register for lane 1

uint32_t INTERP0_ACCUM0_ADD#

(read-write) Values written here are atomically added to ACCUM0

Reading yields lane 0’s raw shift and mask value (BASE0 not added).

uint32_t INTERP0_ACCUM1_ADD#

(read-write) Values written here are atomically added to ACCUM1

Reading yields lane 1’s raw shift and mask value (BASE1 not added).

uint32_t INTERP0_BASE_1AND0#

(read-write) On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.

Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.

uint32_t INTERP1_ACCUM0#: (read-write) Read/write access to accumulator 0

uint32_t INTERP1_ACCUM1#: (read-write) Read/write access to accumulator 1

uint32_t INTERP1_BASE0#: (read-write) Read/write access to BASE0 register.

uint32_t INTERP1_BASE1#: (read-write) Read/write access to BASE1 register.

uint32_t INTERP1_BASE2#: (read-write) Read/write access to BASE2 register.

uint32_t INTERP1_POP_LANE0#: (read-write) Read LANE0 result, and simultaneously write lane results to both accumulators (POP).

uint32_t INTERP1_POP_LANE1#: (read-write) Read LANE1 result, and simultaneously write lane results to both accumulators (POP).

uint32_t INTERP1_POP_FULL#: (read-write) Read FULL result, and simultaneously write lane results to both accumulators (POP).

uint32_t INTERP1_PEEK_LANE0#: (read-write) Read LANE0 result, without altering any internal state (PEEK).

uint32_t INTERP1_PEEK_LANE1#: (read-write) Read LANE1 result, without altering any internal state (PEEK).

uint32_t INTERP1_PEEK_FULL#: (read-write) Read FULL result, without altering any internal state (PEEK).

uint32_t INTERP1_CTRL_LANE0#: (read-write) Control register for lane 0

uint32_t INTERP1_CTRL_LANE1#: (read-write) Control register for lane 1

uint32_t INTERP1_ACCUM0_ADD#

(read-write) Values written here are atomically added to ACCUM0

Reading yields lane 0’s raw shift and mask value (BASE0 not added).

uint32_t INTERP1_ACCUM1_ADD#

(read-write) Values written here are atomically added to ACCUM1

Reading yields lane 1’s raw shift and mask value (BASE1 not added).

uint32_t INTERP1_BASE_1AND0#

(read-write) On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.

Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.

uint32_t SPINLOCK0#