Struct pio0

• Defined in File pio0.h

Struct Documentation

struct pio0

Programmable IO block

Public Functions

inline uint8_t get_CTRL_SM_ENABLE() volatile

Get CTRL’s SM_ENABLE field.

Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously.

inline void set_CTRL_SM_ENABLE(uint8_t value) volatile

Set CTRL’s SM_ENABLE field.

Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously.

inline uint8_t get_CTRL_SM_RESTART() volatile

Get CTRL’s SM_RESTART field.

Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.

Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.

The program counter, the contents of the output shift register and the X/Y scratch registers are not affected.

inline void set_CTRL_SM_RESTART(uint8_t value) volatile

Set CTRL’s SM_RESTART field.

Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.

Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.

The program counter, the contents of the output shift register and the X/Y scratch registers are not affected.

inline uint8_t get_CTRL_CLKDIV_RESTART() volatile

Get CTRL’s CLKDIV_RESTART field.

Restart a state machine’s clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.

Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines’ clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.

Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly.

inline void set_CTRL_CLKDIV_RESTART(uint8_t value) volatile

Set CTRL’s CLKDIV_RESTART field.

Restart a state machine’s clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.

Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines’ clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.

Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly.

inline void get_CTRL(uint8_t &SM_ENABLE, uint8_t &SM_RESTART, uint8_t &CLKDIV_RESTART) volatile

Get all of CTRL’s bit fields.

(read-write) PIO control register

inline void set_CTRL(uint8_t SM_ENABLE, uint8_t SM_RESTART, uint8_t CLKDIV_RESTART) volatile

Set all of CTRL’s bit fields.

(read-write) PIO control register

inline uint8_t get_FSTAT_RXFULL() volatile

Get FSTAT’s RXFULL field.

State machine RX FIFO is full

inline uint8_t get_FSTAT_RXEMPTY() volatile

Get FSTAT’s RXEMPTY field.

State machine RX FIFO is empty

inline uint8_t get_FSTAT_TXFULL() volatile

Get FSTAT’s TXFULL field.

State machine TX FIFO is full

inline uint8_t get_FSTAT_TXEMPTY() volatile

Get FSTAT’s TXEMPTY field.

State machine TX FIFO is empty

inline void get_FSTAT(uint8_t &RXFULL, uint8_t &RXEMPTY, uint8_t &TXFULL, uint8_t &TXEMPTY) volatile

Get all of FSTAT’s bit fields.

(read-only) FIFO status register

inline uint8_t get_FDEBUG_RXSTALL() volatile

Get FDEBUG’s RXSTALL field.

State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear.

inline void set_FDEBUG_RXSTALL(uint8_t value) volatile

Set FDEBUG’s RXSTALL field.

State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear.

inline uint8_t get_FDEBUG_RXUNDER() volatile

Get FDEBUG’s RXUNDER field.

RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error.

inline void set_FDEBUG_RXUNDER(uint8_t value) volatile

Set FDEBUG’s RXUNDER field.

RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error.

inline uint8_t get_FDEBUG_TXOVER() volatile

Get FDEBUG’s TXOVER field.

TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor.

inline void set_FDEBUG_TXOVER(uint8_t value) volatile

Set FDEBUG’s TXOVER field.

TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor.

inline uint8_t get_FDEBUG_TXSTALL() volatile

Get FDEBUG’s TXSTALL field.

State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear.

inline void set_FDEBUG_TXSTALL(uint8_t value) volatile

Set FDEBUG’s TXSTALL field.

State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear.

inline void get_FDEBUG(uint8_t &RXSTALL, uint8_t &RXUNDER, uint8_t &TXOVER, uint8_t &TXSTALL) volatile

Get all of FDEBUG’s bit fields.

(read-write) FIFO debug register

inline void set_FDEBUG(uint8_t RXSTALL, uint8_t RXUNDER, uint8_t TXOVER, uint8_t TXSTALL) volatile

Set all of FDEBUG’s bit fields.

(read-write) FIFO debug register

inline uint8_t get_FLEVEL_TX0() volatile

Get FLEVEL’s TX0 field.

inline uint8_t get_FLEVEL_RX0() volatile

Get FLEVEL’s RX0 field.

inline uint8_t get_FLEVEL_TX1() volatile

Get FLEVEL’s TX1 field.

inline uint8_t get_FLEVEL_RX1() volatile

Get FLEVEL’s RX1 field.

inline uint8_t get_FLEVEL_TX2() volatile

Get FLEVEL’s TX2 field.

inline uint8_t get_FLEVEL_RX2() volatile

Get FLEVEL’s RX2 field.

inline uint8_t get_FLEVEL_TX3() volatile

Get FLEVEL’s TX3 field.

inline uint8_t get_FLEVEL_RX3() volatile

Get FLEVEL’s RX3 field.

inline void get_FLEVEL(uint8_t &TX0, uint8_t &RX0, uint8_t &TX1, uint8_t &RX1, uint8_t &TX2, uint8_t &RX2, uint8_t &TX3, uint8_t &RX3) volatile

Get all of FLEVEL’s bit fields.

(read-only) FIFO levels

inline uint8_t get_IRQ_IRQ() volatile

Get IRQ’s IRQ field.

inline void set_IRQ_IRQ(uint8_t value) volatile

Set IRQ’s IRQ field.

inline void set_IRQ_FORCE_IRQ_FORCE(uint8_t value) volatile

Set IRQ_FORCE’s IRQ_FORCE field.

inline uint8_t get_DBG_CFGINFO_FIFO_DEPTH() volatile

Get DBG_CFGINFO’s FIFO_DEPTH field.

The depth of the state machine TX/RX FIFOs, measured in words.

Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double

this depth.

inline uint8_t get_DBG_CFGINFO_SM_COUNT() volatile

Get DBG_CFGINFO’s SM_COUNT field.

The number of state machines this PIO instance is equipped with.

inline uint8_t get_DBG_CFGINFO_IMEM_SIZE() volatile

Get DBG_CFGINFO’s IMEM_SIZE field.

The size of the instruction memory, measured in units of one instruction

inline void get_DBG_CFGINFO(uint8_t &FIFO_DEPTH, uint8_t &SM_COUNT, uint8_t &IMEM_SIZE) volatile

Get all of DBG_CFGINFO’s bit fields.

(read-only) The PIO hardware has some free parameters that may vary between chip products.

These should be provided in the chip datasheet, but are also exposed here.

inline void set_INSTR_MEM0_INSTR_MEM0(uint16_t value) volatile

Set INSTR_MEM0’s INSTR_MEM0 field.

inline void set_INSTR_MEM1_INSTR_MEM1(uint16_t value) volatile

Set INSTR_MEM1’s INSTR_MEM1 field.

inline void set_INSTR_MEM2_INSTR_MEM2(uint16_t value) volatile

Set INSTR_MEM2’s INSTR_MEM2 field.

inline void set_INSTR_MEM3_INSTR_MEM3(uint16_t value) volatile

Set INSTR_MEM3’s INSTR_MEM3 field.

inline void set_INSTR_MEM4_INSTR_MEM4(uint16_t value) volatile

Set INSTR_MEM4’s INSTR_MEM4 field.

inline void set_INSTR_MEM5_INSTR_MEM5(uint16_t value) volatile

Set INSTR_MEM5’s INSTR_MEM5 field.

inline void set_INSTR_MEM6_INSTR_MEM6(uint16_t value) volatile

Set INSTR_MEM6’s INSTR_MEM6 field.

inline void set_INSTR_MEM7_INSTR_MEM7(uint16_t value) volatile

Set INSTR_MEM7’s INSTR_MEM7 field.

inline void set_INSTR_MEM8_INSTR_MEM8(uint16_t value) volatile

Set INSTR_MEM8’s INSTR_MEM8 field.

inline void set_INSTR_MEM9_INSTR_MEM9(uint16_t value) volatile

Set INSTR_MEM9’s INSTR_MEM9 field.

inline void set_INSTR_MEM10_INSTR_MEM10(uint16_t value) volatile

Set INSTR_MEM10’s INSTR_MEM10 field.

inline void set_INSTR_MEM11_INSTR_MEM11(uint16_t value) volatile

Set INSTR_MEM11’s INSTR_MEM11 field.

inline void set_INSTR_MEM12_INSTR_MEM12(uint16_t value) volatile

Set INSTR_MEM12’s INSTR_MEM12 field.

inline void set_INSTR_MEM13_INSTR_MEM13(uint16_t value) volatile

Set INSTR_MEM13’s INSTR_MEM13 field.

inline void set_INSTR_MEM14_INSTR_MEM14(uint16_t value) volatile

Set INSTR_MEM14’s INSTR_MEM14 field.

inline void set_INSTR_MEM15_INSTR_MEM15(uint16_t value) volatile

Set INSTR_MEM15’s INSTR_MEM15 field.

inline void set_INSTR_MEM16_INSTR_MEM16(uint16_t value) volatile

Set INSTR_MEM16’s INSTR_MEM16 field.

inline void set_INSTR_MEM17_INSTR_MEM17(uint16_t value) volatile

Set INSTR_MEM17’s INSTR_MEM17 field.

inline void set_INSTR_MEM18_INSTR_MEM18(uint16_t value) volatile

Set INSTR_MEM18’s INSTR_MEM18 field.

inline void set_INSTR_MEM19_INSTR_MEM19(uint16_t value) volatile

Set INSTR_MEM19’s INSTR_MEM19 field.

inline void set_INSTR_MEM20_INSTR_MEM20(uint16_t value) volatile

Set INSTR_MEM20’s INSTR_MEM20 field.

inline void set_INSTR_MEM21_INSTR_MEM21(uint16_t value) volatile

Set INSTR_MEM21’s INSTR_MEM21 field.

inline void set_INSTR_MEM22_INSTR_MEM22(uint16_t value) volatile

Set INSTR_MEM22’s INSTR_MEM22 field.

inline void set_INSTR_MEM23_INSTR_MEM23(uint16_t value) volatile

Set INSTR_MEM23’s INSTR_MEM23 field.

inline void set_INSTR_MEM24_INSTR_MEM24(uint16_t value) volatile

Set INSTR_MEM24’s INSTR_MEM24 field.

inline void set_INSTR_MEM25_INSTR_MEM25(uint16_t value) volatile

Set INSTR_MEM25’s INSTR_MEM25 field.

inline void set_INSTR_MEM26_INSTR_MEM26(uint16_t value) volatile

Set INSTR_MEM26’s INSTR_MEM26 field.

inline void set_INSTR_MEM27_INSTR_MEM27(uint16_t value) volatile

Set INSTR_MEM27’s INSTR_MEM27 field.

inline void set_INSTR_MEM28_INSTR_MEM28(uint16_t value) volatile

Set INSTR_MEM28’s INSTR_MEM28 field.

inline void set_INSTR_MEM29_INSTR_MEM29(uint16_t value) volatile

Set INSTR_MEM29’s INSTR_MEM29 field.

inline void set_INSTR_MEM30_INSTR_MEM30(uint16_t value) volatile

Set INSTR_MEM30’s INSTR_MEM30 field.

inline void set_INSTR_MEM31_INSTR_MEM31(uint16_t value) volatile

Set INSTR_MEM31’s INSTR_MEM31 field.

inline uint8_t get_SM0_CLKDIV_FRAC() volatile

Get SM0_CLKDIV’s FRAC field.

Fractional part of clock divisor

inline void set_SM0_CLKDIV_FRAC(uint8_t value) volatile

Set SM0_CLKDIV’s FRAC field.

Fractional part of clock divisor

inline uint16_t get_SM0_CLKDIV_INT() volatile

Get SM0_CLKDIV’s INT field.

Effective frequency is sysclk/(int + frac/256).

Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.

inline void set_SM0_CLKDIV_INT(uint16_t value) volatile

Set SM0_CLKDIV’s INT field.

Effective frequency is sysclk/(int + frac/256).

Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.

inline void get_SM0_CLKDIV(uint8_t &FRAC, uint16_t &INT) volatile

Get all of SM0_CLKDIV’s bit fields.

(read-write) Clock divisor register for state machine 0

Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

inline void set_SM0_CLKDIV(uint8_t FRAC, uint16_t INT) volatile

Set all of SM0_CLKDIV’s bit fields.

(read-write) Clock divisor register for state machine 0

Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

inline uint8_t get_SM0_EXECCTRL_STATUS_N() volatile

Get SM0_EXECCTRL’s STATUS_N field.

Comparison level for the MOV x, STATUS instruction

inline void set_SM0_EXECCTRL_STATUS_N(uint8_t value) volatile

Set SM0_EXECCTRL’s STATUS_N field.

Comparison level for the MOV x, STATUS instruction

inline bool get_SM0_EXECCTRL_STATUS_SEL() volatile

Get SM0_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline void set_SM0_EXECCTRL_STATUS_SEL() volatile

Set SM0_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline void clear_SM0_EXECCTRL_STATUS_SEL() volatile

Clear SM0_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline void toggle_SM0_EXECCTRL_STATUS_SEL() volatile

Toggle SM0_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline uint8_t get_SM0_EXECCTRL_WRAP_BOTTOM() volatile

Get SM0_EXECCTRL’s WRAP_BOTTOM field.

After reaching wrap_top, execution is wrapped to this address.

inline void set_SM0_EXECCTRL_WRAP_BOTTOM(uint8_t value) volatile

Set SM0_EXECCTRL’s WRAP_BOTTOM field.

After reaching wrap_top, execution is wrapped to this address.

inline uint8_t get_SM0_EXECCTRL_WRAP_TOP() volatile

Get SM0_EXECCTRL’s WRAP_TOP field.

After reaching this address, execution is wrapped to wrap_bottom.

If the instruction is a jump, and the jump condition is true, the jump takes priority.

inline void set_SM0_EXECCTRL_WRAP_TOP(uint8_t value) volatile

Set SM0_EXECCTRL’s WRAP_TOP field.

After reaching this address, execution is wrapped to wrap_bottom.

If the instruction is a jump, and the jump condition is true, the jump takes priority.

inline bool get_SM0_EXECCTRL_OUT_STICKY() volatile

Get SM0_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline void set_SM0_EXECCTRL_OUT_STICKY() volatile

Set SM0_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline void clear_SM0_EXECCTRL_OUT_STICKY() volatile

Clear SM0_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline void toggle_SM0_EXECCTRL_OUT_STICKY() volatile

Toggle SM0_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline bool get_SM0_EXECCTRL_INLINE_OUT_EN() volatile

Get SM0_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline void set_SM0_EXECCTRL_INLINE_OUT_EN() volatile

Set SM0_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline void clear_SM0_EXECCTRL_INLINE_OUT_EN() volatile

Clear SM0_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline void toggle_SM0_EXECCTRL_INLINE_OUT_EN() volatile

Toggle SM0_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline uint8_t get_SM0_EXECCTRL_OUT_EN_SEL() volatile

Get SM0_EXECCTRL’s OUT_EN_SEL field.

Which data bit to use for inline OUT enable

inline void set_SM0_EXECCTRL_OUT_EN_SEL(uint8_t value) volatile

Set SM0_EXECCTRL’s OUT_EN_SEL field.

Which data bit to use for inline OUT enable

inline uint8_t get_SM0_EXECCTRL_JMP_PIN() volatile

Get SM0_EXECCTRL’s JMP_PIN field.

The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

inline void set_SM0_EXECCTRL_JMP_PIN(uint8_t value) volatile

Set SM0_EXECCTRL’s JMP_PIN field.

The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

inline bool get_SM0_EXECCTRL_SIDE_PINDIR() volatile

Get SM0_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline void set_SM0_EXECCTRL_SIDE_PINDIR() volatile

Set SM0_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline void clear_SM0_EXECCTRL_SIDE_PINDIR() volatile

Clear SM0_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline void toggle_SM0_EXECCTRL_SIDE_PINDIR() volatile

Toggle SM0_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline bool get_SM0_EXECCTRL_SIDE_EN() volatile

Get SM0_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline void set_SM0_EXECCTRL_SIDE_EN() volatile

Set SM0_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline void clear_SM0_EXECCTRL_SIDE_EN() volatile

Clear SM0_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline void toggle_SM0_EXECCTRL_SIDE_EN() volatile

Toggle SM0_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline bool get_SM0_EXECCTRL_EXEC_STALLED() volatile

Get SM0_EXECCTRL’s EXEC_STALLED bit.

If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.

inline void get_SM0_EXECCTRL(uint8_t &STATUS_N, bool &STATUS_SEL, uint8_t &WRAP_BOTTOM, uint8_t &WRAP_TOP, bool &OUT_STICKY, bool &INLINE_OUT_EN, uint8_t &OUT_EN_SEL, uint8_t &JMP_PIN, bool &SIDE_PINDIR, bool &SIDE_EN, bool &EXEC_STALLED) volatile

Get all of SM0_EXECCTRL’s bit fields.

(read-write) Execution/behavioural settings for state machine 0

inline void set_SM0_EXECCTRL(uint8_t STATUS_N, bool STATUS_SEL, uint8_t WRAP_BOTTOM, uint8_t WRAP_TOP, bool OUT_STICKY, bool INLINE_OUT_EN, uint8_t OUT_EN_SEL, uint8_t JMP_PIN, bool SIDE_PINDIR, bool SIDE_EN) volatile

Set all of SM0_EXECCTRL’s bit fields.

(read-write) Execution/behavioural settings for state machine 0

inline bool get_SM0_SHIFTCTRL_AUTOPUSH() volatile

Get SM0_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline void set_SM0_SHIFTCTRL_AUTOPUSH() volatile

Set SM0_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline void clear_SM0_SHIFTCTRL_AUTOPUSH() volatile

Clear SM0_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline void toggle_SM0_SHIFTCTRL_AUTOPUSH() volatile

Toggle SM0_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline bool get_SM0_SHIFTCTRL_AUTOPULL() volatile

Get SM0_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline void set_SM0_SHIFTCTRL_AUTOPULL() volatile

Set SM0_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline void clear_SM0_SHIFTCTRL_AUTOPULL() volatile

Clear SM0_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline void toggle_SM0_SHIFTCTRL_AUTOPULL() volatile

Toggle SM0_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline bool get_SM0_SHIFTCTRL_IN_SHIFTDIR() volatile

Get SM0_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline void set_SM0_SHIFTCTRL_IN_SHIFTDIR() volatile

Set SM0_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline void clear_SM0_SHIFTCTRL_IN_SHIFTDIR() volatile

Clear SM0_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline void toggle_SM0_SHIFTCTRL_IN_SHIFTDIR() volatile

Toggle SM0_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline bool get_SM0_SHIFTCTRL_OUT_SHIFTDIR() volatile

Get SM0_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline void set_SM0_SHIFTCTRL_OUT_SHIFTDIR() volatile

Set SM0_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline void clear_SM0_SHIFTCTRL_OUT_SHIFTDIR() volatile

Clear SM0_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline void toggle_SM0_SHIFTCTRL_OUT_SHIFTDIR() volatile

Toggle SM0_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline uint8_t get_SM0_SHIFTCTRL_PUSH_THRESH() volatile

Get SM0_SHIFTCTRL’s PUSH_THRESH field.

Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.

Write 0 for value of 32.

inline void set_SM0_SHIFTCTRL_PUSH_THRESH(uint8_t value) volatile

Set SM0_SHIFTCTRL’s PUSH_THRESH field.

Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.

Write 0 for value of 32.

inline uint8_t get_SM0_SHIFTCTRL_PULL_THRESH() volatile

Get SM0_SHIFTCTRL’s PULL_THRESH field.

Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.

Write 0 for value of 32.

inline void set_SM0_SHIFTCTRL_PULL_THRESH(uint8_t value) volatile

Set SM0_SHIFTCTRL’s PULL_THRESH field.

Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.

Write 0 for value of 32.

inline bool get_SM0_SHIFTCTRL_FJOIN_TX() volatile

Get SM0_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void set_SM0_SHIFTCTRL_FJOIN_TX() volatile

Set SM0_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void clear_SM0_SHIFTCTRL_FJOIN_TX() volatile

Clear SM0_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void toggle_SM0_SHIFTCTRL_FJOIN_TX() volatile

Toggle SM0_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline bool get_SM0_SHIFTCTRL_FJOIN_RX() volatile

Get SM0_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void set_SM0_SHIFTCTRL_FJOIN_RX() volatile

Set SM0_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void clear_SM0_SHIFTCTRL_FJOIN_RX() volatile

Clear SM0_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void toggle_SM0_SHIFTCTRL_FJOIN_RX() volatile

Toggle SM0_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void get_SM0_SHIFTCTRL(bool &AUTOPUSH, bool &AUTOPULL, bool &IN_SHIFTDIR, bool &OUT_SHIFTDIR, uint8_t &PUSH_THRESH, uint8_t &PULL_THRESH, bool &FJOIN_TX, bool &FJOIN_RX) volatile

Get all of SM0_SHIFTCTRL’s bit fields.

(read-write) Control behaviour of the input/output shift registers for state machine 0

inline void set_SM0_SHIFTCTRL(bool AUTOPUSH, bool AUTOPULL, bool IN_SHIFTDIR, bool OUT_SHIFTDIR, uint8_t PUSH_THRESH, uint8_t PULL_THRESH, bool FJOIN_TX, bool FJOIN_RX) volatile

Set all of SM0_SHIFTCTRL’s bit fields.

(read-write) Control behaviour of the input/output shift registers for state machine 0

inline uint8_t get_SM0_ADDR_SM0_ADDR() volatile

Get SM0_ADDR’s SM0_ADDR field.

inline uint16_t get_SM0_INSTR_SM0_INSTR() volatile

Get SM0_INSTR’s SM0_INSTR field.

inline void set_SM0_INSTR_SM0_INSTR(uint16_t value) volatile

Set SM0_INSTR’s SM0_INSTR field.

inline uint8_t get_SM0_PINCTRL_OUT_BASE() volatile

Get SM0_PINCTRL’s OUT_BASE field.

The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.

inline void set_SM0_PINCTRL_OUT_BASE(uint8_t value) volatile

Set SM0_PINCTRL’s OUT_BASE field.

The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.

inline uint8_t get_SM0_PINCTRL_SET_BASE() volatile

Get SM0_PINCTRL’s SET_BASE field.

The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.

inline void set_SM0_PINCTRL_SET_BASE(uint8_t value) volatile

Set SM0_PINCTRL’s SET_BASE field.

The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.

inline uint8_t get_SM0_PINCTRL_SIDESET_BASE() volatile

Get SM0_PINCTRL’s SIDESET_BASE field.

The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction’s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.

inline void set_SM0_PINCTRL_SIDESET_BASE(uint8_t value) volatile

Set SM0_PINCTRL’s SIDESET_BASE field.

The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction’s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.

inline uint8_t get_SM0_PINCTRL_IN_BASE() volatile

Get SM0_PINCTRL’s IN_BASE field.

The pin which is mapped to the least-significant bit of a state machine’s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.

inline void set_SM0_PINCTRL_IN_BASE(uint8_t value) volatile

Set SM0_PINCTRL’s IN_BASE field.

The pin which is mapped to the least-significant bit of a state machine’s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.

inline uint8_t get_SM0_PINCTRL_OUT_COUNT() volatile

Get SM0_PINCTRL’s OUT_COUNT field.

The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.

inline void set_SM0_PINCTRL_OUT_COUNT(uint8_t value) volatile

Set SM0_PINCTRL’s OUT_COUNT field.

The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.

inline uint8_t get_SM0_PINCTRL_SET_COUNT() volatile

Get SM0_PINCTRL’s SET_COUNT field.

The number of pins asserted by a SET. In the range 0 to 5 inclusive.

inline void set_SM0_PINCTRL_SET_COUNT(uint8_t value) volatile

Set SM0_PINCTRL’s SET_COUNT field.

The number of pins asserted by a SET. In the range 0 to 5 inclusive.

inline uint8_t get_SM0_PINCTRL_SIDESET_COUNT() volatile

Get SM0_PINCTRL’s SIDESET_COUNT field.

The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).

inline void set_SM0_PINCTRL_SIDESET_COUNT(uint8_t value) volatile

Set SM0_PINCTRL’s SIDESET_COUNT field.

The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).

inline void get_SM0_PINCTRL(uint8_t &OUT_BASE, uint8_t &SET_BASE, uint8_t &SIDESET_BASE, uint8_t &IN_BASE, uint8_t &OUT_COUNT, uint8_t &SET_COUNT, uint8_t &SIDESET_COUNT) volatile

Get all of SM0_PINCTRL’s bit fields.

(read-write) State machine pin control

inline void set_SM0_PINCTRL(uint8_t OUT_BASE, uint8_t SET_BASE, uint8_t SIDESET_BASE, uint8_t IN_BASE, uint8_t OUT_COUNT, uint8_t SET_COUNT, uint8_t SIDESET_COUNT) volatile

Set all of SM0_PINCTRL’s bit fields.

(read-write) State machine pin control

inline uint8_t get_SM1_CLKDIV_FRAC() volatile

Get SM1_CLKDIV’s FRAC field.

Fractional part of clock divisor

inline void set_SM1_CLKDIV_FRAC(uint8_t value) volatile

Set SM1_CLKDIV’s FRAC field.

Fractional part of clock divisor

inline uint16_t get_SM1_CLKDIV_INT() volatile

Get SM1_CLKDIV’s INT field.

Effective frequency is sysclk/(int + frac/256).

Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.

inline void set_SM1_CLKDIV_INT(uint16_t value) volatile

Set SM1_CLKDIV’s INT field.

Effective frequency is sysclk/(int + frac/256).

Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.

inline void get_SM1_CLKDIV(uint8_t &FRAC, uint16_t &INT) volatile

Get all of SM1_CLKDIV’s bit fields.

(read-write) Clock divisor register for state machine 1

Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

inline void set_SM1_CLKDIV(uint8_t FRAC, uint16_t INT) volatile

Set all of SM1_CLKDIV’s bit fields.

(read-write) Clock divisor register for state machine 1

Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

inline uint8_t get_SM1_EXECCTRL_STATUS_N() volatile

Get SM1_EXECCTRL’s STATUS_N field.

Comparison level for the MOV x, STATUS instruction

inline void set_SM1_EXECCTRL_STATUS_N(uint8_t value) volatile

Set SM1_EXECCTRL’s STATUS_N field.

Comparison level for the MOV x, STATUS instruction

inline bool get_SM1_EXECCTRL_STATUS_SEL() volatile

Get SM1_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline void set_SM1_EXECCTRL_STATUS_SEL() volatile

Set SM1_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline void clear_SM1_EXECCTRL_STATUS_SEL() volatile

Clear SM1_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline void toggle_SM1_EXECCTRL_STATUS_SEL() volatile

Toggle SM1_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline uint8_t get_SM1_EXECCTRL_WRAP_BOTTOM() volatile

Get SM1_EXECCTRL’s WRAP_BOTTOM field.

After reaching wrap_top, execution is wrapped to this address.

inline void set_SM1_EXECCTRL_WRAP_BOTTOM(uint8_t value) volatile

Set SM1_EXECCTRL’s WRAP_BOTTOM field.

After reaching wrap_top, execution is wrapped to this address.

inline uint8_t get_SM1_EXECCTRL_WRAP_TOP() volatile

Get SM1_EXECCTRL’s WRAP_TOP field.

After reaching this address, execution is wrapped to wrap_bottom.

If the instruction is a jump, and the jump condition is true, the jump takes priority.

inline void set_SM1_EXECCTRL_WRAP_TOP(uint8_t value) volatile

Set SM1_EXECCTRL’s WRAP_TOP field.

After reaching this address, execution is wrapped to wrap_bottom.

If the instruction is a jump, and the jump condition is true, the jump takes priority.

inline bool get_SM1_EXECCTRL_OUT_STICKY() volatile

Get SM1_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline void set_SM1_EXECCTRL_OUT_STICKY() volatile

Set SM1_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline void clear_SM1_EXECCTRL_OUT_STICKY() volatile

Clear SM1_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline void toggle_SM1_EXECCTRL_OUT_STICKY() volatile

Toggle SM1_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline bool get_SM1_EXECCTRL_INLINE_OUT_EN() volatile

Get SM1_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline void set_SM1_EXECCTRL_INLINE_OUT_EN() volatile

Set SM1_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline void clear_SM1_EXECCTRL_INLINE_OUT_EN() volatile

Clear SM1_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline void toggle_SM1_EXECCTRL_INLINE_OUT_EN() volatile

Toggle SM1_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline uint8_t get_SM1_EXECCTRL_OUT_EN_SEL() volatile

Get SM1_EXECCTRL’s OUT_EN_SEL field.

Which data bit to use for inline OUT enable

inline void set_SM1_EXECCTRL_OUT_EN_SEL(uint8_t value) volatile

Set SM1_EXECCTRL’s OUT_EN_SEL field.

Which data bit to use for inline OUT enable

inline uint8_t get_SM1_EXECCTRL_JMP_PIN() volatile

Get SM1_EXECCTRL’s JMP_PIN field.

The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

inline void set_SM1_EXECCTRL_JMP_PIN(uint8_t value) volatile

Set SM1_EXECCTRL’s JMP_PIN field.

The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

inline bool get_SM1_EXECCTRL_SIDE_PINDIR() volatile

Get SM1_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline void set_SM1_EXECCTRL_SIDE_PINDIR() volatile

Set SM1_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline void clear_SM1_EXECCTRL_SIDE_PINDIR() volatile

Clear SM1_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline void toggle_SM1_EXECCTRL_SIDE_PINDIR() volatile

Toggle SM1_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline bool get_SM1_EXECCTRL_SIDE_EN() volatile

Get SM1_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline void set_SM1_EXECCTRL_SIDE_EN() volatile

Set SM1_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline void clear_SM1_EXECCTRL_SIDE_EN() volatile

Clear SM1_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline void toggle_SM1_EXECCTRL_SIDE_EN() volatile

Toggle SM1_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline bool get_SM1_EXECCTRL_EXEC_STALLED() volatile

Get SM1_EXECCTRL’s EXEC_STALLED bit.

If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.

inline void get_SM1_EXECCTRL(uint8_t &STATUS_N, bool &STATUS_SEL, uint8_t &WRAP_BOTTOM, uint8_t &WRAP_TOP, bool &OUT_STICKY, bool &INLINE_OUT_EN, uint8_t &OUT_EN_SEL, uint8_t &JMP_PIN, bool &SIDE_PINDIR, bool &SIDE_EN, bool &EXEC_STALLED) volatile

Get all of SM1_EXECCTRL’s bit fields.

(read-write) Execution/behavioural settings for state machine 1

inline void set_SM1_EXECCTRL(uint8_t STATUS_N, bool STATUS_SEL, uint8_t WRAP_BOTTOM, uint8_t WRAP_TOP, bool OUT_STICKY, bool INLINE_OUT_EN, uint8_t OUT_EN_SEL, uint8_t JMP_PIN, bool SIDE_PINDIR, bool SIDE_EN) volatile

Set all of SM1_EXECCTRL’s bit fields.

(read-write) Execution/behavioural settings for state machine 1

inline bool get_SM1_SHIFTCTRL_AUTOPUSH() volatile

Get SM1_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline void set_SM1_SHIFTCTRL_AUTOPUSH() volatile

Set SM1_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline void clear_SM1_SHIFTCTRL_AUTOPUSH() volatile

Clear SM1_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline void toggle_SM1_SHIFTCTRL_AUTOPUSH() volatile

Toggle SM1_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline bool get_SM1_SHIFTCTRL_AUTOPULL() volatile

Get SM1_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline void set_SM1_SHIFTCTRL_AUTOPULL() volatile

Set SM1_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline void clear_SM1_SHIFTCTRL_AUTOPULL() volatile

Clear SM1_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline void toggle_SM1_SHIFTCTRL_AUTOPULL() volatile

Toggle SM1_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline bool get_SM1_SHIFTCTRL_IN_SHIFTDIR() volatile

Get SM1_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline void set_SM1_SHIFTCTRL_IN_SHIFTDIR() volatile

Set SM1_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline void clear_SM1_SHIFTCTRL_IN_SHIFTDIR() volatile

Clear SM1_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline void toggle_SM1_SHIFTCTRL_IN_SHIFTDIR() volatile

Toggle SM1_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline bool get_SM1_SHIFTCTRL_OUT_SHIFTDIR() volatile

Get SM1_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline void set_SM1_SHIFTCTRL_OUT_SHIFTDIR() volatile

Set SM1_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline void clear_SM1_SHIFTCTRL_OUT_SHIFTDIR() volatile

Clear SM1_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline void toggle_SM1_SHIFTCTRL_OUT_SHIFTDIR() volatile

Toggle SM1_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline uint8_t get_SM1_SHIFTCTRL_PUSH_THRESH() volatile

Get SM1_SHIFTCTRL’s PUSH_THRESH field.

Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.

Write 0 for value of 32.

inline void set_SM1_SHIFTCTRL_PUSH_THRESH(uint8_t value) volatile

Set SM1_SHIFTCTRL’s PUSH_THRESH field.

Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.

Write 0 for value of 32.

inline uint8_t get_SM1_SHIFTCTRL_PULL_THRESH() volatile

Get SM1_SHIFTCTRL’s PULL_THRESH field.

Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.

Write 0 for value of 32.

inline void set_SM1_SHIFTCTRL_PULL_THRESH(uint8_t value) volatile

Set SM1_SHIFTCTRL’s PULL_THRESH field.

Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.

Write 0 for value of 32.

inline bool get_SM1_SHIFTCTRL_FJOIN_TX() volatile

Get SM1_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void set_SM1_SHIFTCTRL_FJOIN_TX() volatile

Set SM1_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void clear_SM1_SHIFTCTRL_FJOIN_TX() volatile

Clear SM1_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void toggle_SM1_SHIFTCTRL_FJOIN_TX() volatile

Toggle SM1_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline bool get_SM1_SHIFTCTRL_FJOIN_RX() volatile

Get SM1_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void set_SM1_SHIFTCTRL_FJOIN_RX() volatile

Set SM1_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void clear_SM1_SHIFTCTRL_FJOIN_RX() volatile

Clear SM1_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void toggle_SM1_SHIFTCTRL_FJOIN_RX() volatile

Toggle SM1_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void get_SM1_SHIFTCTRL(bool &AUTOPUSH, bool &AUTOPULL, bool &IN_SHIFTDIR, bool &OUT_SHIFTDIR, uint8_t &PUSH_THRESH, uint8_t &PULL_THRESH, bool &FJOIN_TX, bool &FJOIN_RX) volatile

Get all of SM1_SHIFTCTRL’s bit fields.

(read-write) Control behaviour of the input/output shift registers for state machine 1

inline void set_SM1_SHIFTCTRL(bool AUTOPUSH, bool AUTOPULL, bool IN_SHIFTDIR, bool OUT_SHIFTDIR, uint8_t PUSH_THRESH, uint8_t PULL_THRESH, bool FJOIN_TX, bool FJOIN_RX) volatile

Set all of SM1_SHIFTCTRL’s bit fields.

(read-write) Control behaviour of the input/output shift registers for state machine 1

inline uint8_t get_SM1_ADDR_SM1_ADDR() volatile

Get SM1_ADDR’s SM1_ADDR field.

inline uint16_t get_SM1_INSTR_SM1_INSTR() volatile

Get SM1_INSTR’s SM1_INSTR field.

inline void set_SM1_INSTR_SM1_INSTR(uint16_t value) volatile

Set SM1_INSTR’s SM1_INSTR field.

inline uint8_t get_SM1_PINCTRL_OUT_BASE() volatile

Get SM1_PINCTRL’s OUT_BASE field.

The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.

inline void set_SM1_PINCTRL_OUT_BASE(uint8_t value) volatile

Set SM1_PINCTRL’s OUT_BASE field.

The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.

inline uint8_t get_SM1_PINCTRL_SET_BASE() volatile

Get SM1_PINCTRL’s SET_BASE field.

The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.

inline void set_SM1_PINCTRL_SET_BASE(uint8_t value) volatile

Set SM1_PINCTRL’s SET_BASE field.

The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.

inline uint8_t get_SM1_PINCTRL_SIDESET_BASE() volatile

Get SM1_PINCTRL’s SIDESET_BASE field.

The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction’s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.

inline void set_SM1_PINCTRL_SIDESET_BASE(uint8_t value) volatile

Set SM1_PINCTRL’s SIDESET_BASE field.

The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction’s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.

inline uint8_t get_SM1_PINCTRL_IN_BASE() volatile

Get SM1_PINCTRL’s IN_BASE field.

The pin which is mapped to the least-significant bit of a state machine’s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.

inline void set_SM1_PINCTRL_IN_BASE(uint8_t value) volatile

Set SM1_PINCTRL’s IN_BASE field.

The pin which is mapped to the least-significant bit of a state machine’s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.

inline uint8_t get_SM1_PINCTRL_OUT_COUNT() volatile

Get SM1_PINCTRL’s OUT_COUNT field.

The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.

inline void set_SM1_PINCTRL_OUT_COUNT(uint8_t value) volatile

Set SM1_PINCTRL’s OUT_COUNT field.

The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.

inline uint8_t get_SM1_PINCTRL_SET_COUNT() volatile

Get SM1_PINCTRL’s SET_COUNT field.

The number of pins asserted by a SET. In the range 0 to 5 inclusive.

inline void set_SM1_PINCTRL_SET_COUNT(uint8_t value) volatile

Set SM1_PINCTRL’s SET_COUNT field.

The number of pins asserted by a SET. In the range 0 to 5 inclusive.

inline uint8_t get_SM1_PINCTRL_SIDESET_COUNT() volatile

Get SM1_PINCTRL’s SIDESET_COUNT field.

The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).

inline void set_SM1_PINCTRL_SIDESET_COUNT(uint8_t value) volatile

Set SM1_PINCTRL’s SIDESET_COUNT field.

The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).

inline void get_SM1_PINCTRL(uint8_t &OUT_BASE, uint8_t &SET_BASE, uint8_t &SIDESET_BASE, uint8_t &IN_BASE, uint8_t &OUT_COUNT, uint8_t &SET_COUNT, uint8_t &SIDESET_COUNT) volatile

Get all of SM1_PINCTRL’s bit fields.

(read-write) State machine pin control

inline void set_SM1_PINCTRL(uint8_t OUT_BASE, uint8_t SET_BASE, uint8_t SIDESET_BASE, uint8_t IN_BASE, uint8_t OUT_COUNT, uint8_t SET_COUNT, uint8_t SIDESET_COUNT) volatile

Set all of SM1_PINCTRL’s bit fields.

(read-write) State machine pin control

inline uint8_t get_SM2_CLKDIV_FRAC() volatile

Get SM2_CLKDIV’s FRAC field.

Fractional part of clock divisor

inline void set_SM2_CLKDIV_FRAC(uint8_t value) volatile

Set SM2_CLKDIV’s FRAC field.

Fractional part of clock divisor

inline uint16_t get_SM2_CLKDIV_INT() volatile

Get SM2_CLKDIV’s INT field.

Effective frequency is sysclk/(int + frac/256).

Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.

inline void set_SM2_CLKDIV_INT(uint16_t value) volatile

Set SM2_CLKDIV’s INT field.

Effective frequency is sysclk/(int + frac/256).

Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.

inline void get_SM2_CLKDIV(uint8_t &FRAC, uint16_t &INT) volatile

Get all of SM2_CLKDIV’s bit fields.

(read-write) Clock divisor register for state machine 2

Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

inline void set_SM2_CLKDIV(uint8_t FRAC, uint16_t INT) volatile

Set all of SM2_CLKDIV’s bit fields.

(read-write) Clock divisor register for state machine 2

Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

inline uint8_t get_SM2_EXECCTRL_STATUS_N() volatile

Get SM2_EXECCTRL’s STATUS_N field.

Comparison level for the MOV x, STATUS instruction

inline void set_SM2_EXECCTRL_STATUS_N(uint8_t value) volatile

Set SM2_EXECCTRL’s STATUS_N field.

Comparison level for the MOV x, STATUS instruction

inline bool get_SM2_EXECCTRL_STATUS_SEL() volatile

Get SM2_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline void set_SM2_EXECCTRL_STATUS_SEL() volatile

Set SM2_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline void clear_SM2_EXECCTRL_STATUS_SEL() volatile

Clear SM2_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline void toggle_SM2_EXECCTRL_STATUS_SEL() volatile

Toggle SM2_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline uint8_t get_SM2_EXECCTRL_WRAP_BOTTOM() volatile

Get SM2_EXECCTRL’s WRAP_BOTTOM field.

After reaching wrap_top, execution is wrapped to this address.

inline void set_SM2_EXECCTRL_WRAP_BOTTOM(uint8_t value) volatile

Set SM2_EXECCTRL’s WRAP_BOTTOM field.

After reaching wrap_top, execution is wrapped to this address.

inline uint8_t get_SM2_EXECCTRL_WRAP_TOP() volatile

Get SM2_EXECCTRL’s WRAP_TOP field.

After reaching this address, execution is wrapped to wrap_bottom.

If the instruction is a jump, and the jump condition is true, the jump takes priority.

inline void set_SM2_EXECCTRL_WRAP_TOP(uint8_t value) volatile

Set SM2_EXECCTRL’s WRAP_TOP field.

After reaching this address, execution is wrapped to wrap_bottom.

If the instruction is a jump, and the jump condition is true, the jump takes priority.

inline bool get_SM2_EXECCTRL_OUT_STICKY() volatile

Get SM2_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline void set_SM2_EXECCTRL_OUT_STICKY() volatile

Set SM2_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline void clear_SM2_EXECCTRL_OUT_STICKY() volatile

Clear SM2_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline void toggle_SM2_EXECCTRL_OUT_STICKY() volatile

Toggle SM2_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline bool get_SM2_EXECCTRL_INLINE_OUT_EN() volatile

Get SM2_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline void set_SM2_EXECCTRL_INLINE_OUT_EN() volatile

Set SM2_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline void clear_SM2_EXECCTRL_INLINE_OUT_EN() volatile

Clear SM2_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline void toggle_SM2_EXECCTRL_INLINE_OUT_EN() volatile

Toggle SM2_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline uint8_t get_SM2_EXECCTRL_OUT_EN_SEL() volatile

Get SM2_EXECCTRL’s OUT_EN_SEL field.

Which data bit to use for inline OUT enable

inline void set_SM2_EXECCTRL_OUT_EN_SEL(uint8_t value) volatile

Set SM2_EXECCTRL’s OUT_EN_SEL field.

Which data bit to use for inline OUT enable

inline uint8_t get_SM2_EXECCTRL_JMP_PIN() volatile

Get SM2_EXECCTRL’s JMP_PIN field.

The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

inline void set_SM2_EXECCTRL_JMP_PIN(uint8_t value) volatile

Set SM2_EXECCTRL’s JMP_PIN field.

The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

inline bool get_SM2_EXECCTRL_SIDE_PINDIR() volatile

Get SM2_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline void set_SM2_EXECCTRL_SIDE_PINDIR() volatile

Set SM2_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline void clear_SM2_EXECCTRL_SIDE_PINDIR() volatile

Clear SM2_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline void toggle_SM2_EXECCTRL_SIDE_PINDIR() volatile

Toggle SM2_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline bool get_SM2_EXECCTRL_SIDE_EN() volatile

Get SM2_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline void set_SM2_EXECCTRL_SIDE_EN() volatile

Set SM2_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline void clear_SM2_EXECCTRL_SIDE_EN() volatile

Clear SM2_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline void toggle_SM2_EXECCTRL_SIDE_EN() volatile

Toggle SM2_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline bool get_SM2_EXECCTRL_EXEC_STALLED() volatile

Get SM2_EXECCTRL’s EXEC_STALLED bit.

If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.

inline void get_SM2_EXECCTRL(uint8_t &STATUS_N, bool &STATUS_SEL, uint8_t &WRAP_BOTTOM, uint8_t &WRAP_TOP, bool &OUT_STICKY, bool &INLINE_OUT_EN, uint8_t &OUT_EN_SEL, uint8_t &JMP_PIN, bool &SIDE_PINDIR, bool &SIDE_EN, bool &EXEC_STALLED) volatile

Get all of SM2_EXECCTRL’s bit fields.

(read-write) Execution/behavioural settings for state machine 2

inline void set_SM2_EXECCTRL(uint8_t STATUS_N, bool STATUS_SEL, uint8_t WRAP_BOTTOM, uint8_t WRAP_TOP, bool OUT_STICKY, bool INLINE_OUT_EN, uint8_t OUT_EN_SEL, uint8_t JMP_PIN, bool SIDE_PINDIR, bool SIDE_EN) volatile

Set all of SM2_EXECCTRL’s bit fields.

(read-write) Execution/behavioural settings for state machine 2

inline bool get_SM2_SHIFTCTRL_AUTOPUSH() volatile

Get SM2_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline void set_SM2_SHIFTCTRL_AUTOPUSH() volatile

Set SM2_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline void clear_SM2_SHIFTCTRL_AUTOPUSH() volatile

Clear SM2_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline void toggle_SM2_SHIFTCTRL_AUTOPUSH() volatile

Toggle SM2_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline bool get_SM2_SHIFTCTRL_AUTOPULL() volatile

Get SM2_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline void set_SM2_SHIFTCTRL_AUTOPULL() volatile

Set SM2_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline void clear_SM2_SHIFTCTRL_AUTOPULL() volatile

Clear SM2_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline void toggle_SM2_SHIFTCTRL_AUTOPULL() volatile

Toggle SM2_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline bool get_SM2_SHIFTCTRL_IN_SHIFTDIR() volatile

Get SM2_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline void set_SM2_SHIFTCTRL_IN_SHIFTDIR() volatile

Set SM2_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline void clear_SM2_SHIFTCTRL_IN_SHIFTDIR() volatile

Clear SM2_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline void toggle_SM2_SHIFTCTRL_IN_SHIFTDIR() volatile

Toggle SM2_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline bool get_SM2_SHIFTCTRL_OUT_SHIFTDIR() volatile

Get SM2_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline void set_SM2_SHIFTCTRL_OUT_SHIFTDIR() volatile

Set SM2_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline void clear_SM2_SHIFTCTRL_OUT_SHIFTDIR() volatile

Clear SM2_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline void toggle_SM2_SHIFTCTRL_OUT_SHIFTDIR() volatile

Toggle SM2_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline uint8_t get_SM2_SHIFTCTRL_PUSH_THRESH() volatile

Get SM2_SHIFTCTRL’s PUSH_THRESH field.

Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.

Write 0 for value of 32.

inline void set_SM2_SHIFTCTRL_PUSH_THRESH(uint8_t value) volatile

Set SM2_SHIFTCTRL’s PUSH_THRESH field.

Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.

Write 0 for value of 32.

inline uint8_t get_SM2_SHIFTCTRL_PULL_THRESH() volatile

Get SM2_SHIFTCTRL’s PULL_THRESH field.

Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.

Write 0 for value of 32.

inline void set_SM2_SHIFTCTRL_PULL_THRESH(uint8_t value) volatile

Set SM2_SHIFTCTRL’s PULL_THRESH field.

Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.

Write 0 for value of 32.

inline bool get_SM2_SHIFTCTRL_FJOIN_TX() volatile

Get SM2_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void set_SM2_SHIFTCTRL_FJOIN_TX() volatile

Set SM2_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void clear_SM2_SHIFTCTRL_FJOIN_TX() volatile

Clear SM2_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void toggle_SM2_SHIFTCTRL_FJOIN_TX() volatile

Toggle SM2_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline bool get_SM2_SHIFTCTRL_FJOIN_RX() volatile

Get SM2_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void set_SM2_SHIFTCTRL_FJOIN_RX() volatile

Set SM2_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void clear_SM2_SHIFTCTRL_FJOIN_RX() volatile

Clear SM2_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void toggle_SM2_SHIFTCTRL_FJOIN_RX() volatile

Toggle SM2_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void get_SM2_SHIFTCTRL(bool &AUTOPUSH, bool &AUTOPULL, bool &IN_SHIFTDIR, bool &OUT_SHIFTDIR, uint8_t &PUSH_THRESH, uint8_t &PULL_THRESH, bool &FJOIN_TX, bool &FJOIN_RX) volatile

Get all of SM2_SHIFTCTRL’s bit fields.

(read-write) Control behaviour of the input/output shift registers for state machine 2

inline void set_SM2_SHIFTCTRL(bool AUTOPUSH, bool AUTOPULL, bool IN_SHIFTDIR, bool OUT_SHIFTDIR, uint8_t PUSH_THRESH, uint8_t PULL_THRESH, bool FJOIN_TX, bool FJOIN_RX) volatile

Set all of SM2_SHIFTCTRL’s bit fields.

(read-write) Control behaviour of the input/output shift registers for state machine 2

inline uint8_t get_SM2_ADDR_SM2_ADDR() volatile

Get SM2_ADDR’s SM2_ADDR field.

inline uint16_t get_SM2_INSTR_SM2_INSTR() volatile

Get SM2_INSTR’s SM2_INSTR field.

inline void set_SM2_INSTR_SM2_INSTR(uint16_t value) volatile

Set SM2_INSTR’s SM2_INSTR field.

inline uint8_t get_SM2_PINCTRL_OUT_BASE() volatile

Get SM2_PINCTRL’s OUT_BASE field.

The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.

inline void set_SM2_PINCTRL_OUT_BASE(uint8_t value) volatile

Set SM2_PINCTRL’s OUT_BASE field.

The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.

inline uint8_t get_SM2_PINCTRL_SET_BASE() volatile

Get SM2_PINCTRL’s SET_BASE field.

The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.

inline void set_SM2_PINCTRL_SET_BASE(uint8_t value) volatile

Set SM2_PINCTRL’s SET_BASE field.

The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.

inline uint8_t get_SM2_PINCTRL_SIDESET_BASE() volatile

Get SM2_PINCTRL’s SIDESET_BASE field.

The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction’s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.

inline void set_SM2_PINCTRL_SIDESET_BASE(uint8_t value) volatile

Set SM2_PINCTRL’s SIDESET_BASE field.

The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction’s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.

inline uint8_t get_SM2_PINCTRL_IN_BASE() volatile

Get SM2_PINCTRL’s IN_BASE field.

The pin which is mapped to the least-significant bit of a state machine’s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.

inline void set_SM2_PINCTRL_IN_BASE(uint8_t value) volatile

Set SM2_PINCTRL’s IN_BASE field.

The pin which is mapped to the least-significant bit of a state machine’s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.

inline uint8_t get_SM2_PINCTRL_OUT_COUNT() volatile

Get SM2_PINCTRL’s OUT_COUNT field.

The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.

inline void set_SM2_PINCTRL_OUT_COUNT(uint8_t value) volatile

Set SM2_PINCTRL’s OUT_COUNT field.

The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.

inline uint8_t get_SM2_PINCTRL_SET_COUNT() volatile

Get SM2_PINCTRL’s SET_COUNT field.

The number of pins asserted by a SET. In the range 0 to 5 inclusive.

inline void set_SM2_PINCTRL_SET_COUNT(uint8_t value) volatile

Set SM2_PINCTRL’s SET_COUNT field.

The number of pins asserted by a SET. In the range 0 to 5 inclusive.

inline uint8_t get_SM2_PINCTRL_SIDESET_COUNT() volatile

Get SM2_PINCTRL’s SIDESET_COUNT field.

The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).

inline void set_SM2_PINCTRL_SIDESET_COUNT(uint8_t value) volatile

Set SM2_PINCTRL’s SIDESET_COUNT field.

The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).

inline void get_SM2_PINCTRL(uint8_t &OUT_BASE, uint8_t &SET_BASE, uint8_t &SIDESET_BASE, uint8_t &IN_BASE, uint8_t &OUT_COUNT, uint8_t &SET_COUNT, uint8_t &SIDESET_COUNT) volatile

Get all of SM2_PINCTRL’s bit fields.

(read-write) State machine pin control

inline void set_SM2_PINCTRL(uint8_t OUT_BASE, uint8_t SET_BASE, uint8_t SIDESET_BASE, uint8_t IN_BASE, uint8_t OUT_COUNT, uint8_t SET_COUNT, uint8_t SIDESET_COUNT) volatile

Set all of SM2_PINCTRL’s bit fields.

(read-write) State machine pin control

inline uint8_t get_SM3_CLKDIV_FRAC() volatile

Get SM3_CLKDIV’s FRAC field.

Fractional part of clock divisor

inline void set_SM3_CLKDIV_FRAC(uint8_t value) volatile

Set SM3_CLKDIV’s FRAC field.

Fractional part of clock divisor

inline uint16_t get_SM3_CLKDIV_INT() volatile

Get SM3_CLKDIV’s INT field.

Effective frequency is sysclk/(int + frac/256).

Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.

inline void set_SM3_CLKDIV_INT(uint16_t value) volatile

Set SM3_CLKDIV’s INT field.

Effective frequency is sysclk/(int + frac/256).

Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.

inline void get_SM3_CLKDIV(uint8_t &FRAC, uint16_t &INT) volatile

Get all of SM3_CLKDIV’s bit fields.

(read-write) Clock divisor register for state machine 3

Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

inline void set_SM3_CLKDIV(uint8_t FRAC, uint16_t INT) volatile

Set all of SM3_CLKDIV’s bit fields.

(read-write) Clock divisor register for state machine 3

Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

inline uint8_t get_SM3_EXECCTRL_STATUS_N() volatile

Get SM3_EXECCTRL’s STATUS_N field.

Comparison level for the MOV x, STATUS instruction

inline void set_SM3_EXECCTRL_STATUS_N(uint8_t value) volatile

Set SM3_EXECCTRL’s STATUS_N field.

Comparison level for the MOV x, STATUS instruction

inline bool get_SM3_EXECCTRL_STATUS_SEL() volatile

Get SM3_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline void set_SM3_EXECCTRL_STATUS_SEL() volatile

Set SM3_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline void clear_SM3_EXECCTRL_STATUS_SEL() volatile

Clear SM3_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline void toggle_SM3_EXECCTRL_STATUS_SEL() volatile

Toggle SM3_EXECCTRL’s STATUS_SEL bit.

Comparison used for the MOV x, STATUS instruction.

inline uint8_t get_SM3_EXECCTRL_WRAP_BOTTOM() volatile

Get SM3_EXECCTRL’s WRAP_BOTTOM field.

After reaching wrap_top, execution is wrapped to this address.

inline void set_SM3_EXECCTRL_WRAP_BOTTOM(uint8_t value) volatile

Set SM3_EXECCTRL’s WRAP_BOTTOM field.

After reaching wrap_top, execution is wrapped to this address.

inline uint8_t get_SM3_EXECCTRL_WRAP_TOP() volatile

Get SM3_EXECCTRL’s WRAP_TOP field.

After reaching this address, execution is wrapped to wrap_bottom.

If the instruction is a jump, and the jump condition is true, the jump takes priority.

inline void set_SM3_EXECCTRL_WRAP_TOP(uint8_t value) volatile

Set SM3_EXECCTRL’s WRAP_TOP field.

After reaching this address, execution is wrapped to wrap_bottom.

If the instruction is a jump, and the jump condition is true, the jump takes priority.

inline bool get_SM3_EXECCTRL_OUT_STICKY() volatile

Get SM3_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline void set_SM3_EXECCTRL_OUT_STICKY() volatile

Set SM3_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline void clear_SM3_EXECCTRL_OUT_STICKY() volatile

Clear SM3_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline void toggle_SM3_EXECCTRL_OUT_STICKY() volatile

Toggle SM3_EXECCTRL’s OUT_STICKY bit.

Continuously assert the most recent OUT/SET to the pins

inline bool get_SM3_EXECCTRL_INLINE_OUT_EN() volatile

Get SM3_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline void set_SM3_EXECCTRL_INLINE_OUT_EN() volatile

Set SM3_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline void clear_SM3_EXECCTRL_INLINE_OUT_EN() volatile

Clear SM3_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline void toggle_SM3_EXECCTRL_INLINE_OUT_EN() volatile

Toggle SM3_EXECCTRL’s INLINE_OUT_EN bit.

If 1, use a bit of OUT data as an auxiliary write enable

When used in conjunction with OUT_STICKY, writes with an enable of 0 will

deassert the latest pin write. This can create useful masking/override behaviour

due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

inline uint8_t get_SM3_EXECCTRL_OUT_EN_SEL() volatile

Get SM3_EXECCTRL’s OUT_EN_SEL field.

Which data bit to use for inline OUT enable

inline void set_SM3_EXECCTRL_OUT_EN_SEL(uint8_t value) volatile

Set SM3_EXECCTRL’s OUT_EN_SEL field.

Which data bit to use for inline OUT enable

inline uint8_t get_SM3_EXECCTRL_JMP_PIN() volatile

Get SM3_EXECCTRL’s JMP_PIN field.

The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

inline void set_SM3_EXECCTRL_JMP_PIN(uint8_t value) volatile

Set SM3_EXECCTRL’s JMP_PIN field.

The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

inline bool get_SM3_EXECCTRL_SIDE_PINDIR() volatile

Get SM3_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline void set_SM3_EXECCTRL_SIDE_PINDIR() volatile

Set SM3_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline void clear_SM3_EXECCTRL_SIDE_PINDIR() volatile

Clear SM3_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline void toggle_SM3_EXECCTRL_SIDE_PINDIR() volatile

Toggle SM3_EXECCTRL’s SIDE_PINDIR bit.

If 1, side-set data is asserted to pin directions, instead of pin values

inline bool get_SM3_EXECCTRL_SIDE_EN() volatile

Get SM3_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline void set_SM3_EXECCTRL_SIDE_EN() volatile

Set SM3_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline void clear_SM3_EXECCTRL_SIDE_EN() volatile

Clear SM3_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline void toggle_SM3_EXECCTRL_SIDE_EN() volatile

Toggle SM3_EXECCTRL’s SIDE_EN bit.

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

inline bool get_SM3_EXECCTRL_EXEC_STALLED() volatile

Get SM3_EXECCTRL’s EXEC_STALLED bit.

If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.

inline void get_SM3_EXECCTRL(uint8_t &STATUS_N, bool &STATUS_SEL, uint8_t &WRAP_BOTTOM, uint8_t &WRAP_TOP, bool &OUT_STICKY, bool &INLINE_OUT_EN, uint8_t &OUT_EN_SEL, uint8_t &JMP_PIN, bool &SIDE_PINDIR, bool &SIDE_EN, bool &EXEC_STALLED) volatile

Get all of SM3_EXECCTRL’s bit fields.

(read-write) Execution/behavioural settings for state machine 3

inline void set_SM3_EXECCTRL(uint8_t STATUS_N, bool STATUS_SEL, uint8_t WRAP_BOTTOM, uint8_t WRAP_TOP, bool OUT_STICKY, bool INLINE_OUT_EN, uint8_t OUT_EN_SEL, uint8_t JMP_PIN, bool SIDE_PINDIR, bool SIDE_EN) volatile

Set all of SM3_EXECCTRL’s bit fields.

(read-write) Execution/behavioural settings for state machine 3

inline bool get_SM3_SHIFTCTRL_AUTOPUSH() volatile

Get SM3_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline void set_SM3_SHIFTCTRL_AUTOPUSH() volatile

Set SM3_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline void clear_SM3_SHIFTCTRL_AUTOPUSH() volatile

Clear SM3_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline void toggle_SM3_SHIFTCTRL_AUTOPUSH() volatile

Toggle SM3_SHIFTCTRL’s AUTOPUSH bit.

Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.

inline bool get_SM3_SHIFTCTRL_AUTOPULL() volatile

Get SM3_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline void set_SM3_SHIFTCTRL_AUTOPULL() volatile

Set SM3_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline void clear_SM3_SHIFTCTRL_AUTOPULL() volatile

Clear SM3_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline void toggle_SM3_SHIFTCTRL_AUTOPULL() volatile

Toggle SM3_SHIFTCTRL’s AUTOPULL bit.

Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.

inline bool get_SM3_SHIFTCTRL_IN_SHIFTDIR() volatile

Get SM3_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline void set_SM3_SHIFTCTRL_IN_SHIFTDIR() volatile

Set SM3_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline void clear_SM3_SHIFTCTRL_IN_SHIFTDIR() volatile

Clear SM3_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline void toggle_SM3_SHIFTCTRL_IN_SHIFTDIR() volatile

Toggle SM3_SHIFTCTRL’s IN_SHIFTDIR bit.

1 = shift input shift register to right (data enters from left). 0 = to left.

inline bool get_SM3_SHIFTCTRL_OUT_SHIFTDIR() volatile

Get SM3_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline void set_SM3_SHIFTCTRL_OUT_SHIFTDIR() volatile

Set SM3_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline void clear_SM3_SHIFTCTRL_OUT_SHIFTDIR() volatile

Clear SM3_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline void toggle_SM3_SHIFTCTRL_OUT_SHIFTDIR() volatile

Toggle SM3_SHIFTCTRL’s OUT_SHIFTDIR bit.

1 = shift out of output shift register to right. 0 = to left.

inline uint8_t get_SM3_SHIFTCTRL_PUSH_THRESH() volatile

Get SM3_SHIFTCTRL’s PUSH_THRESH field.

Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.

Write 0 for value of 32.

inline void set_SM3_SHIFTCTRL_PUSH_THRESH(uint8_t value) volatile

Set SM3_SHIFTCTRL’s PUSH_THRESH field.

Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.

Write 0 for value of 32.

inline uint8_t get_SM3_SHIFTCTRL_PULL_THRESH() volatile

Get SM3_SHIFTCTRL’s PULL_THRESH field.

Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.

Write 0 for value of 32.

inline void set_SM3_SHIFTCTRL_PULL_THRESH(uint8_t value) volatile

Set SM3_SHIFTCTRL’s PULL_THRESH field.

Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.

Write 0 for value of 32.

inline bool get_SM3_SHIFTCTRL_FJOIN_TX() volatile

Get SM3_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void set_SM3_SHIFTCTRL_FJOIN_TX() volatile

Set SM3_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void clear_SM3_SHIFTCTRL_FJOIN_TX() volatile

Clear SM3_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void toggle_SM3_SHIFTCTRL_FJOIN_TX() volatile

Toggle SM3_SHIFTCTRL’s FJOIN_TX bit.

When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep.

RX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline bool get_SM3_SHIFTCTRL_FJOIN_RX() volatile

Get SM3_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void set_SM3_SHIFTCTRL_FJOIN_RX() volatile

Set SM3_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void clear_SM3_SHIFTCTRL_FJOIN_RX() volatile

Clear SM3_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void toggle_SM3_SHIFTCTRL_FJOIN_RX() volatile

Toggle SM3_SHIFTCTRL’s FJOIN_RX bit.

When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep.

TX FIFO is disabled as a result (always reads as both full and empty).

FIFOs are flushed when this bit is changed.

inline void get_SM3_SHIFTCTRL(bool &AUTOPUSH, bool &AUTOPULL, bool &IN_SHIFTDIR, bool &OUT_SHIFTDIR, uint8_t &PUSH_THRESH, uint8_t &PULL_THRESH, bool &FJOIN_TX, bool &FJOIN_RX) volatile

Get all of SM3_SHIFTCTRL’s bit fields.

(read-write) Control behaviour of the input/output shift registers for state machine 3

inline void set_SM3_SHIFTCTRL(bool AUTOPUSH, bool AUTOPULL, bool IN_SHIFTDIR, bool OUT_SHIFTDIR, uint8_t PUSH_THRESH, uint8_t PULL_THRESH, bool FJOIN_TX, bool FJOIN_RX) volatile

Set all of SM3_SHIFTCTRL’s bit fields.

(read-write) Control behaviour of the input/output shift registers for state machine 3

inline uint8_t get_SM3_ADDR_SM3_ADDR() volatile

Get SM3_ADDR’s SM3_ADDR field.

inline uint16_t get_SM3_INSTR_SM3_INSTR() volatile

Get SM3_INSTR’s SM3_INSTR field.

inline void set_SM3_INSTR_SM3_INSTR(uint16_t value) volatile

Set SM3_INSTR’s SM3_INSTR field.

inline uint8_t get_SM3_PINCTRL_OUT_BASE() volatile

Get SM3_PINCTRL’s OUT_BASE field.

The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.

inline void set_SM3_PINCTRL_OUT_BASE(uint8_t value) volatile

Set SM3_PINCTRL’s OUT_BASE field.

The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.

inline uint8_t get_SM3_PINCTRL_SET_BASE() volatile

Get SM3_PINCTRL’s SET_BASE field.

The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.

inline void set_SM3_PINCTRL_SET_BASE(uint8_t value) volatile

Set SM3_PINCTRL’s SET_BASE field.

The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.

inline uint8_t get_SM3_PINCTRL_SIDESET_BASE() volatile

Get SM3_PINCTRL’s SIDESET_BASE field.

The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction’s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.

inline void set_SM3_PINCTRL_SIDESET_BASE(uint8_t value) volatile

Set SM3_PINCTRL’s SIDESET_BASE field.

The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction’s side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.

inline uint8_t get_SM3_PINCTRL_IN_BASE() volatile

Get SM3_PINCTRL’s IN_BASE field.

The pin which is mapped to the least-significant bit of a state machine’s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.

inline void set_SM3_PINCTRL_IN_BASE(uint8_t value) volatile

Set SM3_PINCTRL’s IN_BASE field.

The pin which is mapped to the least-significant bit of a state machine’s IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.

inline uint8_t get_SM3_PINCTRL_OUT_COUNT() volatile

Get SM3_PINCTRL’s OUT_COUNT field.

The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.

inline void set_SM3_PINCTRL_OUT_COUNT(uint8_t value) volatile

Set SM3_PINCTRL’s OUT_COUNT field.

The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.

inline uint8_t get_SM3_PINCTRL_SET_COUNT() volatile

Get SM3_PINCTRL’s SET_COUNT field.

The number of pins asserted by a SET. In the range 0 to 5 inclusive.

inline void set_SM3_PINCTRL_SET_COUNT(uint8_t value) volatile

Set SM3_PINCTRL’s SET_COUNT field.

The number of pins asserted by a SET. In the range 0 to 5 inclusive.

inline uint8_t get_SM3_PINCTRL_SIDESET_COUNT() volatile

Get SM3_PINCTRL’s SIDESET_COUNT field.

The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).

inline void set_SM3_PINCTRL_SIDESET_COUNT(uint8_t value) volatile

Set SM3_PINCTRL’s SIDESET_COUNT field.

The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).

inline void get_SM3_PINCTRL(uint8_t &OUT_BASE, uint8_t &SET_BASE, uint8_t &SIDESET_BASE, uint8_t &IN_BASE, uint8_t &OUT_COUNT, uint8_t &SET_COUNT, uint8_t &SIDESET_COUNT) volatile

Get all of SM3_PINCTRL’s bit fields.

(read-write) State machine pin control

inline void set_SM3_PINCTRL(uint8_t OUT_BASE, uint8_t SET_BASE, uint8_t SIDESET_BASE, uint8_t IN_BASE, uint8_t OUT_COUNT, uint8_t SET_COUNT, uint8_t SIDESET_COUNT) volatile

Set all of SM3_PINCTRL’s bit fields.

(read-write) State machine pin control

inline bool get_INTR_SM0_RXNEMPTY() volatile

Get INTR’s SM0_RXNEMPTY bit.

inline bool get_INTR_SM1_RXNEMPTY() volatile

Get INTR’s SM1_RXNEMPTY bit.

inline bool get_INTR_SM2_RXNEMPTY() volatile

Get INTR’s SM2_RXNEMPTY bit.

inline bool get_INTR_SM3_RXNEMPTY() volatile

Get INTR’s SM3_RXNEMPTY bit.

inline bool get_INTR_SM0_TXNFULL() volatile

Get INTR’s SM0_TXNFULL bit.

inline bool get_INTR_SM1_TXNFULL() volatile

Get INTR’s SM1_TXNFULL bit.

inline bool get_INTR_SM2_TXNFULL() volatile

Get INTR’s SM2_TXNFULL bit.

inline bool get_INTR_SM3_TXNFULL() volatile

Get INTR’s SM3_TXNFULL bit.

inline bool get_INTR_SM0() volatile

Get INTR’s SM0 bit.

inline bool get_INTR_SM1() volatile

Get INTR’s SM1 bit.

inline bool get_INTR_SM2() volatile

Get INTR’s SM2 bit.

inline bool get_INTR_SM3() volatile

Get INTR’s SM3 bit.

inline void get_INTR(bool &SM0_RXNEMPTY, bool &SM1_RXNEMPTY, bool &SM2_RXNEMPTY, bool &SM3_RXNEMPTY, bool &SM0_TXNFULL, bool &SM1_TXNFULL, bool &SM2_TXNFULL, bool &SM3_TXNFULL, bool &SM0, bool &SM1, bool &SM2, bool &SM3) volatile

Get all of INTR’s bit fields.

(read-only) Raw Interrupts

inline bool get_IRQ0_INTE_SM0_RXNEMPTY() volatile

Get IRQ0_INTE’s SM0_RXNEMPTY bit.

inline void set_IRQ0_INTE_SM0_RXNEMPTY() volatile

Set IRQ0_INTE’s SM0_RXNEMPTY bit.

inline void clear_IRQ0_INTE_SM0_RXNEMPTY() volatile

Clear IRQ0_INTE’s SM0_RXNEMPTY bit.

inline void toggle_IRQ0_INTE_SM0_RXNEMPTY() volatile

Toggle IRQ0_INTE’s SM0_RXNEMPTY bit.

inline bool get_IRQ0_INTE_SM1_RXNEMPTY() volatile

Get IRQ0_INTE’s SM1_RXNEMPTY bit.

inline void set_IRQ0_INTE_SM1_RXNEMPTY() volatile

Set IRQ0_INTE’s SM1_RXNEMPTY bit.

inline void clear_IRQ0_INTE_SM1_RXNEMPTY() volatile

Clear IRQ0_INTE’s SM1_RXNEMPTY bit.

inline void toggle_IRQ0_INTE_SM1_RXNEMPTY() volatile

Toggle IRQ0_INTE’s SM1_RXNEMPTY bit.

inline bool get_IRQ0_INTE_SM2_RXNEMPTY() volatile

Get IRQ0_INTE’s SM2_RXNEMPTY bit.

inline void set_IRQ0_INTE_SM2_RXNEMPTY() volatile

Set IRQ0_INTE’s SM2_RXNEMPTY bit.

inline void clear_IRQ0_INTE_SM2_RXNEMPTY() volatile

Clear IRQ0_INTE’s SM2_RXNEMPTY bit.

inline void toggle_IRQ0_INTE_SM2_RXNEMPTY() volatile

Toggle IRQ0_INTE’s SM2_RXNEMPTY bit.

inline bool get_IRQ0_INTE_SM3_RXNEMPTY() volatile

Get IRQ0_INTE’s SM3_RXNEMPTY bit.

inline void set_IRQ0_INTE_SM3_RXNEMPTY() volatile

Set IRQ0_INTE’s SM3_RXNEMPTY bit.

inline void clear_IRQ0_INTE_SM3_RXNEMPTY() volatile

Clear IRQ0_INTE’s SM3_RXNEMPTY bit.

inline void toggle_IRQ0_INTE_SM3_RXNEMPTY() volatile

Toggle IRQ0_INTE’s SM3_RXNEMPTY bit.

inline bool get_IRQ0_INTE_SM0_TXNFULL() volatile

Get IRQ0_INTE’s SM0_TXNFULL bit.

inline void set_IRQ0_INTE_SM0_TXNFULL() volatile

Set IRQ0_INTE’s SM0_TXNFULL bit.

inline void clear_IRQ0_INTE_SM0_TXNFULL() volatile

Clear IRQ0_INTE’s SM0_TXNFULL bit.

inline void toggle_IRQ0_INTE_SM0_TXNFULL() volatile

Toggle IRQ0_INTE’s SM0_TXNFULL bit.

inline bool get_IRQ0_INTE_SM1_TXNFULL() volatile

Get IRQ0_INTE’s SM1_TXNFULL bit.

inline void set_IRQ0_INTE_SM1_TXNFULL() volatile

Set IRQ0_INTE’s SM1_TXNFULL bit.

inline void clear_IRQ0_INTE_SM1_TXNFULL() volatile

Clear IRQ0_INTE’s SM1_TXNFULL bit.

inline void toggle_IRQ0_INTE_SM1_TXNFULL() volatile

Toggle IRQ0_INTE’s SM1_TXNFULL bit.

inline bool get_IRQ0_INTE_SM2_TXNFULL() volatile

Get IRQ0_INTE’s SM2_TXNFULL bit.

inline void set_IRQ0_INTE_SM2_TXNFULL() volatile

Set IRQ0_INTE’s SM2_TXNFULL bit.

inline void clear_IRQ0_INTE_SM2_TXNFULL() volatile

Clear IRQ0_INTE’s SM2_TXNFULL bit.

inline void toggle_IRQ0_INTE_SM2_TXNFULL() volatile

Toggle IRQ0_INTE’s SM2_TXNFULL bit.

inline bool get_IRQ0_INTE_SM3_TXNFULL() volatile

Get IRQ0_INTE’s SM3_TXNFULL bit.

inline void set_IRQ0_INTE_SM3_TXNFULL() volatile

Set IRQ0_INTE’s SM3_TXNFULL bit.

inline void clear_IRQ0_INTE_SM3_TXNFULL() volatile

Clear IRQ0_INTE’s SM3_TXNFULL bit.

inline void toggle_IRQ0_INTE_SM3_TXNFULL() volatile

Toggle IRQ0_INTE’s SM3_TXNFULL bit.

inline bool get_IRQ0_INTE_SM0() volatile

Get IRQ0_INTE’s SM0 bit.

inline void set_IRQ0_INTE_SM0() volatile

Set IRQ0_INTE’s SM0 bit.

inline void clear_IRQ0_INTE_SM0() volatile

Clear IRQ0_INTE’s SM0 bit.

inline void toggle_IRQ0_INTE_SM0() volatile

Toggle IRQ0_INTE’s SM0 bit.

inline bool get_IRQ0_INTE_SM1() volatile

Get IRQ0_INTE’s SM1 bit.

inline void set_IRQ0_INTE_SM1() volatile

Set IRQ0_INTE’s SM1 bit.

inline void clear_IRQ0_INTE_SM1() volatile

Clear IRQ0_INTE’s SM1 bit.

inline void toggle_IRQ0_INTE_SM1() volatile

Toggle IRQ0_INTE’s SM1 bit.

inline bool get_IRQ0_INTE_SM2() volatile

Get IRQ0_INTE’s SM2 bit.

inline void set_IRQ0_INTE_SM2() volatile

Set IRQ0_INTE’s SM2 bit.

inline void clear_IRQ0_INTE_SM2() volatile

Clear IRQ0_INTE’s SM2 bit.

inline void toggle_IRQ0_INTE_SM2() volatile

Toggle IRQ0_INTE’s SM2 bit.

inline bool get_IRQ0_INTE_SM3() volatile

Get IRQ0_INTE’s SM3 bit.

inline void set_IRQ0_INTE_SM3() volatile

Set IRQ0_INTE’s SM3 bit.

inline void clear_IRQ0_INTE_SM3() volatile

Clear IRQ0_INTE’s SM3 bit.

inline void toggle_IRQ0_INTE_SM3() volatile

Toggle IRQ0_INTE’s SM3 bit.

inline void get_IRQ0_INTE(bool &SM0_RXNEMPTY, bool &SM1_RXNEMPTY, bool &SM2_RXNEMPTY, bool &SM3_RXNEMPTY, bool &SM0_TXNFULL, bool &SM1_TXNFULL, bool &SM2_TXNFULL, bool &SM3_TXNFULL, bool &SM0, bool &SM1, bool &SM2, bool &SM3) volatile

Get all of IRQ0_INTE’s bit fields.

(read-write) Interrupt Enable for irq0

inline void set_IRQ0_INTE(bool SM0_RXNEMPTY, bool SM1_RXNEMPTY, bool SM2_RXNEMPTY, bool SM3_RXNEMPTY, bool SM0_TXNFULL, bool SM1_TXNFULL, bool SM2_TXNFULL, bool SM3_TXNFULL, bool SM0, bool SM1, bool SM2, bool SM3) volatile

Set all of IRQ0_INTE’s bit fields.

(read-write) Interrupt Enable for irq0

inline bool get_IRQ0_INTF_SM0_RXNEMPTY() volatile

Get IRQ0_INTF’s SM0_RXNEMPTY bit.

inline void set_IRQ0_INTF_SM0_RXNEMPTY() volatile

Set IRQ0_INTF’s SM0_RXNEMPTY bit.

inline void clear_IRQ0_INTF_SM0_RXNEMPTY() volatile

Clear IRQ0_INTF’s SM0_RXNEMPTY bit.

inline void toggle_IRQ0_INTF_SM0_RXNEMPTY() volatile

Toggle IRQ0_INTF’s SM0_RXNEMPTY bit.

inline bool get_IRQ0_INTF_SM1_RXNEMPTY() volatile

Get IRQ0_INTF’s SM1_RXNEMPTY bit.

inline void set_IRQ0_INTF_SM1_RXNEMPTY() volatile

Set IRQ0_INTF’s SM1_RXNEMPTY bit.

inline void clear_IRQ0_INTF_SM1_RXNEMPTY() volatile

Clear IRQ0_INTF’s SM1_RXNEMPTY bit.

inline void toggle_IRQ0_INTF_SM1_RXNEMPTY() volatile

Toggle IRQ0_INTF’s SM1_RXNEMPTY bit.

inline bool get_IRQ0_INTF_SM2_RXNEMPTY() volatile

Get IRQ0_INTF’s SM2_RXNEMPTY bit.

inline void set_IRQ0_INTF_SM2_RXNEMPTY() volatile

Set IRQ0_INTF’s SM2_RXNEMPTY bit.

inline void clear_IRQ0_INTF_SM2_RXNEMPTY() volatile

Clear IRQ0_INTF’s SM2_RXNEMPTY bit.

inline void toggle_IRQ0_INTF_SM2_RXNEMPTY() volatile

Toggle IRQ0_INTF’s SM2_RXNEMPTY bit.

inline bool get_IRQ0_INTF_SM3_RXNEMPTY() volatile

Get IRQ0_INTF’s SM3_RXNEMPTY bit.

inline void set_IRQ0_INTF_SM3_RXNEMPTY() volatile

Set IRQ0_INTF’s SM3_RXNEMPTY bit.

inline void clear_IRQ0_INTF_SM3_RXNEMPTY() volatile

Clear IRQ0_INTF’s SM3_RXNEMPTY bit.

inline void toggle_IRQ0_INTF_SM3_RXNEMPTY() volatile

Toggle IRQ0_INTF’s SM3_RXNEMPTY bit.

inline bool get_IRQ0_INTF_SM0_TXNFULL() volatile

Get IRQ0_INTF’s SM0_TXNFULL bit.

inline void set_IRQ0_INTF_SM0_TXNFULL() volatile

Set IRQ0_INTF’s SM0_TXNFULL bit.

inline void clear_IRQ0_INTF_SM0_TXNFULL() volatile

Clear IRQ0_INTF’s SM0_TXNFULL bit.

inline void toggle_IRQ0_INTF_SM0_TXNFULL() volatile

Toggle IRQ0_INTF’s SM0_TXNFULL bit.

inline bool get_IRQ0_INTF_SM1_TXNFULL() volatile

Get IRQ0_INTF’s SM1_TXNFULL bit.

inline void set_IRQ0_INTF_SM1_TXNFULL() volatile

Set IRQ0_INTF’s SM1_TXNFULL bit.

inline void clear_IRQ0_INTF_SM1_TXNFULL() volatile

Clear IRQ0_INTF’s SM1_TXNFULL bit.

inline void toggle_IRQ0_INTF_SM1_TXNFULL() volatile

Toggle IRQ0_INTF’s SM1_TXNFULL bit.

inline bool get_IRQ0_INTF_SM2_TXNFULL() volatile

Get IRQ0_INTF’s SM2_TXNFULL bit.

inline void set_IRQ0_INTF_SM2_TXNFULL() volatile

Set IRQ0_INTF’s SM2_TXNFULL bit.

inline void clear_IRQ0_INTF_SM2_TXNFULL() volatile

Clear IRQ0_INTF’s SM2_TXNFULL bit.

inline void toggle_IRQ0_INTF_SM2_TXNFULL() volatile

Toggle IRQ0_INTF’s SM2_TXNFULL bit.

inline bool get_IRQ0_INTF_SM3_TXNFULL() volatile

Get IRQ0_INTF’s SM3_TXNFULL bit.

inline void set_IRQ0_INTF_SM3_TXNFULL() volatile

Set IRQ0_INTF’s SM3_TXNFULL bit.

inline void clear_IRQ0_INTF_SM3_TXNFULL() volatile

Clear IRQ0_INTF’s SM3_TXNFULL bit.

inline void toggle_IRQ0_INTF_SM3_TXNFULL() volatile

Toggle IRQ0_INTF’s SM3_TXNFULL bit.

inline bool get_IRQ0_INTF_SM0() volatile

Get IRQ0_INTF’s SM0 bit.

inline void set_IRQ0_INTF_SM0() volatile

Set IRQ0_INTF’s SM0 bit.

inline void clear_IRQ0_INTF_SM0() volatile

Clear IRQ0_INTF’s SM0 bit.

inline void toggle_IRQ0_INTF_SM0() volatile

Toggle IRQ0_INTF’s SM0 bit.

inline bool get_IRQ0_INTF_SM1() volatile

Get IRQ0_INTF’s SM1 bit.

inline void set_IRQ0_INTF_SM1() volatile

Set IRQ0_INTF’s SM1 bit.

inline void clear_IRQ0_INTF_SM1() volatile

Clear IRQ0_INTF’s SM1 bit.

inline void toggle_IRQ0_INTF_SM1() volatile

Toggle IRQ0_INTF’s SM1 bit.

inline bool get_IRQ0_INTF_SM2() volatile

Get IRQ0_INTF’s SM2 bit.

inline void set_IRQ0_INTF_SM2() volatile

Set IRQ0_INTF’s SM2 bit.

inline void clear_IRQ0_INTF_SM2() volatile

Clear IRQ0_INTF’s SM2 bit.

inline void toggle_IRQ0_INTF_SM2() volatile

Toggle IRQ0_INTF’s SM2 bit.

inline bool get_IRQ0_INTF_SM3() volatile

Get IRQ0_INTF’s SM3 bit.

inline void set_IRQ0_INTF_SM3() volatile

Set IRQ0_INTF’s SM3 bit.

inline void clear_IRQ0_INTF_SM3() volatile

Clear IRQ0_INTF’s SM3 bit.

inline void toggle_IRQ0_INTF_SM3() volatile

Toggle IRQ0_INTF’s SM3 bit.

inline void get_IRQ0_INTF(bool &SM0_RXNEMPTY, bool &SM1_RXNEMPTY, bool &SM2_RXNEMPTY, bool &SM3_RXNEMPTY, bool &SM0_TXNFULL, bool &SM1_TXNFULL, bool &SM2_TXNFULL, bool &SM3_TXNFULL, bool &SM0, bool &SM1, bool &SM2, bool &SM3) volatile

Get all of IRQ0_INTF’s bit fields.

(read-write) Interrupt Force for irq0

inline void set_IRQ0_INTF(bool SM0_RXNEMPTY, bool SM1_RXNEMPTY, bool SM2_RXNEMPTY, bool SM3_RXNEMPTY, bool SM0_TXNFULL, bool SM1_TXNFULL, bool SM2_TXNFULL, bool SM3_TXNFULL, bool SM0, bool SM1, bool SM2, bool SM3) volatile

Set all of IRQ0_INTF’s bit fields.

(read-write) Interrupt Force for irq0

inline bool get_IRQ0_INTS_SM0_RXNEMPTY() volatile

Get IRQ0_INTS’s SM0_RXNEMPTY bit.

inline bool get_IRQ0_INTS_SM1_RXNEMPTY() volatile

Get IRQ0_INTS’s SM1_RXNEMPTY bit.

inline bool get_IRQ0_INTS_SM2_RXNEMPTY() volatile

Get IRQ0_INTS’s SM2_RXNEMPTY bit.

inline bool get_IRQ0_INTS_SM3_RXNEMPTY() volatile

Get IRQ0_INTS’s SM3_RXNEMPTY bit.

inline bool get_IRQ0_INTS_SM0_TXNFULL() volatile

Get IRQ0_INTS’s SM0_TXNFULL bit.

inline bool get_IRQ0_INTS_SM1_TXNFULL() volatile

Get IRQ0_INTS’s SM1_TXNFULL bit.

inline bool get_IRQ0_INTS_SM2_TXNFULL() volatile

Get IRQ0_INTS’s SM2_TXNFULL bit.

inline bool get_IRQ0_INTS_SM3_TXNFULL() volatile

Get IRQ0_INTS’s SM3_TXNFULL bit.

inline bool get_IRQ0_INTS_SM0() volatile

Get IRQ0_INTS’s SM0 bit.

inline bool get_IRQ0_INTS_SM1() volatile

Get IRQ0_INTS’s SM1 bit.

inline bool get_IRQ0_INTS_SM2() volatile

Get IRQ0_INTS’s SM2 bit.

inline bool get_IRQ0_INTS_SM3() volatile

Get IRQ0_INTS’s SM3 bit.

inline void get_IRQ0_INTS(bool &SM0_RXNEMPTY, bool &SM1_RXNEMPTY, bool &SM2_RXNEMPTY, bool &SM3_RXNEMPTY, bool &SM0_TXNFULL, bool &SM1_TXNFULL, bool &SM2_TXNFULL, bool &SM3_TXNFULL, bool &SM0, bool &SM1, bool &SM2, bool &SM3) volatile

Get all of IRQ0_INTS’s bit fields.

(read-only) Interrupt status after masking & forcing for irq0

inline bool get_IRQ1_INTE_SM0_RXNEMPTY() volatile

Get IRQ1_INTE’s SM0_RXNEMPTY bit.

inline void set_IRQ1_INTE_SM0_RXNEMPTY() volatile

Set IRQ1_INTE’s SM0_RXNEMPTY bit.

inline void clear_IRQ1_INTE_SM0_RXNEMPTY() volatile

Clear IRQ1_INTE’s SM0_RXNEMPTY bit.

inline void toggle_IRQ1_INTE_SM0_RXNEMPTY() volatile

Toggle IRQ1_INTE’s SM0_RXNEMPTY bit.

inline bool get_IRQ1_INTE_SM1_RXNEMPTY() volatile

Get IRQ1_INTE’s SM1_RXNEMPTY bit.

inline void set_IRQ1_INTE_SM1_RXNEMPTY() volatile

Set IRQ1_INTE’s SM1_RXNEMPTY bit.

inline void clear_IRQ1_INTE_SM1_RXNEMPTY() volatile

Clear IRQ1_INTE’s SM1_RXNEMPTY bit.

inline void toggle_IRQ1_INTE_SM1_RXNEMPTY() volatile

Toggle IRQ1_INTE’s SM1_RXNEMPTY bit.

inline bool get_IRQ1_INTE_SM2_RXNEMPTY() volatile

Get IRQ1_INTE’s SM2_RXNEMPTY bit.

inline void set_IRQ1_INTE_SM2_RXNEMPTY() volatile

Set IRQ1_INTE’s SM2_RXNEMPTY bit.

inline void clear_IRQ1_INTE_SM2_RXNEMPTY() volatile

Clear IRQ1_INTE’s SM2_RXNEMPTY bit.

inline void toggle_IRQ1_INTE_SM2_RXNEMPTY() volatile

Toggle IRQ1_INTE’s SM2_RXNEMPTY bit.

inline bool get_IRQ1_INTE_SM3_RXNEMPTY() volatile

Get IRQ1_INTE’s SM3_RXNEMPTY bit.

inline void set_IRQ1_INTE_SM3_RXNEMPTY() volatile

Set IRQ1_INTE’s SM3_RXNEMPTY bit.

inline void clear_IRQ1_INTE_SM3_RXNEMPTY() volatile

Clear IRQ1_INTE’s SM3_RXNEMPTY bit.

inline void toggle_IRQ1_INTE_SM3_RXNEMPTY() volatile

Toggle IRQ1_INTE’s SM3_RXNEMPTY bit.

inline bool get_IRQ1_INTE_SM0_TXNFULL() volatile

Get IRQ1_INTE’s SM0_TXNFULL bit.

inline void set_IRQ1_INTE_SM0_TXNFULL() volatile

Set IRQ1_INTE’s SM0_TXNFULL bit.

inline void clear_IRQ1_INTE_SM0_TXNFULL() volatile

Clear IRQ1_INTE’s SM0_TXNFULL bit.

inline void toggle_IRQ1_INTE_SM0_TXNFULL() volatile

Toggle IRQ1_INTE’s SM0_TXNFULL bit.

inline bool get_IRQ1_INTE_SM1_TXNFULL() volatile

Get IRQ1_INTE’s SM1_TXNFULL bit.

inline void set_IRQ1_INTE_SM1_TXNFULL() volatile

Set IRQ1_INTE’s SM1_TXNFULL bit.

inline void clear_IRQ1_INTE_SM1_TXNFULL() volatile

Clear IRQ1_INTE’s SM1_TXNFULL bit.

inline void toggle_IRQ1_INTE_SM1_TXNFULL() volatile

Toggle IRQ1_INTE’s SM1_TXNFULL bit.

inline bool get_IRQ1_INTE_SM2_TXNFULL() volatile

Get IRQ1_INTE’s SM2_TXNFULL bit.

inline void set_IRQ1_INTE_SM2_TXNFULL() volatile

Set IRQ1_INTE’s SM2_TXNFULL bit.

inline void clear_IRQ1_INTE_SM2_TXNFULL() volatile

Clear IRQ1_INTE’s SM2_TXNFULL bit.

inline void toggle_IRQ1_INTE_SM2_TXNFULL() volatile

Toggle IRQ1_INTE’s SM2_TXNFULL bit.

inline bool get_IRQ1_INTE_SM3_TXNFULL() volatile

Get IRQ1_INTE’s SM3_TXNFULL bit.

inline void set_IRQ1_INTE_SM3_TXNFULL() volatile

Set IRQ1_INTE’s SM3_TXNFULL bit.

inline void clear_IRQ1_INTE_SM3_TXNFULL() volatile

Clear IRQ1_INTE’s SM3_TXNFULL bit.

inline void toggle_IRQ1_INTE_SM3_TXNFULL() volatile

Toggle IRQ1_INTE’s SM3_TXNFULL bit.

inline bool get_IRQ1_INTE_SM0() volatile

Get IRQ1_INTE’s SM0 bit.

inline void set_IRQ1_INTE_SM0() volatile

Set IRQ1_INTE’s SM0 bit.

inline void clear_IRQ1_INTE_SM0() volatile

Clear IRQ1_INTE’s SM0 bit.

inline void toggle_IRQ1_INTE_SM0() volatile

Toggle IRQ1_INTE’s SM0 bit.

inline bool get_IRQ1_INTE_SM1() volatile

Get IRQ1_INTE’s SM1 bit.

inline void set_IRQ1_INTE_SM1() volatile

Set IRQ1_INTE’s SM1 bit.

inline void clear_IRQ1_INTE_SM1() volatile

Clear IRQ1_INTE’s SM1 bit.

inline void toggle_IRQ1_INTE_SM1() volatile

Toggle IRQ1_INTE’s SM1 bit.

inline bool get_IRQ1_INTE_SM2() volatile

Get IRQ1_INTE’s SM2 bit.

inline void set_IRQ1_INTE_SM2() volatile

Set IRQ1_INTE’s SM2 bit.

inline void clear_IRQ1_INTE_SM2() volatile

Clear IRQ1_INTE’s SM2 bit.

inline void toggle_IRQ1_INTE_SM2() volatile

Toggle IRQ1_INTE’s SM2 bit.

inline bool get_IRQ1_INTE_SM3() volatile

Get IRQ1_INTE’s SM3 bit.

inline void set_IRQ1_INTE_SM3() volatile

Set IRQ1_INTE’s SM3 bit.

inline void clear_IRQ1_INTE_SM3() volatile

Clear IRQ1_INTE’s SM3 bit.

inline void toggle_IRQ1_INTE_SM3() volatile

Toggle IRQ1_INTE’s SM3 bit.

inline void get_IRQ1_INTE(bool &SM0_RXNEMPTY, bool &SM1_RXNEMPTY, bool &SM2_RXNEMPTY, bool &SM3_RXNEMPTY, bool &SM0_TXNFULL, bool &SM1_TXNFULL, bool &SM2_TXNFULL, bool &SM3_TXNFULL, bool &SM0, bool &SM1, bool &SM2, bool &SM3) volatile

Get all of IRQ1_INTE’s bit fields.

(read-write) Interrupt Enable for irq1

inline void set_IRQ1_INTE(bool SM0_RXNEMPTY, bool SM1_RXNEMPTY, bool SM2_RXNEMPTY, bool SM3_RXNEMPTY, bool SM0_TXNFULL, bool SM1_TXNFULL, bool SM2_TXNFULL, bool SM3_TXNFULL, bool SM0, bool SM1, bool SM2, bool SM3) volatile

Set all of IRQ1_INTE’s bit fields.

(read-write) Interrupt Enable for irq1

inline bool get_IRQ1_INTF_SM0_RXNEMPTY() volatile

Get IRQ1_INTF’s SM0_RXNEMPTY bit.

inline void set_IRQ1_INTF_SM0_RXNEMPTY() volatile

Set IRQ1_INTF’s SM0_RXNEMPTY bit.

inline void clear_IRQ1_INTF_SM0_RXNEMPTY() volatile

Clear IRQ1_INTF’s SM0_RXNEMPTY bit.

inline void toggle_IRQ1_INTF_SM0_RXNEMPTY() volatile

Toggle IRQ1_INTF’s SM0_RXNEMPTY bit.

inline bool get_IRQ1_INTF_SM1_RXNEMPTY() volatile

Get IRQ1_INTF’s SM1_RXNEMPTY bit.

inline void set_IRQ1_INTF_SM1_RXNEMPTY() volatile

Set IRQ1_INTF’s SM1_RXNEMPTY bit.

inline void clear_IRQ1_INTF_SM1_RXNEMPTY() volatile

Clear IRQ1_INTF’s SM1_RXNEMPTY bit.

inline void toggle_IRQ1_INTF_SM1_RXNEMPTY() volatile

Toggle IRQ1_INTF’s SM1_RXNEMPTY bit.

inline bool get_IRQ1_INTF_SM2_RXNEMPTY() volatile

Get IRQ1_INTF’s SM2_RXNEMPTY bit.

inline void set_IRQ1_INTF_SM2_RXNEMPTY() volatile

Set IRQ1_INTF’s SM2_RXNEMPTY bit.

inline void clear_IRQ1_INTF_SM2_RXNEMPTY() volatile

Clear IRQ1_INTF’s SM2_RXNEMPTY bit.

inline void toggle_IRQ1_INTF_SM2_RXNEMPTY() volatile

Toggle IRQ1_INTF’s SM2_RXNEMPTY bit.

inline bool get_IRQ1_INTF_SM3_RXNEMPTY() volatile

Get IRQ1_INTF’s SM3_RXNEMPTY bit.

inline void set_IRQ1_INTF_SM3_RXNEMPTY() volatile

Set IRQ1_INTF’s SM3_RXNEMPTY bit.

inline void clear_IRQ1_INTF_SM3_RXNEMPTY() volatile

Clear IRQ1_INTF’s SM3_RXNEMPTY bit.

inline void toggle_IRQ1_INTF_SM3_RXNEMPTY() volatile

Toggle IRQ1_INTF’s SM3_RXNEMPTY bit.

inline bool get_IRQ1_INTF_SM0_TXNFULL() volatile

Get IRQ1_INTF’s SM0_TXNFULL bit.

inline void set_IRQ1_INTF_SM0_TXNFULL() volatile

Set IRQ1_INTF’s SM0_TXNFULL bit.

inline void clear_IRQ1_INTF_SM0_TXNFULL() volatile

Clear IRQ1_INTF’s SM0_TXNFULL bit.

inline void toggle_IRQ1_INTF_SM0_TXNFULL() volatile

Toggle IRQ1_INTF’s SM0_TXNFULL bit.

inline bool get_IRQ1_INTF_SM1_TXNFULL() volatile

Get IRQ1_INTF’s SM1_TXNFULL bit.

inline void set_IRQ1_INTF_SM1_TXNFULL() volatile

Set IRQ1_INTF’s SM1_TXNFULL bit.

inline void clear_IRQ1_INTF_SM1_TXNFULL() volatile

Clear IRQ1_INTF’s SM1_TXNFULL bit.

inline void toggle_IRQ1_INTF_SM1_TXNFULL() volatile

Toggle IRQ1_INTF’s SM1_TXNFULL bit.

inline bool get_IRQ1_INTF_SM2_TXNFULL() volatile

Get IRQ1_INTF’s SM2_TXNFULL bit.

inline void set_IRQ1_INTF_SM2_TXNFULL() volatile

Set IRQ1_INTF’s SM2_TXNFULL bit.

inline void clear_IRQ1_INTF_SM2_TXNFULL() volatile

Clear IRQ1_INTF’s SM2_TXNFULL bit.

inline void toggle_IRQ1_INTF_SM2_TXNFULL() volatile

Toggle IRQ1_INTF’s SM2_TXNFULL bit.

inline bool get_IRQ1_INTF_SM3_TXNFULL() volatile

Get IRQ1_INTF’s SM3_TXNFULL bit.

inline void set_IRQ1_INTF_SM3_TXNFULL() volatile

Set IRQ1_INTF’s SM3_TXNFULL bit.

inline void clear_IRQ1_INTF_SM3_TXNFULL() volatile

Clear IRQ1_INTF’s SM3_TXNFULL bit.

inline void toggle_IRQ1_INTF_SM3_TXNFULL() volatile

Toggle IRQ1_INTF’s SM3_TXNFULL bit.

inline bool get_IRQ1_INTF_SM0() volatile

Get IRQ1_INTF’s SM0 bit.

inline void set_IRQ1_INTF_SM0() volatile

Set IRQ1_INTF’s SM0 bit.

inline void clear_IRQ1_INTF_SM0() volatile

Clear IRQ1_INTF’s SM0 bit.

inline void toggle_IRQ1_INTF_SM0() volatile

Toggle IRQ1_INTF’s SM0 bit.

inline bool get_IRQ1_INTF_SM1() volatile

Get IRQ1_INTF’s SM1 bit.

inline void set_IRQ1_INTF_SM1() volatile

Set IRQ1_INTF’s SM1 bit.

inline void clear_IRQ1_INTF_SM1() volatile

Clear IRQ1_INTF’s SM1 bit.

inline void toggle_IRQ1_INTF_SM1() volatile

Toggle IRQ1_INTF’s SM1 bit.

inline bool get_IRQ1_INTF_SM2() volatile

Get IRQ1_INTF’s SM2 bit.

inline void set_IRQ1_INTF_SM2() volatile

Set IRQ1_INTF’s SM2 bit.

inline void clear_IRQ1_INTF_SM2() volatile

Clear IRQ1_INTF’s SM2 bit.

inline void toggle_IRQ1_INTF_SM2() volatile

Toggle IRQ1_INTF’s SM2 bit.

inline bool get_IRQ1_INTF_SM3() volatile

Get IRQ1_INTF’s SM3 bit.

inline void set_IRQ1_INTF_SM3() volatile

Set IRQ1_INTF’s SM3 bit.

inline void clear_IRQ1_INTF_SM3() volatile

Clear IRQ1_INTF’s SM3 bit.

inline void toggle_IRQ1_INTF_SM3() volatile

Toggle IRQ1_INTF’s SM3 bit.

inline void get_IRQ1_INTF(bool &SM0_RXNEMPTY, bool &SM1_RXNEMPTY, bool &SM2_RXNEMPTY, bool &SM3_RXNEMPTY, bool &SM0_TXNFULL, bool &SM1_TXNFULL, bool &SM2_TXNFULL, bool &SM3_TXNFULL, bool &SM0, bool &SM1, bool &SM2, bool &SM3) volatile

Get all of IRQ1_INTF’s bit fields.

(read-write) Interrupt Force for irq1

inline void set_IRQ1_INTF(bool SM0_RXNEMPTY, bool SM1_RXNEMPTY, bool SM2_RXNEMPTY, bool SM3_RXNEMPTY, bool SM0_TXNFULL, bool SM1_TXNFULL, bool SM2_TXNFULL, bool SM3_TXNFULL, bool SM0, bool SM1, bool SM2, bool SM3) volatile

Set all of IRQ1_INTF’s bit fields.

(read-write) Interrupt Force for irq1

inline bool get_IRQ1_INTS_SM0_RXNEMPTY() volatile

Get IRQ1_INTS’s SM0_RXNEMPTY bit.

inline bool get_IRQ1_INTS_SM1_RXNEMPTY() volatile

Get IRQ1_INTS’s SM1_RXNEMPTY bit.

inline bool get_IRQ1_INTS_SM2_RXNEMPTY() volatile

Get IRQ1_INTS’s SM2_RXNEMPTY bit.

inline bool get_IRQ1_INTS_SM3_RXNEMPTY() volatile

Get IRQ1_INTS’s SM3_RXNEMPTY bit.

inline bool get_IRQ1_INTS_SM0_TXNFULL() volatile

Get IRQ1_INTS’s SM0_TXNFULL bit.

inline bool get_IRQ1_INTS_SM1_TXNFULL() volatile

Get IRQ1_INTS’s SM1_TXNFULL bit.

inline bool get_IRQ1_INTS_SM2_TXNFULL() volatile

Get IRQ1_INTS’s SM2_TXNFULL bit.

inline bool get_IRQ1_INTS_SM3_TXNFULL() volatile

Get IRQ1_INTS’s SM3_TXNFULL bit.

inline bool get_IRQ1_INTS_SM0() volatile

Get IRQ1_INTS’s SM0 bit.

inline bool get_IRQ1_INTS_SM1() volatile

Get IRQ1_INTS’s SM1 bit.

inline bool get_IRQ1_INTS_SM2() volatile

Get IRQ1_INTS’s SM2 bit.

inline bool get_IRQ1_INTS_SM3() volatile

Get IRQ1_INTS’s SM3 bit.

inline void get_IRQ1_INTS(bool &SM0_RXNEMPTY, bool &SM1_RXNEMPTY, bool &SM2_RXNEMPTY, bool &SM3_RXNEMPTY, bool &SM0_TXNFULL, bool &SM1_TXNFULL, bool &SM2_TXNFULL, bool &SM3_TXNFULL, bool &SM0, bool &SM1, bool &SM2, bool &SM3) volatile

Get all of IRQ1_INTS’s bit fields.

(read-only) Interrupt status after masking & forcing for irq1

Public Members

uint32_t CTRL

(read-write) PIO control register

const uint32_t FSTAT = {}

(read-only) FIFO status register

uint32_t FDEBUG

(read-write) FIFO debug register

const uint32_t FLEVEL = {}

(read-only) FIFO levels

uint32_t TXF0

(read-write) Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.

uint32_t TXF1

(read-write) Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.

uint32_t TXF2

(read-write) Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.

uint32_t TXF3

(read-write) Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.

uint32_t RXF0

(read-write) Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.

uint32_t RXF1

(read-write) Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.

uint32_t RXF2

(read-write) Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.

uint32_t RXF3

(read-write) Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.

uint32_t IRQ

(read-write) State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There’s no fixed association between flags and state machines &#8212; any state machine can use any flag.

Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts

&#8212; see e.g. IRQ0_INTE.

uint32_t IRQ_FORCE

(write-only) Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.

uint32_t INPUT_SYNC_BYPASS

(read-write) There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.

0 -> input is synchronized (default)

1 -> synchronizer is bypassed

If in doubt, leave this register as all zeroes.

uint32_t DBG_PADOUT

(read-write) Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.

uint32_t DBG_PADOE

(read-write) Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.

const uint32_t DBG_CFGINFO = {}

(read-only) The PIO hardware has some free parameters that may vary between chip products.

These should be provided in the chip datasheet, but are also exposed here.

uint32_t INSTR_MEM0

(write-only) Write-only access to instruction memory location 0

uint32_t INSTR_MEM1

(write-only) Write-only access to instruction memory location 1

uint32_t INSTR_MEM2

(write-only) Write-only access to instruction memory location 2

uint32_t INSTR_MEM3

(write-only) Write-only access to instruction memory location 3

uint32_t INSTR_MEM4

(write-only) Write-only access to instruction memory location 4

uint32_t INSTR_MEM5

(write-only) Write-only access to instruction memory location 5

uint32_t INSTR_MEM6

(write-only) Write-only access to instruction memory location 6

uint32_t INSTR_MEM7

(write-only) Write-only access to instruction memory location 7

uint32_t INSTR_MEM8

(write-only) Write-only access to instruction memory location 8

uint32_t INSTR_MEM9

(write-only) Write-only access to instruction memory location 9

uint32_t INSTR_MEM10

(write-only) Write-only access to instruction memory location 10

uint32_t INSTR_MEM11

(write-only) Write-only access to instruction memory location 11

uint32_t INSTR_MEM12

(write-only) Write-only access to instruction memory location 12

uint32_t INSTR_MEM13

(write-only) Write-only access to instruction memory location 13

uint32_t INSTR_MEM14

(write-only) Write-only access to instruction memory location 14

uint32_t INSTR_MEM15

(write-only) Write-only access to instruction memory location 15

uint32_t INSTR_MEM16

(write-only) Write-only access to instruction memory location 16

uint32_t INSTR_MEM17

(write-only) Write-only access to instruction memory location 17

uint32_t INSTR_MEM18

(write-only) Write-only access to instruction memory location 18

uint32_t INSTR_MEM19

(write-only) Write-only access to instruction memory location 19

uint32_t INSTR_MEM20

(write-only) Write-only access to instruction memory location 20

uint32_t INSTR_MEM21

(write-only) Write-only access to instruction memory location 21

uint32_t INSTR_MEM22

(write-only) Write-only access to instruction memory location 22

uint32_t INSTR_MEM23

(write-only) Write-only access to instruction memory location 23

uint32_t INSTR_MEM24

(write-only) Write-only access to instruction memory location 24

uint32_t INSTR_MEM25

(write-only) Write-only access to instruction memory location 25

uint32_t INSTR_MEM26

(write-only) Write-only access to instruction memory location 26

uint32_t INSTR_MEM27

(write-only) Write-only access to instruction memory location 27

uint32_t INSTR_MEM28

(write-only) Write-only access to instruction memory location 28

uint32_t INSTR_MEM29

(write-only) Write-only access to instruction memory location 29

uint32_t INSTR_MEM30

(write-only) Write-only access to instruction memory location 30

uint32_t INSTR_MEM31

(write-only) Write-only access to instruction memory location 31

uint32_t SM0_CLKDIV

(read-write) Clock divisor register for state machine 0

Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

uint32_t SM0_EXECCTRL

(read-write) Execution/behavioural settings for state machine 0

uint32_t SM0_SHIFTCTRL

(read-write) Control behaviour of the input/output shift registers for state machine 0

const uint32_t SM0_ADDR = {}

(read-only) Current instruction address of state machine 0

uint32_t SM0_INSTR

(read-write) Read to see the instruction currently addressed by state machine 0’s program counter

Write to execute an instruction immediately (including jumps) and then resume execution.

uint32_t SM0_PINCTRL

(read-write) State machine pin control

uint32_t SM1_CLKDIV

(read-write) Clock divisor register for state machine 1

Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

uint32_t SM1_EXECCTRL

(read-write) Execution/behavioural settings for state machine 1

uint32_t SM1_SHIFTCTRL

(read-write) Control behaviour of the input/output shift registers for state machine 1

const uint32_t SM1_ADDR = {}

(read-only) Current instruction address of state machine 1

uint32_t SM1_INSTR

(read-write) Read to see the instruction currently addressed by state machine 1’s program counter

Write to execute an instruction immediately (including jumps) and then resume execution.

uint32_t SM1_PINCTRL

(read-write) State machine pin control

uint32_t SM2_CLKDIV

(read-write) Clock divisor register for state machine 2

Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

uint32_t SM2_EXECCTRL

(read-write) Execution/behavioural settings for state machine 2

uint32_t SM2_SHIFTCTRL

(read-write) Control behaviour of the input/output shift registers for state machine 2

const uint32_t SM2_ADDR = {}

(read-only) Current instruction address of state machine 2

uint32_t SM2_INSTR

(read-write) Read to see the instruction currently addressed by state machine 2’s program counter

Write to execute an instruction immediately (including jumps) and then resume execution.

uint32_t SM2_PINCTRL

(read-write) State machine pin control

uint32_t SM3_CLKDIV

(read-write) Clock divisor register for state machine 3

Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

uint32_t SM3_EXECCTRL

(read-write) Execution/behavioural settings for state machine 3

uint32_t SM3_SHIFTCTRL

(read-write) Control behaviour of the input/output shift registers for state machine 3

const uint32_t SM3_ADDR = {}

(read-only) Current instruction address of state machine 3

uint32_t SM3_INSTR

(read-write) Read to see the instruction currently addressed by state machine 3’s program counter

Write to execute an instruction immediately (including jumps) and then resume execution.

uint32_t SM3_PINCTRL

(read-write) State machine pin control

const uint32_t INTR = {}

(read-only) Raw Interrupts

uint32_t IRQ0_INTE

(read-write) Interrupt Enable for irq0

uint32_t IRQ0_INTF

(read-write) Interrupt Force for irq0

const uint32_t IRQ0_INTS = {}

(read-only) Interrupt status after masking & forcing for irq0

uint32_t IRQ1_INTE

(read-write) Interrupt Enable for irq1

uint32_t IRQ1_INTF

(read-write) Interrupt Force for irq1

const uint32_t IRQ1_INTS = {}

(read-only) Interrupt status after masking & forcing for irq1

Public Static Attributes

static constexpr std::size_t size = 324

pio0’s size in bytes.