Struct dma

• Defined in File dma.h

Struct Documentation

struct dma

DMA with separate read and write masters

Public Functions

inline bool get_CH0_CTRL_TRIG_EN() volatile

Get CH0_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_CH0_CTRL_TRIG_EN() volatile

Set CH0_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_CH0_CTRL_TRIG_EN() volatile

Clear CH0_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_CH0_CTRL_TRIG_EN() volatile

Toggle CH0_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_CH0_CTRL_TRIG_HIGH_PRIORITY() volatile

Get CH0_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_CH0_CTRL_TRIG_HIGH_PRIORITY() volatile

Set CH0_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_CH0_CTRL_TRIG_HIGH_PRIORITY() volatile

Clear CH0_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_CH0_CTRL_TRIG_HIGH_PRIORITY() volatile

Toggle CH0_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_CH0_CTRL_TRIG_DATA_SIZE get_CH0_CTRL_TRIG_DATA_SIZE() volatile

Get CH0_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_CH0_CTRL_TRIG_DATA_SIZE(DMA_CH0_CTRL_TRIG_DATA_SIZE value) volatile

Set CH0_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_CH0_CTRL_TRIG_INCR_READ() volatile

Get CH0_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void set_CH0_CTRL_TRIG_INCR_READ() volatile

Set CH0_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_CH0_CTRL_TRIG_INCR_READ() volatile

Clear CH0_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_CH0_CTRL_TRIG_INCR_READ() volatile

Toggle CH0_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_CH0_CTRL_TRIG_INCR_WRITE() volatile

Get CH0_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void set_CH0_CTRL_TRIG_INCR_WRITE() volatile

Set CH0_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_CH0_CTRL_TRIG_INCR_WRITE() volatile

Clear CH0_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_CH0_CTRL_TRIG_INCR_WRITE() volatile

Toggle CH0_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_CH0_CTRL_TRIG_RING_SIZE get_CH0_CTRL_TRIG_RING_SIZE() volatile

Get CH0_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_CH0_CTRL_TRIG_RING_SIZE(DMA_CH0_CTRL_TRIG_RING_SIZE value) volatile

Set CH0_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_CH0_CTRL_TRIG_RING_SEL() volatile

Get CH0_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_CH0_CTRL_TRIG_RING_SEL() volatile

Set CH0_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_CH0_CTRL_TRIG_RING_SEL() volatile

Clear CH0_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_CH0_CTRL_TRIG_RING_SEL() volatile

Toggle CH0_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_CH0_CTRL_TRIG_CHAIN_TO() volatile

Get CH0_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_CH0_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile

Set CH0_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_CH0_CTRL_TRIG_TREQ_SEL get_CH0_CTRL_TRIG_TREQ_SEL() volatile

Get CH0_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline void set_CH0_CTRL_TRIG_TREQ_SEL(DMA_CH0_CTRL_TRIG_TREQ_SEL value) volatile

Set CH0_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_CH0_CTRL_TRIG_IRQ_QUIET() volatile

Get CH0_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_CH0_CTRL_TRIG_IRQ_QUIET() volatile

Set CH0_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_CH0_CTRL_TRIG_IRQ_QUIET() volatile

Clear CH0_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_CH0_CTRL_TRIG_IRQ_QUIET() volatile

Toggle CH0_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_CH0_CTRL_TRIG_BSWAP() volatile

Get CH0_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_CH0_CTRL_TRIG_BSWAP() volatile

Set CH0_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_CH0_CTRL_TRIG_BSWAP() volatile

Clear CH0_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_CH0_CTRL_TRIG_BSWAP() volatile

Toggle CH0_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_CH0_CTRL_TRIG_SNIFF_EN() volatile

Get CH0_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_CH0_CTRL_TRIG_SNIFF_EN() volatile

Set CH0_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_CH0_CTRL_TRIG_SNIFF_EN() volatile

Clear CH0_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_CH0_CTRL_TRIG_SNIFF_EN() volatile

Toggle CH0_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_CH0_CTRL_TRIG_BUSY() volatile

Get CH0_CTRL_TRIG’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.

To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_CH0_CTRL_TRIG_WRITE_ERROR() volatile

Get CH0_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_CH0_CTRL_TRIG_WRITE_ERROR() volatile

Set CH0_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_CH0_CTRL_TRIG_WRITE_ERROR() volatile

Clear CH0_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_CH0_CTRL_TRIG_WRITE_ERROR() volatile

Toggle CH0_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_CH0_CTRL_TRIG_READ_ERROR() volatile

Get CH0_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_CH0_CTRL_TRIG_READ_ERROR() volatile

Set CH0_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_CH0_CTRL_TRIG_READ_ERROR() volatile

Clear CH0_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_CH0_CTRL_TRIG_READ_ERROR() volatile

Toggle CH0_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_CH0_CTRL_TRIG_AHB_ERROR() volatile

Get CH0_CTRL_TRIG’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_CH0_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY, DMA_CH0_CTRL_TRIG_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_CH0_CTRL_TRIG_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_CH0_CTRL_TRIG_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR) volatile

Get all of CH0_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 0 Control and Status

inline void set_CH0_CTRL_TRIG(bool EN, bool HIGH_PRIORITY, DMA_CH0_CTRL_TRIG_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_CH0_CTRL_TRIG_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_CH0_CTRL_TRIG_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR) volatile

Set all of CH0_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 0 Control and Status

inline bool get_CH1_CTRL_TRIG_EN() volatile

Get CH1_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_CH1_CTRL_TRIG_EN() volatile

Set CH1_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_CH1_CTRL_TRIG_EN() volatile

Clear CH1_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_CH1_CTRL_TRIG_EN() volatile

Toggle CH1_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_CH1_CTRL_TRIG_HIGH_PRIORITY() volatile

Get CH1_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_CH1_CTRL_TRIG_HIGH_PRIORITY() volatile

Set CH1_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_CH1_CTRL_TRIG_HIGH_PRIORITY() volatile

Clear CH1_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_CH1_CTRL_TRIG_HIGH_PRIORITY() volatile

Toggle CH1_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_CH1_CTRL_TRIG_DATA_SIZE get_CH1_CTRL_TRIG_DATA_SIZE() volatile

Get CH1_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_CH1_CTRL_TRIG_DATA_SIZE(DMA_CH1_CTRL_TRIG_DATA_SIZE value) volatile

Set CH1_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_CH1_CTRL_TRIG_INCR_READ() volatile

Get CH1_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void set_CH1_CTRL_TRIG_INCR_READ() volatile

Set CH1_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_CH1_CTRL_TRIG_INCR_READ() volatile

Clear CH1_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_CH1_CTRL_TRIG_INCR_READ() volatile

Toggle CH1_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_CH1_CTRL_TRIG_INCR_WRITE() volatile

Get CH1_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void set_CH1_CTRL_TRIG_INCR_WRITE() volatile

Set CH1_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_CH1_CTRL_TRIG_INCR_WRITE() volatile

Clear CH1_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_CH1_CTRL_TRIG_INCR_WRITE() volatile

Toggle CH1_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_CH1_CTRL_TRIG_RING_SIZE get_CH1_CTRL_TRIG_RING_SIZE() volatile

Get CH1_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_CH1_CTRL_TRIG_RING_SIZE(DMA_CH1_CTRL_TRIG_RING_SIZE value) volatile

Set CH1_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_CH1_CTRL_TRIG_RING_SEL() volatile

Get CH1_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_CH1_CTRL_TRIG_RING_SEL() volatile

Set CH1_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_CH1_CTRL_TRIG_RING_SEL() volatile

Clear CH1_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_CH1_CTRL_TRIG_RING_SEL() volatile

Toggle CH1_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_CH1_CTRL_TRIG_CHAIN_TO() volatile

Get CH1_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_CH1_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile

Set CH1_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_CH1_CTRL_TRIG_TREQ_SEL get_CH1_CTRL_TRIG_TREQ_SEL() volatile

Get CH1_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline void set_CH1_CTRL_TRIG_TREQ_SEL(DMA_CH1_CTRL_TRIG_TREQ_SEL value) volatile

Set CH1_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_CH1_CTRL_TRIG_IRQ_QUIET() volatile

Get CH1_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_CH1_CTRL_TRIG_IRQ_QUIET() volatile

Set CH1_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_CH1_CTRL_TRIG_IRQ_QUIET() volatile

Clear CH1_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_CH1_CTRL_TRIG_IRQ_QUIET() volatile

Toggle CH1_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_CH1_CTRL_TRIG_BSWAP() volatile

Get CH1_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_CH1_CTRL_TRIG_BSWAP() volatile

Set CH1_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_CH1_CTRL_TRIG_BSWAP() volatile

Clear CH1_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_CH1_CTRL_TRIG_BSWAP() volatile

Toggle CH1_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_CH1_CTRL_TRIG_SNIFF_EN() volatile

Get CH1_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_CH1_CTRL_TRIG_SNIFF_EN() volatile

Set CH1_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_CH1_CTRL_TRIG_SNIFF_EN() volatile

Clear CH1_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_CH1_CTRL_TRIG_SNIFF_EN() volatile

Toggle CH1_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_CH1_CTRL_TRIG_BUSY() volatile

Get CH1_CTRL_TRIG’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.

To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_CH1_CTRL_TRIG_WRITE_ERROR() volatile

Get CH1_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_CH1_CTRL_TRIG_WRITE_ERROR() volatile

Set CH1_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_CH1_CTRL_TRIG_WRITE_ERROR() volatile

Clear CH1_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_CH1_CTRL_TRIG_WRITE_ERROR() volatile

Toggle CH1_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_CH1_CTRL_TRIG_READ_ERROR() volatile

Get CH1_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_CH1_CTRL_TRIG_READ_ERROR() volatile

Set CH1_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_CH1_CTRL_TRIG_READ_ERROR() volatile

Clear CH1_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_CH1_CTRL_TRIG_READ_ERROR() volatile

Toggle CH1_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_CH1_CTRL_TRIG_AHB_ERROR() volatile

Get CH1_CTRL_TRIG’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_CH1_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY, DMA_CH1_CTRL_TRIG_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_CH1_CTRL_TRIG_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_CH1_CTRL_TRIG_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR) volatile

Get all of CH1_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 1 Control and Status

inline void set_CH1_CTRL_TRIG(bool EN, bool HIGH_PRIORITY, DMA_CH1_CTRL_TRIG_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_CH1_CTRL_TRIG_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_CH1_CTRL_TRIG_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR) volatile

Set all of CH1_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 1 Control and Status

inline bool get_CH2_CTRL_TRIG_EN() volatile

Get CH2_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_CH2_CTRL_TRIG_EN() volatile

Set CH2_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_CH2_CTRL_TRIG_EN() volatile

Clear CH2_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_CH2_CTRL_TRIG_EN() volatile

Toggle CH2_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_CH2_CTRL_TRIG_HIGH_PRIORITY() volatile

Get CH2_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_CH2_CTRL_TRIG_HIGH_PRIORITY() volatile

Set CH2_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_CH2_CTRL_TRIG_HIGH_PRIORITY() volatile

Clear CH2_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_CH2_CTRL_TRIG_HIGH_PRIORITY() volatile

Toggle CH2_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_CH2_CTRL_TRIG_DATA_SIZE get_CH2_CTRL_TRIG_DATA_SIZE() volatile

Get CH2_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_CH2_CTRL_TRIG_DATA_SIZE(DMA_CH2_CTRL_TRIG_DATA_SIZE value) volatile

Set CH2_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_CH2_CTRL_TRIG_INCR_READ() volatile

Get CH2_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void set_CH2_CTRL_TRIG_INCR_READ() volatile

Set CH2_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_CH2_CTRL_TRIG_INCR_READ() volatile

Clear CH2_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_CH2_CTRL_TRIG_INCR_READ() volatile

Toggle CH2_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_CH2_CTRL_TRIG_INCR_WRITE() volatile

Get CH2_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void set_CH2_CTRL_TRIG_INCR_WRITE() volatile

Set CH2_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_CH2_CTRL_TRIG_INCR_WRITE() volatile

Clear CH2_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_CH2_CTRL_TRIG_INCR_WRITE() volatile

Toggle CH2_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_CH2_CTRL_TRIG_RING_SIZE get_CH2_CTRL_TRIG_RING_SIZE() volatile

Get CH2_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_CH2_CTRL_TRIG_RING_SIZE(DMA_CH2_CTRL_TRIG_RING_SIZE value) volatile

Set CH2_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_CH2_CTRL_TRIG_RING_SEL() volatile

Get CH2_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_CH2_CTRL_TRIG_RING_SEL() volatile

Set CH2_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_CH2_CTRL_TRIG_RING_SEL() volatile

Clear CH2_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_CH2_CTRL_TRIG_RING_SEL() volatile

Toggle CH2_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_CH2_CTRL_TRIG_CHAIN_TO() volatile

Get CH2_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_CH2_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile

Set CH2_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_CH2_CTRL_TRIG_TREQ_SEL get_CH2_CTRL_TRIG_TREQ_SEL() volatile

Get CH2_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline void set_CH2_CTRL_TRIG_TREQ_SEL(DMA_CH2_CTRL_TRIG_TREQ_SEL value) volatile

Set CH2_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_CH2_CTRL_TRIG_IRQ_QUIET() volatile

Get CH2_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_CH2_CTRL_TRIG_IRQ_QUIET() volatile

Set CH2_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_CH2_CTRL_TRIG_IRQ_QUIET() volatile

Clear CH2_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_CH2_CTRL_TRIG_IRQ_QUIET() volatile

Toggle CH2_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_CH2_CTRL_TRIG_BSWAP() volatile

Get CH2_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_CH2_CTRL_TRIG_BSWAP() volatile

Set CH2_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_CH2_CTRL_TRIG_BSWAP() volatile

Clear CH2_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_CH2_CTRL_TRIG_BSWAP() volatile

Toggle CH2_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_CH2_CTRL_TRIG_SNIFF_EN() volatile

Get CH2_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_CH2_CTRL_TRIG_SNIFF_EN() volatile

Set CH2_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_CH2_CTRL_TRIG_SNIFF_EN() volatile

Clear CH2_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_CH2_CTRL_TRIG_SNIFF_EN() volatile

Toggle CH2_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_CH2_CTRL_TRIG_BUSY() volatile

Get CH2_CTRL_TRIG’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.

To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_CH2_CTRL_TRIG_WRITE_ERROR() volatile

Get CH2_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_CH2_CTRL_TRIG_WRITE_ERROR() volatile

Set CH2_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_CH2_CTRL_TRIG_WRITE_ERROR() volatile

Clear CH2_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_CH2_CTRL_TRIG_WRITE_ERROR() volatile

Toggle CH2_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_CH2_CTRL_TRIG_READ_ERROR() volatile

Get CH2_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_CH2_CTRL_TRIG_READ_ERROR() volatile

Set CH2_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_CH2_CTRL_TRIG_READ_ERROR() volatile

Clear CH2_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_CH2_CTRL_TRIG_READ_ERROR() volatile

Toggle CH2_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_CH2_CTRL_TRIG_AHB_ERROR() volatile

Get CH2_CTRL_TRIG’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_CH2_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY, DMA_CH2_CTRL_TRIG_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_CH2_CTRL_TRIG_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_CH2_CTRL_TRIG_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR) volatile

Get all of CH2_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 2 Control and Status

inline void set_CH2_CTRL_TRIG(bool EN, bool HIGH_PRIORITY, DMA_CH2_CTRL_TRIG_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_CH2_CTRL_TRIG_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_CH2_CTRL_TRIG_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR) volatile

Set all of CH2_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 2 Control and Status

inline bool get_CH3_CTRL_TRIG_EN() volatile

Get CH3_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_CH3_CTRL_TRIG_EN() volatile

Set CH3_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_CH3_CTRL_TRIG_EN() volatile

Clear CH3_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_CH3_CTRL_TRIG_EN() volatile

Toggle CH3_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_CH3_CTRL_TRIG_HIGH_PRIORITY() volatile

Get CH3_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_CH3_CTRL_TRIG_HIGH_PRIORITY() volatile

Set CH3_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_CH3_CTRL_TRIG_HIGH_PRIORITY() volatile

Clear CH3_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_CH3_CTRL_TRIG_HIGH_PRIORITY() volatile

Toggle CH3_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_CH3_CTRL_TRIG_DATA_SIZE get_CH3_CTRL_TRIG_DATA_SIZE() volatile

Get CH3_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_CH3_CTRL_TRIG_DATA_SIZE(DMA_CH3_CTRL_TRIG_DATA_SIZE value) volatile

Set CH3_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_CH3_CTRL_TRIG_INCR_READ() volatile

Get CH3_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void set_CH3_CTRL_TRIG_INCR_READ() volatile

Set CH3_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_CH3_CTRL_TRIG_INCR_READ() volatile

Clear CH3_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_CH3_CTRL_TRIG_INCR_READ() volatile

Toggle CH3_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_CH3_CTRL_TRIG_INCR_WRITE() volatile

Get CH3_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void set_CH3_CTRL_TRIG_INCR_WRITE() volatile

Set CH3_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_CH3_CTRL_TRIG_INCR_WRITE() volatile

Clear CH3_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_CH3_CTRL_TRIG_INCR_WRITE() volatile

Toggle CH3_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_CH3_CTRL_TRIG_RING_SIZE get_CH3_CTRL_TRIG_RING_SIZE() volatile

Get CH3_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_CH3_CTRL_TRIG_RING_SIZE(DMA_CH3_CTRL_TRIG_RING_SIZE value) volatile

Set CH3_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_CH3_CTRL_TRIG_RING_SEL() volatile

Get CH3_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_CH3_CTRL_TRIG_RING_SEL() volatile

Set CH3_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_CH3_CTRL_TRIG_RING_SEL() volatile

Clear CH3_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_CH3_CTRL_TRIG_RING_SEL() volatile

Toggle CH3_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_CH3_CTRL_TRIG_CHAIN_TO() volatile

Get CH3_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_CH3_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile

Set CH3_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_CH3_CTRL_TRIG_TREQ_SEL get_CH3_CTRL_TRIG_TREQ_SEL() volatile

Get CH3_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline void set_CH3_CTRL_TRIG_TREQ_SEL(DMA_CH3_CTRL_TRIG_TREQ_SEL value) volatile

Set CH3_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_CH3_CTRL_TRIG_IRQ_QUIET() volatile

Get CH3_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_CH3_CTRL_TRIG_IRQ_QUIET() volatile

Set CH3_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_CH3_CTRL_TRIG_IRQ_QUIET() volatile

Clear CH3_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_CH3_CTRL_TRIG_IRQ_QUIET() volatile

Toggle CH3_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_CH3_CTRL_TRIG_BSWAP() volatile

Get CH3_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_CH3_CTRL_TRIG_BSWAP() volatile

Set CH3_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_CH3_CTRL_TRIG_BSWAP() volatile

Clear CH3_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_CH3_CTRL_TRIG_BSWAP() volatile

Toggle CH3_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_CH3_CTRL_TRIG_SNIFF_EN() volatile

Get CH3_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_CH3_CTRL_TRIG_SNIFF_EN() volatile

Set CH3_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_CH3_CTRL_TRIG_SNIFF_EN() volatile

Clear CH3_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_CH3_CTRL_TRIG_SNIFF_EN() volatile

Toggle CH3_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_CH3_CTRL_TRIG_BUSY() volatile

Get CH3_CTRL_TRIG’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.

To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_CH3_CTRL_TRIG_WRITE_ERROR() volatile

Get CH3_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_CH3_CTRL_TRIG_WRITE_ERROR() volatile

Set CH3_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_CH3_CTRL_TRIG_WRITE_ERROR() volatile

Clear CH3_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_CH3_CTRL_TRIG_WRITE_ERROR() volatile

Toggle CH3_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_CH3_CTRL_TRIG_READ_ERROR() volatile

Get CH3_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_CH3_CTRL_TRIG_READ_ERROR() volatile

Set CH3_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_CH3_CTRL_TRIG_READ_ERROR() volatile

Clear CH3_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_CH3_CTRL_TRIG_READ_ERROR() volatile

Toggle CH3_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_CH3_CTRL_TRIG_AHB_ERROR() volatile

Get CH3_CTRL_TRIG’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_CH3_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY, DMA_CH3_CTRL_TRIG_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_CH3_CTRL_TRIG_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_CH3_CTRL_TRIG_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR) volatile

Get all of CH3_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 3 Control and Status

inline void set_CH3_CTRL_TRIG(bool EN, bool HIGH_PRIORITY, DMA_CH3_CTRL_TRIG_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_CH3_CTRL_TRIG_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_CH3_CTRL_TRIG_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR) volatile

Set all of CH3_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 3 Control and Status

inline bool get_CH4_CTRL_TRIG_EN() volatile

Get CH4_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_CH4_CTRL_TRIG_EN() volatile

Set CH4_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_CH4_CTRL_TRIG_EN() volatile

Clear CH4_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_CH4_CTRL_TRIG_EN() volatile

Toggle CH4_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_CH4_CTRL_TRIG_HIGH_PRIORITY() volatile

Get CH4_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_CH4_CTRL_TRIG_HIGH_PRIORITY() volatile

Set CH4_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_CH4_CTRL_TRIG_HIGH_PRIORITY() volatile

Clear CH4_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_CH4_CTRL_TRIG_HIGH_PRIORITY() volatile

Toggle CH4_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_CH4_CTRL_TRIG_DATA_SIZE get_CH4_CTRL_TRIG_DATA_SIZE() volatile

Get CH4_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_CH4_CTRL_TRIG_DATA_SIZE(DMA_CH4_CTRL_TRIG_DATA_SIZE value) volatile

Set CH4_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_CH4_CTRL_TRIG_INCR_READ() volatile

Get CH4_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void set_CH4_CTRL_TRIG_INCR_READ() volatile

Set CH4_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_CH4_CTRL_TRIG_INCR_READ() volatile

Clear CH4_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_CH4_CTRL_TRIG_INCR_READ() volatile

Toggle CH4_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_CH4_CTRL_TRIG_INCR_WRITE() volatile

Get CH4_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void set_CH4_CTRL_TRIG_INCR_WRITE() volatile

Set CH4_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_CH4_CTRL_TRIG_INCR_WRITE() volatile

Clear CH4_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_CH4_CTRL_TRIG_INCR_WRITE() volatile

Toggle CH4_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_CH4_CTRL_TRIG_RING_SIZE get_CH4_CTRL_TRIG_RING_SIZE() volatile

Get CH4_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_CH4_CTRL_TRIG_RING_SIZE(DMA_CH4_CTRL_TRIG_RING_SIZE value) volatile

Set CH4_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_CH4_CTRL_TRIG_RING_SEL() volatile

Get CH4_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_CH4_CTRL_TRIG_RING_SEL() volatile

Set CH4_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_CH4_CTRL_TRIG_RING_SEL() volatile

Clear CH4_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_CH4_CTRL_TRIG_RING_SEL() volatile

Toggle CH4_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_CH4_CTRL_TRIG_CHAIN_TO() volatile

Get CH4_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_CH4_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile

Set CH4_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_CH4_CTRL_TRIG_TREQ_SEL get_CH4_CTRL_TRIG_TREQ_SEL() volatile

Get CH4_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline void set_CH4_CTRL_TRIG_TREQ_SEL(DMA_CH4_CTRL_TRIG_TREQ_SEL value) volatile

Set CH4_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_CH4_CTRL_TRIG_IRQ_QUIET() volatile

Get CH4_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_CH4_CTRL_TRIG_IRQ_QUIET() volatile

Set CH4_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_CH4_CTRL_TRIG_IRQ_QUIET() volatile

Clear CH4_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_CH4_CTRL_TRIG_IRQ_QUIET() volatile

Toggle CH4_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_CH4_CTRL_TRIG_BSWAP() volatile

Get CH4_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_CH4_CTRL_TRIG_BSWAP() volatile

Set CH4_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_CH4_CTRL_TRIG_BSWAP() volatile

Clear CH4_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_CH4_CTRL_TRIG_BSWAP() volatile

Toggle CH4_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_CH4_CTRL_TRIG_SNIFF_EN() volatile

Get CH4_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_CH4_CTRL_TRIG_SNIFF_EN() volatile

Set CH4_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_CH4_CTRL_TRIG_SNIFF_EN() volatile

Clear CH4_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_CH4_CTRL_TRIG_SNIFF_EN() volatile

Toggle CH4_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_CH4_CTRL_TRIG_BUSY() volatile

Get CH4_CTRL_TRIG’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.

To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_CH4_CTRL_TRIG_WRITE_ERROR() volatile

Get CH4_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_CH4_CTRL_TRIG_WRITE_ERROR() volatile

Set CH4_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_CH4_CTRL_TRIG_WRITE_ERROR() volatile

Clear CH4_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_CH4_CTRL_TRIG_WRITE_ERROR() volatile

Toggle CH4_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_CH4_CTRL_TRIG_READ_ERROR() volatile

Get CH4_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_CH4_CTRL_TRIG_READ_ERROR() volatile

Set CH4_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_CH4_CTRL_TRIG_READ_ERROR() volatile

Clear CH4_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_CH4_CTRL_TRIG_READ_ERROR() volatile

Toggle CH4_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_CH4_CTRL_TRIG_AHB_ERROR() volatile

Get CH4_CTRL_TRIG’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_CH4_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY, DMA_CH4_CTRL_TRIG_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_CH4_CTRL_TRIG_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_CH4_CTRL_TRIG_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR) volatile

Get all of CH4_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 4 Control and Status

inline void set_CH4_CTRL_TRIG(bool EN, bool HIGH_PRIORITY, DMA_CH4_CTRL_TRIG_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_CH4_CTRL_TRIG_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_CH4_CTRL_TRIG_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR) volatile

Set all of CH4_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 4 Control and Status

inline bool get_CH5_CTRL_TRIG_EN() volatile

Get CH5_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_CH5_CTRL_TRIG_EN() volatile

Set CH5_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_CH5_CTRL_TRIG_EN() volatile

Clear CH5_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_CH5_CTRL_TRIG_EN() volatile

Toggle CH5_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_CH5_CTRL_TRIG_HIGH_PRIORITY() volatile

Get CH5_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_CH5_CTRL_TRIG_HIGH_PRIORITY() volatile

Set CH5_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_CH5_CTRL_TRIG_HIGH_PRIORITY() volatile

Clear CH5_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_CH5_CTRL_TRIG_HIGH_PRIORITY() volatile

Toggle CH5_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_CH5_CTRL_TRIG_DATA_SIZE get_CH5_CTRL_TRIG_DATA_SIZE() volatile

Get CH5_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_CH5_CTRL_TRIG_DATA_SIZE(DMA_CH5_CTRL_TRIG_DATA_SIZE value) volatile

Set CH5_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_CH5_CTRL_TRIG_INCR_READ() volatile

Get CH5_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void set_CH5_CTRL_TRIG_INCR_READ() volatile

Set CH5_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_CH5_CTRL_TRIG_INCR_READ() volatile

Clear CH5_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_CH5_CTRL_TRIG_INCR_READ() volatile

Toggle CH5_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_CH5_CTRL_TRIG_INCR_WRITE() volatile

Get CH5_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void set_CH5_CTRL_TRIG_INCR_WRITE() volatile

Set CH5_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_CH5_CTRL_TRIG_INCR_WRITE() volatile

Clear CH5_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_CH5_CTRL_TRIG_INCR_WRITE() volatile

Toggle CH5_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_CH5_CTRL_TRIG_RING_SIZE get_CH5_CTRL_TRIG_RING_SIZE() volatile

Get CH5_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_CH5_CTRL_TRIG_RING_SIZE(DMA_CH5_CTRL_TRIG_RING_SIZE value) volatile

Set CH5_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_CH5_CTRL_TRIG_RING_SEL() volatile

Get CH5_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_CH5_CTRL_TRIG_RING_SEL() volatile

Set CH5_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_CH5_CTRL_TRIG_RING_SEL() volatile

Clear CH5_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_CH5_CTRL_TRIG_RING_SEL() volatile

Toggle CH5_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_CH5_CTRL_TRIG_CHAIN_TO() volatile

Get CH5_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_CH5_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile

Set CH5_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_CH5_CTRL_TRIG_TREQ_SEL get_CH5_CTRL_TRIG_TREQ_SEL() volatile

Get CH5_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline void set_CH5_CTRL_TRIG_TREQ_SEL(DMA_CH5_CTRL_TRIG_TREQ_SEL value) volatile

Set CH5_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_CH5_CTRL_TRIG_IRQ_QUIET() volatile

Get CH5_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_CH5_CTRL_TRIG_IRQ_QUIET() volatile

Set CH5_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_CH5_CTRL_TRIG_IRQ_QUIET() volatile

Clear CH5_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_CH5_CTRL_TRIG_IRQ_QUIET() volatile

Toggle CH5_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_CH5_CTRL_TRIG_BSWAP() volatile

Get CH5_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_CH5_CTRL_TRIG_BSWAP() volatile

Set CH5_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_CH5_CTRL_TRIG_BSWAP() volatile

Clear CH5_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_CH5_CTRL_TRIG_BSWAP() volatile

Toggle CH5_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_CH5_CTRL_TRIG_SNIFF_EN() volatile

Get CH5_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_CH5_CTRL_TRIG_SNIFF_EN() volatile

Set CH5_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_CH5_CTRL_TRIG_SNIFF_EN() volatile

Clear CH5_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_CH5_CTRL_TRIG_SNIFF_EN() volatile

Toggle CH5_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_CH5_CTRL_TRIG_BUSY() volatile

Get CH5_CTRL_TRIG’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.

To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_CH5_CTRL_TRIG_WRITE_ERROR() volatile

Get CH5_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_CH5_CTRL_TRIG_WRITE_ERROR() volatile

Set CH5_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_CH5_CTRL_TRIG_WRITE_ERROR() volatile

Clear CH5_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_CH5_CTRL_TRIG_WRITE_ERROR() volatile

Toggle CH5_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_CH5_CTRL_TRIG_READ_ERROR() volatile

Get CH5_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_CH5_CTRL_TRIG_READ_ERROR() volatile

Set CH5_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_CH5_CTRL_TRIG_READ_ERROR() volatile

Clear CH5_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_CH5_CTRL_TRIG_READ_ERROR() volatile

Toggle CH5_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_CH5_CTRL_TRIG_AHB_ERROR() volatile

Get CH5_CTRL_TRIG’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_CH5_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY, DMA_CH5_CTRL_TRIG_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_CH5_CTRL_TRIG_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_CH5_CTRL_TRIG_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR) volatile

Get all of CH5_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 5 Control and Status

inline void set_CH5_CTRL_TRIG(bool EN, bool HIGH_PRIORITY, DMA_CH5_CTRL_TRIG_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_CH5_CTRL_TRIG_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_CH5_CTRL_TRIG_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR) volatile

Set all of CH5_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 5 Control and Status

inline bool get_CH6_CTRL_TRIG_EN() volatile

Get CH6_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_CH6_CTRL_TRIG_EN() volatile

Set CH6_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_CH6_CTRL_TRIG_EN() volatile

Clear CH6_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_CH6_CTRL_TRIG_EN() volatile

Toggle CH6_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_CH6_CTRL_TRIG_HIGH_PRIORITY() volatile

Get CH6_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_CH6_CTRL_TRIG_HIGH_PRIORITY() volatile

Set CH6_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_CH6_CTRL_TRIG_HIGH_PRIORITY() volatile

Clear CH6_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_CH6_CTRL_TRIG_HIGH_PRIORITY() volatile

Toggle CH6_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_CH6_CTRL_TRIG_DATA_SIZE get_CH6_CTRL_TRIG_DATA_SIZE() volatile

Get CH6_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_CH6_CTRL_TRIG_DATA_SIZE(DMA_CH6_CTRL_TRIG_DATA_SIZE value) volatile

Set CH6_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_CH6_CTRL_TRIG_INCR_READ() volatile

Get CH6_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void set_CH6_CTRL_TRIG_INCR_READ() volatile

Set CH6_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_CH6_CTRL_TRIG_INCR_READ() volatile

Clear CH6_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_CH6_CTRL_TRIG_INCR_READ() volatile

Toggle CH6_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_CH6_CTRL_TRIG_INCR_WRITE() volatile

Get CH6_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void set_CH6_CTRL_TRIG_INCR_WRITE() volatile

Set CH6_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_CH6_CTRL_TRIG_INCR_WRITE() volatile

Clear CH6_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_CH6_CTRL_TRIG_INCR_WRITE() volatile

Toggle CH6_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_CH6_CTRL_TRIG_RING_SIZE get_CH6_CTRL_TRIG_RING_SIZE() volatile

Get CH6_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_CH6_CTRL_TRIG_RING_SIZE(DMA_CH6_CTRL_TRIG_RING_SIZE value) volatile

Set CH6_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_CH6_CTRL_TRIG_RING_SEL() volatile

Get CH6_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_CH6_CTRL_TRIG_RING_SEL() volatile

Set CH6_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_CH6_CTRL_TRIG_RING_SEL() volatile

Clear CH6_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_CH6_CTRL_TRIG_RING_SEL() volatile

Toggle CH6_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_CH6_CTRL_TRIG_CHAIN_TO() volatile

Get CH6_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_CH6_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile

Set CH6_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_CH6_CTRL_TRIG_TREQ_SEL get_CH6_CTRL_TRIG_TREQ_SEL() volatile

Get CH6_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline void set_CH6_CTRL_TRIG_TREQ_SEL(DMA_CH6_CTRL_TRIG_TREQ_SEL value) volatile

Set CH6_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_CH6_CTRL_TRIG_IRQ_QUIET() volatile

Get CH6_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_CH6_CTRL_TRIG_IRQ_QUIET() volatile

Set CH6_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_CH6_CTRL_TRIG_IRQ_QUIET() volatile

Clear CH6_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_CH6_CTRL_TRIG_IRQ_QUIET() volatile

Toggle CH6_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_CH6_CTRL_TRIG_BSWAP() volatile

Get CH6_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_CH6_CTRL_TRIG_BSWAP() volatile

Set CH6_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_CH6_CTRL_TRIG_BSWAP() volatile

Clear CH6_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_CH6_CTRL_TRIG_BSWAP() volatile

Toggle CH6_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_CH6_CTRL_TRIG_SNIFF_EN() volatile

Get CH6_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_CH6_CTRL_TRIG_SNIFF_EN() volatile

Set CH6_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_CH6_CTRL_TRIG_SNIFF_EN() volatile

Clear CH6_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_CH6_CTRL_TRIG_SNIFF_EN() volatile

Toggle CH6_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_CH6_CTRL_TRIG_BUSY() volatile

Get CH6_CTRL_TRIG’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.

To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_CH6_CTRL_TRIG_WRITE_ERROR() volatile

Get CH6_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_CH6_CTRL_TRIG_WRITE_ERROR() volatile

Set CH6_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_CH6_CTRL_TRIG_WRITE_ERROR() volatile

Clear CH6_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_CH6_CTRL_TRIG_WRITE_ERROR() volatile

Toggle CH6_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_CH6_CTRL_TRIG_READ_ERROR() volatile

Get CH6_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_CH6_CTRL_TRIG_READ_ERROR() volatile

Set CH6_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_CH6_CTRL_TRIG_READ_ERROR() volatile

Clear CH6_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_CH6_CTRL_TRIG_READ_ERROR() volatile

Toggle CH6_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_CH6_CTRL_TRIG_AHB_ERROR() volatile

Get CH6_CTRL_TRIG’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_CH6_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY, DMA_CH6_CTRL_TRIG_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_CH6_CTRL_TRIG_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_CH6_CTRL_TRIG_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR) volatile

Get all of CH6_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 6 Control and Status

inline void set_CH6_CTRL_TRIG(bool EN, bool HIGH_PRIORITY, DMA_CH6_CTRL_TRIG_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_CH6_CTRL_TRIG_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_CH6_CTRL_TRIG_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR) volatile

Set all of CH6_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 6 Control and Status

inline bool get_CH7_CTRL_TRIG_EN() volatile

Get CH7_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_CH7_CTRL_TRIG_EN() volatile

Set CH7_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_CH7_CTRL_TRIG_EN() volatile

Clear CH7_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_CH7_CTRL_TRIG_EN() volatile

Toggle CH7_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_CH7_CTRL_TRIG_HIGH_PRIORITY() volatile

Get CH7_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_CH7_CTRL_TRIG_HIGH_PRIORITY() volatile

Set CH7_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_CH7_CTRL_TRIG_HIGH_PRIORITY() volatile

Clear CH7_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_CH7_CTRL_TRIG_HIGH_PRIORITY() volatile

Toggle CH7_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_CH7_CTRL_TRIG_DATA_SIZE get_CH7_CTRL_TRIG_DATA_SIZE() volatile

Get CH7_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_CH7_CTRL_TRIG_DATA_SIZE(DMA_CH7_CTRL_TRIG_DATA_SIZE value) volatile

Set CH7_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_CH7_CTRL_TRIG_INCR_READ() volatile

Get CH7_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void set_CH7_CTRL_TRIG_INCR_READ() volatile

Set CH7_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_CH7_CTRL_TRIG_INCR_READ() volatile

Clear CH7_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_CH7_CTRL_TRIG_INCR_READ() volatile

Toggle CH7_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_CH7_CTRL_TRIG_INCR_WRITE() volatile

Get CH7_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void set_CH7_CTRL_TRIG_INCR_WRITE() volatile

Set CH7_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_CH7_CTRL_TRIG_INCR_WRITE() volatile

Clear CH7_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_CH7_CTRL_TRIG_INCR_WRITE() volatile

Toggle CH7_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_CH7_CTRL_TRIG_RING_SIZE get_CH7_CTRL_TRIG_RING_SIZE() volatile

Get CH7_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_CH7_CTRL_TRIG_RING_SIZE(DMA_CH7_CTRL_TRIG_RING_SIZE value) volatile

Set CH7_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_CH7_CTRL_TRIG_RING_SEL() volatile

Get CH7_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_CH7_CTRL_TRIG_RING_SEL() volatile

Set CH7_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_CH7_CTRL_TRIG_RING_SEL() volatile

Clear CH7_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_CH7_CTRL_TRIG_RING_SEL() volatile

Toggle CH7_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_CH7_CTRL_TRIG_CHAIN_TO() volatile

Get CH7_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_CH7_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile

Set CH7_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_CH7_CTRL_TRIG_TREQ_SEL get_CH7_CTRL_TRIG_TREQ_SEL() volatile

Get CH7_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline void set_CH7_CTRL_TRIG_TREQ_SEL(DMA_CH7_CTRL_TRIG_TREQ_SEL value) volatile

Set CH7_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_CH7_CTRL_TRIG_IRQ_QUIET() volatile

Get CH7_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_CH7_CTRL_TRIG_IRQ_QUIET() volatile

Set CH7_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_CH7_CTRL_TRIG_IRQ_QUIET() volatile

Clear CH7_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_CH7_CTRL_TRIG_IRQ_QUIET() volatile

Toggle CH7_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_CH7_CTRL_TRIG_BSWAP() volatile

Get CH7_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_CH7_CTRL_TRIG_BSWAP() volatile

Set CH7_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_CH7_CTRL_TRIG_BSWAP() volatile

Clear CH7_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_CH7_CTRL_TRIG_BSWAP() volatile

Toggle CH7_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_CH7_CTRL_TRIG_SNIFF_EN() volatile

Get CH7_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_CH7_CTRL_TRIG_SNIFF_EN() volatile

Set CH7_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_CH7_CTRL_TRIG_SNIFF_EN() volatile

Clear CH7_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_CH7_CTRL_TRIG_SNIFF_EN() volatile

Toggle CH7_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_CH7_CTRL_TRIG_BUSY() volatile

Get CH7_CTRL_TRIG’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.

To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_CH7_CTRL_TRIG_WRITE_ERROR() volatile

Get CH7_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_CH7_CTRL_TRIG_WRITE_ERROR() volatile

Set CH7_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_CH7_CTRL_TRIG_WRITE_ERROR() volatile

Clear CH7_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_CH7_CTRL_TRIG_WRITE_ERROR() volatile

Toggle CH7_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_CH7_CTRL_TRIG_READ_ERROR() volatile

Get CH7_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_CH7_CTRL_TRIG_READ_ERROR() volatile

Set CH7_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_CH7_CTRL_TRIG_READ_ERROR() volatile

Clear CH7_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_CH7_CTRL_TRIG_READ_ERROR() volatile

Toggle CH7_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_CH7_CTRL_TRIG_AHB_ERROR() volatile

Get CH7_CTRL_TRIG’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_CH7_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY, DMA_CH7_CTRL_TRIG_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_CH7_CTRL_TRIG_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_CH7_CTRL_TRIG_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR) volatile

Get all of CH7_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 7 Control and Status

inline void set_CH7_CTRL_TRIG(bool EN, bool HIGH_PRIORITY, DMA_CH7_CTRL_TRIG_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_CH7_CTRL_TRIG_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_CH7_CTRL_TRIG_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR) volatile

Set all of CH7_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 7 Control and Status

inline bool get_CH8_CTRL_TRIG_EN() volatile

Get CH8_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_CH8_CTRL_TRIG_EN() volatile

Set CH8_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_CH8_CTRL_TRIG_EN() volatile

Clear CH8_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_CH8_CTRL_TRIG_EN() volatile

Toggle CH8_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_CH8_CTRL_TRIG_HIGH_PRIORITY() volatile

Get CH8_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_CH8_CTRL_TRIG_HIGH_PRIORITY() volatile

Set CH8_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_CH8_CTRL_TRIG_HIGH_PRIORITY() volatile

Clear CH8_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_CH8_CTRL_TRIG_HIGH_PRIORITY() volatile

Toggle CH8_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_CH8_CTRL_TRIG_DATA_SIZE get_CH8_CTRL_TRIG_DATA_SIZE() volatile

Get CH8_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_CH8_CTRL_TRIG_DATA_SIZE(DMA_CH8_CTRL_TRIG_DATA_SIZE value) volatile

Set CH8_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_CH8_CTRL_TRIG_INCR_READ() volatile

Get CH8_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void set_CH8_CTRL_TRIG_INCR_READ() volatile

Set CH8_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_CH8_CTRL_TRIG_INCR_READ() volatile

Clear CH8_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_CH8_CTRL_TRIG_INCR_READ() volatile

Toggle CH8_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_CH8_CTRL_TRIG_INCR_WRITE() volatile

Get CH8_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void set_CH8_CTRL_TRIG_INCR_WRITE() volatile

Set CH8_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_CH8_CTRL_TRIG_INCR_WRITE() volatile

Clear CH8_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_CH8_CTRL_TRIG_INCR_WRITE() volatile

Toggle CH8_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_CH8_CTRL_TRIG_RING_SIZE get_CH8_CTRL_TRIG_RING_SIZE() volatile

Get CH8_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_CH8_CTRL_TRIG_RING_SIZE(DMA_CH8_CTRL_TRIG_RING_SIZE value) volatile

Set CH8_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_CH8_CTRL_TRIG_RING_SEL() volatile

Get CH8_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_CH8_CTRL_TRIG_RING_SEL() volatile

Set CH8_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_CH8_CTRL_TRIG_RING_SEL() volatile

Clear CH8_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_CH8_CTRL_TRIG_RING_SEL() volatile

Toggle CH8_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_CH8_CTRL_TRIG_CHAIN_TO() volatile

Get CH8_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_CH8_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile

Set CH8_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_CH8_CTRL_TRIG_TREQ_SEL get_CH8_CTRL_TRIG_TREQ_SEL() volatile

Get CH8_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline void set_CH8_CTRL_TRIG_TREQ_SEL(DMA_CH8_CTRL_TRIG_TREQ_SEL value) volatile

Set CH8_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_CH8_CTRL_TRIG_IRQ_QUIET() volatile

Get CH8_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_CH8_CTRL_TRIG_IRQ_QUIET() volatile

Set CH8_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_CH8_CTRL_TRIG_IRQ_QUIET() volatile

Clear CH8_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_CH8_CTRL_TRIG_IRQ_QUIET() volatile

Toggle CH8_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_CH8_CTRL_TRIG_BSWAP() volatile

Get CH8_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_CH8_CTRL_TRIG_BSWAP() volatile

Set CH8_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_CH8_CTRL_TRIG_BSWAP() volatile

Clear CH8_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_CH8_CTRL_TRIG_BSWAP() volatile

Toggle CH8_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_CH8_CTRL_TRIG_SNIFF_EN() volatile

Get CH8_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_CH8_CTRL_TRIG_SNIFF_EN() volatile

Set CH8_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_CH8_CTRL_TRIG_SNIFF_EN() volatile

Clear CH8_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_CH8_CTRL_TRIG_SNIFF_EN() volatile

Toggle CH8_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_CH8_CTRL_TRIG_BUSY() volatile

Get CH8_CTRL_TRIG’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.

To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_CH8_CTRL_TRIG_WRITE_ERROR() volatile

Get CH8_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_CH8_CTRL_TRIG_WRITE_ERROR() volatile

Set CH8_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_CH8_CTRL_TRIG_WRITE_ERROR() volatile

Clear CH8_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_CH8_CTRL_TRIG_WRITE_ERROR() volatile

Toggle CH8_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_CH8_CTRL_TRIG_READ_ERROR() volatile

Get CH8_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_CH8_CTRL_TRIG_READ_ERROR() volatile

Set CH8_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_CH8_CTRL_TRIG_READ_ERROR() volatile

Clear CH8_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_CH8_CTRL_TRIG_READ_ERROR() volatile

Toggle CH8_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_CH8_CTRL_TRIG_AHB_ERROR() volatile

Get CH8_CTRL_TRIG’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_CH8_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY, DMA_CH8_CTRL_TRIG_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_CH8_CTRL_TRIG_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_CH8_CTRL_TRIG_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR) volatile

Get all of CH8_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 8 Control and Status

inline void set_CH8_CTRL_TRIG(bool EN, bool HIGH_PRIORITY, DMA_CH8_CTRL_TRIG_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_CH8_CTRL_TRIG_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_CH8_CTRL_TRIG_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR) volatile

Set all of CH8_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 8 Control and Status

inline bool get_CH9_CTRL_TRIG_EN() volatile

Get CH9_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_CH9_CTRL_TRIG_EN() volatile

Set CH9_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_CH9_CTRL_TRIG_EN() volatile

Clear CH9_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_CH9_CTRL_TRIG_EN() volatile

Toggle CH9_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_CH9_CTRL_TRIG_HIGH_PRIORITY() volatile

Get CH9_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_CH9_CTRL_TRIG_HIGH_PRIORITY() volatile

Set CH9_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_CH9_CTRL_TRIG_HIGH_PRIORITY() volatile

Clear CH9_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_CH9_CTRL_TRIG_HIGH_PRIORITY() volatile

Toggle CH9_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_CH9_CTRL_TRIG_DATA_SIZE get_CH9_CTRL_TRIG_DATA_SIZE() volatile

Get CH9_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_CH9_CTRL_TRIG_DATA_SIZE(DMA_CH9_CTRL_TRIG_DATA_SIZE value) volatile

Set CH9_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_CH9_CTRL_TRIG_INCR_READ() volatile

Get CH9_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void set_CH9_CTRL_TRIG_INCR_READ() volatile

Set CH9_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_CH9_CTRL_TRIG_INCR_READ() volatile

Clear CH9_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_CH9_CTRL_TRIG_INCR_READ() volatile

Toggle CH9_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_CH9_CTRL_TRIG_INCR_WRITE() volatile

Get CH9_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void set_CH9_CTRL_TRIG_INCR_WRITE() volatile

Set CH9_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_CH9_CTRL_TRIG_INCR_WRITE() volatile

Clear CH9_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_CH9_CTRL_TRIG_INCR_WRITE() volatile

Toggle CH9_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_CH9_CTRL_TRIG_RING_SIZE get_CH9_CTRL_TRIG_RING_SIZE() volatile

Get CH9_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_CH9_CTRL_TRIG_RING_SIZE(DMA_CH9_CTRL_TRIG_RING_SIZE value) volatile

Set CH9_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_CH9_CTRL_TRIG_RING_SEL() volatile

Get CH9_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_CH9_CTRL_TRIG_RING_SEL() volatile

Set CH9_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_CH9_CTRL_TRIG_RING_SEL() volatile

Clear CH9_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_CH9_CTRL_TRIG_RING_SEL() volatile

Toggle CH9_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_CH9_CTRL_TRIG_CHAIN_TO() volatile

Get CH9_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_CH9_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile

Set CH9_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_CH9_CTRL_TRIG_TREQ_SEL get_CH9_CTRL_TRIG_TREQ_SEL() volatile

Get CH9_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline void set_CH9_CTRL_TRIG_TREQ_SEL(DMA_CH9_CTRL_TRIG_TREQ_SEL value) volatile

Set CH9_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_CH9_CTRL_TRIG_IRQ_QUIET() volatile

Get CH9_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_CH9_CTRL_TRIG_IRQ_QUIET() volatile

Set CH9_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_CH9_CTRL_TRIG_IRQ_QUIET() volatile

Clear CH9_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_CH9_CTRL_TRIG_IRQ_QUIET() volatile

Toggle CH9_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_CH9_CTRL_TRIG_BSWAP() volatile

Get CH9_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_CH9_CTRL_TRIG_BSWAP() volatile

Set CH9_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_CH9_CTRL_TRIG_BSWAP() volatile

Clear CH9_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_CH9_CTRL_TRIG_BSWAP() volatile

Toggle CH9_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_CH9_CTRL_TRIG_SNIFF_EN() volatile

Get CH9_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_CH9_CTRL_TRIG_SNIFF_EN() volatile

Set CH9_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_CH9_CTRL_TRIG_SNIFF_EN() volatile

Clear CH9_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_CH9_CTRL_TRIG_SNIFF_EN() volatile

Toggle CH9_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_CH9_CTRL_TRIG_BUSY() volatile

Get CH9_CTRL_TRIG’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.

To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_CH9_CTRL_TRIG_WRITE_ERROR() volatile

Get CH9_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_CH9_CTRL_TRIG_WRITE_ERROR() volatile

Set CH9_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_CH9_CTRL_TRIG_WRITE_ERROR() volatile

Clear CH9_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_CH9_CTRL_TRIG_WRITE_ERROR() volatile

Toggle CH9_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_CH9_CTRL_TRIG_READ_ERROR() volatile

Get CH9_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_CH9_CTRL_TRIG_READ_ERROR() volatile

Set CH9_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_CH9_CTRL_TRIG_READ_ERROR() volatile

Clear CH9_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_CH9_CTRL_TRIG_READ_ERROR() volatile

Toggle CH9_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_CH9_CTRL_TRIG_AHB_ERROR() volatile

Get CH9_CTRL_TRIG’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_CH9_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY, DMA_CH9_CTRL_TRIG_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_CH9_CTRL_TRIG_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_CH9_CTRL_TRIG_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR) volatile

Get all of CH9_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 9 Control and Status

inline void set_CH9_CTRL_TRIG(bool EN, bool HIGH_PRIORITY, DMA_CH9_CTRL_TRIG_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_CH9_CTRL_TRIG_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_CH9_CTRL_TRIG_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR) volatile

Set all of CH9_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 9 Control and Status

inline bool get_CH10_CTRL_TRIG_EN() volatile

Get CH10_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_CH10_CTRL_TRIG_EN() volatile

Set CH10_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_CH10_CTRL_TRIG_EN() volatile

Clear CH10_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_CH10_CTRL_TRIG_EN() volatile

Toggle CH10_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_CH10_CTRL_TRIG_HIGH_PRIORITY() volatile

Get CH10_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_CH10_CTRL_TRIG_HIGH_PRIORITY() volatile

Set CH10_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_CH10_CTRL_TRIG_HIGH_PRIORITY() volatile

Clear CH10_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_CH10_CTRL_TRIG_HIGH_PRIORITY() volatile

Toggle CH10_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_CH10_CTRL_TRIG_DATA_SIZE get_CH10_CTRL_TRIG_DATA_SIZE() volatile

Get CH10_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_CH10_CTRL_TRIG_DATA_SIZE(DMA_CH10_CTRL_TRIG_DATA_SIZE value) volatile

Set CH10_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_CH10_CTRL_TRIG_INCR_READ() volatile

Get CH10_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void set_CH10_CTRL_TRIG_INCR_READ() volatile

Set CH10_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_CH10_CTRL_TRIG_INCR_READ() volatile

Clear CH10_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_CH10_CTRL_TRIG_INCR_READ() volatile

Toggle CH10_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_CH10_CTRL_TRIG_INCR_WRITE() volatile

Get CH10_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void set_CH10_CTRL_TRIG_INCR_WRITE() volatile

Set CH10_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_CH10_CTRL_TRIG_INCR_WRITE() volatile

Clear CH10_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_CH10_CTRL_TRIG_INCR_WRITE() volatile

Toggle CH10_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_CH10_CTRL_TRIG_RING_SIZE get_CH10_CTRL_TRIG_RING_SIZE() volatile

Get CH10_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_CH10_CTRL_TRIG_RING_SIZE(DMA_CH10_CTRL_TRIG_RING_SIZE value) volatile

Set CH10_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_CH10_CTRL_TRIG_RING_SEL() volatile

Get CH10_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_CH10_CTRL_TRIG_RING_SEL() volatile

Set CH10_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_CH10_CTRL_TRIG_RING_SEL() volatile

Clear CH10_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_CH10_CTRL_TRIG_RING_SEL() volatile

Toggle CH10_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_CH10_CTRL_TRIG_CHAIN_TO() volatile

Get CH10_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_CH10_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile

Set CH10_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_CH10_CTRL_TRIG_TREQ_SEL get_CH10_CTRL_TRIG_TREQ_SEL() volatile

Get CH10_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline void set_CH10_CTRL_TRIG_TREQ_SEL(DMA_CH10_CTRL_TRIG_TREQ_SEL value) volatile

Set CH10_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_CH10_CTRL_TRIG_IRQ_QUIET() volatile

Get CH10_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_CH10_CTRL_TRIG_IRQ_QUIET() volatile

Set CH10_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_CH10_CTRL_TRIG_IRQ_QUIET() volatile

Clear CH10_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_CH10_CTRL_TRIG_IRQ_QUIET() volatile

Toggle CH10_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_CH10_CTRL_TRIG_BSWAP() volatile

Get CH10_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_CH10_CTRL_TRIG_BSWAP() volatile

Set CH10_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_CH10_CTRL_TRIG_BSWAP() volatile

Clear CH10_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_CH10_CTRL_TRIG_BSWAP() volatile

Toggle CH10_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_CH10_CTRL_TRIG_SNIFF_EN() volatile

Get CH10_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_CH10_CTRL_TRIG_SNIFF_EN() volatile

Set CH10_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_CH10_CTRL_TRIG_SNIFF_EN() volatile

Clear CH10_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_CH10_CTRL_TRIG_SNIFF_EN() volatile

Toggle CH10_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_CH10_CTRL_TRIG_BUSY() volatile

Get CH10_CTRL_TRIG’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.

To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_CH10_CTRL_TRIG_WRITE_ERROR() volatile

Get CH10_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_CH10_CTRL_TRIG_WRITE_ERROR() volatile

Set CH10_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_CH10_CTRL_TRIG_WRITE_ERROR() volatile

Clear CH10_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_CH10_CTRL_TRIG_WRITE_ERROR() volatile

Toggle CH10_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_CH10_CTRL_TRIG_READ_ERROR() volatile

Get CH10_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_CH10_CTRL_TRIG_READ_ERROR() volatile

Set CH10_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_CH10_CTRL_TRIG_READ_ERROR() volatile

Clear CH10_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_CH10_CTRL_TRIG_READ_ERROR() volatile

Toggle CH10_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_CH10_CTRL_TRIG_AHB_ERROR() volatile

Get CH10_CTRL_TRIG’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_CH10_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY, DMA_CH10_CTRL_TRIG_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_CH10_CTRL_TRIG_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_CH10_CTRL_TRIG_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR) volatile

Get all of CH10_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 10 Control and Status

inline void set_CH10_CTRL_TRIG(bool EN, bool HIGH_PRIORITY, DMA_CH10_CTRL_TRIG_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_CH10_CTRL_TRIG_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_CH10_CTRL_TRIG_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR) volatile

Set all of CH10_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 10 Control and Status

inline bool get_CH11_CTRL_TRIG_EN() volatile

Get CH11_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_CH11_CTRL_TRIG_EN() volatile

Set CH11_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_CH11_CTRL_TRIG_EN() volatile

Clear CH11_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_CH11_CTRL_TRIG_EN() volatile

Toggle CH11_CTRL_TRIG’s EN bit.

DMA Channel Enable.

When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_CH11_CTRL_TRIG_HIGH_PRIORITY() volatile

Get CH11_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_CH11_CTRL_TRIG_HIGH_PRIORITY() volatile

Set CH11_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_CH11_CTRL_TRIG_HIGH_PRIORITY() volatile

Clear CH11_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_CH11_CTRL_TRIG_HIGH_PRIORITY() volatile

Toggle CH11_CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_CH11_CTRL_TRIG_DATA_SIZE get_CH11_CTRL_TRIG_DATA_SIZE() volatile

Get CH11_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_CH11_CTRL_TRIG_DATA_SIZE(DMA_CH11_CTRL_TRIG_DATA_SIZE value) volatile

Set CH11_CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_CH11_CTRL_TRIG_INCR_READ() volatile

Get CH11_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void set_CH11_CTRL_TRIG_INCR_READ() volatile

Set CH11_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_CH11_CTRL_TRIG_INCR_READ() volatile

Clear CH11_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_CH11_CTRL_TRIG_INCR_READ() volatile

Toggle CH11_CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_CH11_CTRL_TRIG_INCR_WRITE() volatile

Get CH11_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void set_CH11_CTRL_TRIG_INCR_WRITE() volatile

Set CH11_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_CH11_CTRL_TRIG_INCR_WRITE() volatile

Clear CH11_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_CH11_CTRL_TRIG_INCR_WRITE() volatile

Toggle CH11_CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_CH11_CTRL_TRIG_RING_SIZE get_CH11_CTRL_TRIG_RING_SIZE() volatile

Get CH11_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_CH11_CTRL_TRIG_RING_SIZE(DMA_CH11_CTRL_TRIG_RING_SIZE value) volatile

Set CH11_CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_CH11_CTRL_TRIG_RING_SEL() volatile

Get CH11_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_CH11_CTRL_TRIG_RING_SEL() volatile

Set CH11_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_CH11_CTRL_TRIG_RING_SEL() volatile

Clear CH11_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_CH11_CTRL_TRIG_RING_SEL() volatile

Toggle CH11_CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses.

If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_CH11_CTRL_TRIG_CHAIN_TO() volatile

Get CH11_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_CH11_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile

Set CH11_CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_CH11_CTRL_TRIG_TREQ_SEL get_CH11_CTRL_TRIG_TREQ_SEL() volatile

Get CH11_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline void set_CH11_CTRL_TRIG_TREQ_SEL(DMA_CH11_CTRL_TRIG_TREQ_SEL value) volatile

Set CH11_CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal.

The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).

0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_CH11_CTRL_TRIG_IRQ_QUIET() volatile

Get CH11_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_CH11_CTRL_TRIG_IRQ_QUIET() volatile

Set CH11_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_CH11_CTRL_TRIG_IRQ_QUIET() volatile

Clear CH11_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_CH11_CTRL_TRIG_IRQ_QUIET() volatile

Toggle CH11_CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_CH11_CTRL_TRIG_BSWAP() volatile

Get CH11_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_CH11_CTRL_TRIG_BSWAP() volatile

Set CH11_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_CH11_CTRL_TRIG_BSWAP() volatile

Clear CH11_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_CH11_CTRL_TRIG_BSWAP() volatile

Toggle CH11_CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data.

For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_CH11_CTRL_TRIG_SNIFF_EN() volatile

Get CH11_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_CH11_CTRL_TRIG_SNIFF_EN() volatile

Set CH11_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_CH11_CTRL_TRIG_SNIFF_EN() volatile

Clear CH11_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_CH11_CTRL_TRIG_SNIFF_EN() volatile

Toggle CH11_CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_CH11_CTRL_TRIG_BUSY() volatile

Get CH11_CTRL_TRIG’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.

To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_CH11_CTRL_TRIG_WRITE_ERROR() volatile

Get CH11_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_CH11_CTRL_TRIG_WRITE_ERROR() volatile

Set CH11_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_CH11_CTRL_TRIG_WRITE_ERROR() volatile

Clear CH11_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_CH11_CTRL_TRIG_WRITE_ERROR() volatile

Toggle CH11_CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear.

WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_CH11_CTRL_TRIG_READ_ERROR() volatile

Get CH11_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_CH11_CTRL_TRIG_READ_ERROR() volatile

Set CH11_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_CH11_CTRL_TRIG_READ_ERROR() volatile

Clear CH11_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_CH11_CTRL_TRIG_READ_ERROR() volatile

Toggle CH11_CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear.

READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_CH11_CTRL_TRIG_AHB_ERROR() volatile

Get CH11_CTRL_TRIG’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_CH11_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY, DMA_CH11_CTRL_TRIG_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_CH11_CTRL_TRIG_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_CH11_CTRL_TRIG_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR) volatile

Get all of CH11_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 11 Control and Status

inline void set_CH11_CTRL_TRIG(bool EN, bool HIGH_PRIORITY, DMA_CH11_CTRL_TRIG_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_CH11_CTRL_TRIG_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_CH11_CTRL_TRIG_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR) volatile

Set all of CH11_CTRL_TRIG’s bit fields.

(read-write) DMA Channel 11 Control and Status

inline uint16_t get_INTR_INTR() volatile

Get INTR’s INTR field.

Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.

Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.

This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.

It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.

inline void set_INTR_INTR(uint16_t value) volatile

Set INTR’s INTR field.

Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.

Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.

This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.

It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.

inline uint16_t get_INTE0_INTE0() volatile

Get INTE0’s INTE0 field.

Set bit n to pass interrupts from channel n to DMA IRQ 0.

inline void set_INTE0_INTE0(uint16_t value) volatile

Set INTE0’s INTE0 field.

Set bit n to pass interrupts from channel n to DMA IRQ 0.

inline uint16_t get_INTF0_INTF0() volatile

Get INTF0’s INTF0 field.

Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.

inline void set_INTF0_INTF0(uint16_t value) volatile

Set INTF0’s INTF0 field.

Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.

inline uint16_t get_INTS0_INTS0() volatile

Get INTS0’s INTS0 field.

Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.

Channel interrupts can be cleared by writing a bit mask here.

inline void set_INTS0_INTS0(uint16_t value) volatile

Set INTS0’s INTS0 field.

Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.

Channel interrupts can be cleared by writing a bit mask here.

inline uint16_t get_INTE1_INTE1() volatile

Get INTE1’s INTE1 field.

Set bit n to pass interrupts from channel n to DMA IRQ 1.

inline void set_INTE1_INTE1(uint16_t value) volatile

Set INTE1’s INTE1 field.

Set bit n to pass interrupts from channel n to DMA IRQ 1.

inline uint16_t get_INTF1_INTF1() volatile

Get INTF1’s INTF1 field.

Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.

inline void set_INTF1_INTF1(uint16_t value) volatile

Set INTF1’s INTF1 field.

Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.

inline uint16_t get_INTS1_INTS1() volatile

Get INTS1’s INTS1 field.

Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.

Channel interrupts can be cleared by writing a bit mask here.

inline void set_INTS1_INTS1(uint16_t value) volatile

Set INTS1’s INTS1 field.

Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.

Channel interrupts can be cleared by writing a bit mask here.

inline uint16_t get_TIMER0_Y() volatile

Get TIMER0’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline void set_TIMER0_Y(uint16_t value) volatile

Set TIMER0’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline uint16_t get_TIMER0_X() volatile

Get TIMER0’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void set_TIMER0_X(uint16_t value) volatile

Set TIMER0’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void get_TIMER0(uint16_t &Y, uint16_t &X) volatile

Get all of TIMER0’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer

The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline void set_TIMER0(uint16_t Y, uint16_t X) volatile

Set all of TIMER0’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer

The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline uint16_t get_TIMER1_Y() volatile

Get TIMER1’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline void set_TIMER1_Y(uint16_t value) volatile

Set TIMER1’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline uint16_t get_TIMER1_X() volatile

Get TIMER1’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void set_TIMER1_X(uint16_t value) volatile

Set TIMER1’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void get_TIMER1(uint16_t &Y, uint16_t &X) volatile

Get all of TIMER1’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer

The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline void set_TIMER1(uint16_t Y, uint16_t X) volatile

Set all of TIMER1’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer

The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline uint16_t get_TIMER2_Y() volatile

Get TIMER2’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline void set_TIMER2_Y(uint16_t value) volatile

Set TIMER2’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline uint16_t get_TIMER2_X() volatile

Get TIMER2’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void set_TIMER2_X(uint16_t value) volatile

Set TIMER2’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void get_TIMER2(uint16_t &Y, uint16_t &X) volatile

Get all of TIMER2’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer

The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline void set_TIMER2(uint16_t Y, uint16_t X) volatile

Set all of TIMER2’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer

The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline uint16_t get_TIMER3_Y() volatile

Get TIMER3’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline void set_TIMER3_Y(uint16_t value) volatile

Set TIMER3’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline uint16_t get_TIMER3_X() volatile

Get TIMER3’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void set_TIMER3_X(uint16_t value) volatile

Set TIMER3’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void get_TIMER3(uint16_t &Y, uint16_t &X) volatile

Get all of TIMER3’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer

The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline void set_TIMER3(uint16_t Y, uint16_t X) volatile

Set all of TIMER3’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer

The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline uint16_t get_MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER() volatile

Get MULTI_CHAN_TRIGGER’s MULTI_CHAN_TRIGGER field.

Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel’s trigger register; the channel will start if it is currently enabled and not already busy.

inline void set_MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER(uint16_t value) volatile

Set MULTI_CHAN_TRIGGER’s MULTI_CHAN_TRIGGER field.

Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel’s trigger register; the channel will start if it is currently enabled and not already busy.

inline bool get_SNIFF_CTRL_EN() volatile

Get SNIFF_CTRL’s EN bit.

Enable sniffer

inline void set_SNIFF_CTRL_EN() volatile

Set SNIFF_CTRL’s EN bit.

Enable sniffer

inline void clear_SNIFF_CTRL_EN() volatile

Clear SNIFF_CTRL’s EN bit.

Enable sniffer

inline void toggle_SNIFF_CTRL_EN() volatile

Toggle SNIFF_CTRL’s EN bit.

Enable sniffer

inline uint8_t get_SNIFF_CTRL_DMACH() volatile

Get SNIFF_CTRL’s DMACH field.

DMA channel for Sniffer to observe

inline void set_SNIFF_CTRL_DMACH(uint8_t value) volatile

Set SNIFF_CTRL’s DMACH field.

DMA channel for Sniffer to observe

inline DMA_SNIFF_CTRL_CALC get_SNIFF_CTRL_CALC() volatile

Get SNIFF_CTRL’s CALC field.

inline void set_SNIFF_CTRL_CALC(DMA_SNIFF_CTRL_CALC value) volatile

Set SNIFF_CTRL’s CALC field.

inline bool get_SNIFF_CTRL_BSWAP() volatile

Get SNIFF_CTRL’s BSWAP bit.

Locally perform a byte reverse on the sniffed data, before feeding into checksum.

Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer’s point of view.

inline void set_SNIFF_CTRL_BSWAP() volatile

Set SNIFF_CTRL’s BSWAP bit.

Locally perform a byte reverse on the sniffed data, before feeding into checksum.

Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer’s point of view.

inline void clear_SNIFF_CTRL_BSWAP() volatile

Clear SNIFF_CTRL’s BSWAP bit.

Locally perform a byte reverse on the sniffed data, before feeding into checksum.

Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer’s point of view.

inline void toggle_SNIFF_CTRL_BSWAP() volatile

Toggle SNIFF_CTRL’s BSWAP bit.

Locally perform a byte reverse on the sniffed data, before feeding into checksum.

Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer’s point of view.

inline bool get_SNIFF_CTRL_OUT_REV() volatile

Get SNIFF_CTRL’s OUT_REV bit.

If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline void set_SNIFF_CTRL_OUT_REV() volatile

Set SNIFF_CTRL’s OUT_REV bit.

If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline void clear_SNIFF_CTRL_OUT_REV() volatile

Clear SNIFF_CTRL’s OUT_REV bit.

If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline void toggle_SNIFF_CTRL_OUT_REV() volatile

Toggle SNIFF_CTRL’s OUT_REV bit.

If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline bool get_SNIFF_CTRL_OUT_INV() volatile

Get SNIFF_CTRL’s OUT_INV bit.

If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline void set_SNIFF_CTRL_OUT_INV() volatile

Set SNIFF_CTRL’s OUT_INV bit.

If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline void clear_SNIFF_CTRL_OUT_INV() volatile

Clear SNIFF_CTRL’s OUT_INV bit.

If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline void toggle_SNIFF_CTRL_OUT_INV() volatile

Toggle SNIFF_CTRL’s OUT_INV bit.

If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline void get_SNIFF_CTRL(bool &EN, uint8_t &DMACH, DMA_SNIFF_CTRL_CALC &CALC, bool &BSWAP, bool &OUT_REV, bool &OUT_INV) volatile

Get all of SNIFF_CTRL’s bit fields.

(read-write) Sniffer Control

inline void set_SNIFF_CTRL(bool EN, uint8_t DMACH, DMA_SNIFF_CTRL_CALC CALC, bool BSWAP, bool OUT_REV, bool OUT_INV) volatile

Set all of SNIFF_CTRL’s bit fields.

(read-write) Sniffer Control

inline uint8_t get_FIFO_LEVELS_TDF_LVL() volatile

Get FIFO_LEVELS’s TDF_LVL field.

Current Transfer-Data-FIFO fill level

inline uint8_t get_FIFO_LEVELS_WAF_LVL() volatile

Get FIFO_LEVELS’s WAF_LVL field.

Current Write-Address-FIFO fill level

inline uint8_t get_FIFO_LEVELS_RAF_LVL() volatile

Get FIFO_LEVELS’s RAF_LVL field.

Current Read-Address-FIFO fill level

inline void get_FIFO_LEVELS(uint8_t &TDF_LVL, uint8_t &WAF_LVL, uint8_t &RAF_LVL) volatile

Get all of FIFO_LEVELS’s bit fields.

(read-only) Debug RAF, WAF, TDF levels

inline uint16_t get_CHAN_ABORT_CHAN_ABORT() volatile

Get CHAN_ABORT’s CHAN_ABORT field.

Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.

After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.

inline void set_CHAN_ABORT_CHAN_ABORT(uint16_t value) volatile

Set CHAN_ABORT’s CHAN_ABORT field.

Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.

After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.

inline uint8_t get_N_CHANNELS_N_CHANNELS() volatile

Get N_CHANNELS’s N_CHANNELS field.

inline uint8_t get_CH0_DBG_CTDREQ_CH0_DBG_CTDREQ() volatile

Get CH0_DBG_CTDREQ’s CH0_DBG_CTDREQ field.

inline void set_CH0_DBG_CTDREQ_CH0_DBG_CTDREQ(uint8_t value) volatile

Set CH0_DBG_CTDREQ’s CH0_DBG_CTDREQ field.

inline uint8_t get_CH1_DBG_CTDREQ_CH1_DBG_CTDREQ() volatile

Get CH1_DBG_CTDREQ’s CH1_DBG_CTDREQ field.

inline void set_CH1_DBG_CTDREQ_CH1_DBG_CTDREQ(uint8_t value) volatile

Set CH1_DBG_CTDREQ’s CH1_DBG_CTDREQ field.

inline uint8_t get_CH2_DBG_CTDREQ_CH2_DBG_CTDREQ() volatile

Get CH2_DBG_CTDREQ’s CH2_DBG_CTDREQ field.

inline void set_CH2_DBG_CTDREQ_CH2_DBG_CTDREQ(uint8_t value) volatile

Set CH2_DBG_CTDREQ’s CH2_DBG_CTDREQ field.

inline uint8_t get_CH3_DBG_CTDREQ_CH3_DBG_CTDREQ() volatile

Get CH3_DBG_CTDREQ’s CH3_DBG_CTDREQ field.

inline void set_CH3_DBG_CTDREQ_CH3_DBG_CTDREQ(uint8_t value) volatile

Set CH3_DBG_CTDREQ’s CH3_DBG_CTDREQ field.

inline uint8_t get_CH4_DBG_CTDREQ_CH4_DBG_CTDREQ() volatile

Get CH4_DBG_CTDREQ’s CH4_DBG_CTDREQ field.

inline void set_CH4_DBG_CTDREQ_CH4_DBG_CTDREQ(uint8_t value) volatile

Set CH4_DBG_CTDREQ’s CH4_DBG_CTDREQ field.

inline uint8_t get_CH5_DBG_CTDREQ_CH5_DBG_CTDREQ() volatile

Get CH5_DBG_CTDREQ’s CH5_DBG_CTDREQ field.

inline void set_CH5_DBG_CTDREQ_CH5_DBG_CTDREQ(uint8_t value) volatile

Set CH5_DBG_CTDREQ’s CH5_DBG_CTDREQ field.

inline uint8_t get_CH6_DBG_CTDREQ_CH6_DBG_CTDREQ() volatile

Get CH6_DBG_CTDREQ’s CH6_DBG_CTDREQ field.

inline void set_CH6_DBG_CTDREQ_CH6_DBG_CTDREQ(uint8_t value) volatile

Set CH6_DBG_CTDREQ’s CH6_DBG_CTDREQ field.

inline uint8_t get_CH7_DBG_CTDREQ_CH7_DBG_CTDREQ() volatile

Get CH7_DBG_CTDREQ’s CH7_DBG_CTDREQ field.

inline void set_CH7_DBG_CTDREQ_CH7_DBG_CTDREQ(uint8_t value) volatile

Set CH7_DBG_CTDREQ’s CH7_DBG_CTDREQ field.

inline uint8_t get_CH8_DBG_CTDREQ_CH8_DBG_CTDREQ() volatile

Get CH8_DBG_CTDREQ’s CH8_DBG_CTDREQ field.

inline void set_CH8_DBG_CTDREQ_CH8_DBG_CTDREQ(uint8_t value) volatile

Set CH8_DBG_CTDREQ’s CH8_DBG_CTDREQ field.

inline uint8_t get_CH9_DBG_CTDREQ_CH9_DBG_CTDREQ() volatile

Get CH9_DBG_CTDREQ’s CH9_DBG_CTDREQ field.

inline void set_CH9_DBG_CTDREQ_CH9_DBG_CTDREQ(uint8_t value) volatile

Set CH9_DBG_CTDREQ’s CH9_DBG_CTDREQ field.

inline uint8_t get_CH10_DBG_CTDREQ_CH10_DBG_CTDREQ() volatile

Get CH10_DBG_CTDREQ’s CH10_DBG_CTDREQ field.

inline void set_CH10_DBG_CTDREQ_CH10_DBG_CTDREQ(uint8_t value) volatile

Set CH10_DBG_CTDREQ’s CH10_DBG_CTDREQ field.

inline uint8_t get_CH11_DBG_CTDREQ_CH11_DBG_CTDREQ() volatile

Get CH11_DBG_CTDREQ’s CH11_DBG_CTDREQ field.

inline void set_CH11_DBG_CTDREQ_CH11_DBG_CTDREQ(uint8_t value) volatile

Set CH11_DBG_CTDREQ’s CH11_DBG_CTDREQ field.

Public Members

uint32_t CH0_READ_ADDR

(read-write) DMA Channel 0 Read Address pointer

This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

uint32_t CH0_WRITE_ADDR

(read-write) DMA Channel 0 Write Address pointer

This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

uint32_t CH0_TRANS_COUNT

(read-write) DMA Channel 0 Transfer Count

Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).

When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.

Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.

The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

uint32_t CH0_CTRL_TRIG

(read-write) DMA Channel 0 Control and Status

uint32_t CH0_AL1_CTRL

(read-write) Alias for channel 0 CTRL register

uint32_t CH0_AL1_READ_ADDR

(read-write) Alias for channel 0 READ_ADDR register

uint32_t CH0_AL1_WRITE_ADDR

(read-write) Alias for channel 0 WRITE_ADDR register

uint32_t CH0_AL1_TRANS_COUNT_TRIG

(read-write) Alias for channel 0 TRANS_COUNT register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH0_AL2_CTRL

(read-write) Alias for channel 0 CTRL register

uint32_t CH0_AL2_TRANS_COUNT

(read-write) Alias for channel 0 TRANS_COUNT register

uint32_t CH0_AL2_READ_ADDR

(read-write) Alias for channel 0 READ_ADDR register

uint32_t CH0_AL2_WRITE_ADDR_TRIG

(read-write) Alias for channel 0 WRITE_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH0_AL3_CTRL

(read-write) Alias for channel 0 CTRL register

uint32_t CH0_AL3_WRITE_ADDR

(read-write) Alias for channel 0 WRITE_ADDR register

uint32_t CH0_AL3_TRANS_COUNT

(read-write) Alias for channel 0 TRANS_COUNT register

uint32_t CH0_AL3_READ_ADDR_TRIG

(read-write) Alias for channel 0 READ_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH1_READ_ADDR

(read-write) DMA Channel 1 Read Address pointer

This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

uint32_t CH1_WRITE_ADDR

(read-write) DMA Channel 1 Write Address pointer

This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

uint32_t CH1_TRANS_COUNT

(read-write) DMA Channel 1 Transfer Count

Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).

When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.

Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.

The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

uint32_t CH1_CTRL_TRIG

(read-write) DMA Channel 1 Control and Status

uint32_t CH1_AL1_CTRL

(read-write) Alias for channel 1 CTRL register

uint32_t CH1_AL1_READ_ADDR

(read-write) Alias for channel 1 READ_ADDR register

uint32_t CH1_AL1_WRITE_ADDR

(read-write) Alias for channel 1 WRITE_ADDR register

uint32_t CH1_AL1_TRANS_COUNT_TRIG

(read-write) Alias for channel 1 TRANS_COUNT register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH1_AL2_CTRL

(read-write) Alias for channel 1 CTRL register

uint32_t CH1_AL2_TRANS_COUNT

(read-write) Alias for channel 1 TRANS_COUNT register

uint32_t CH1_AL2_READ_ADDR

(read-write) Alias for channel 1 READ_ADDR register

uint32_t CH1_AL2_WRITE_ADDR_TRIG

(read-write) Alias for channel 1 WRITE_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH1_AL3_CTRL

(read-write) Alias for channel 1 CTRL register

uint32_t CH1_AL3_WRITE_ADDR

(read-write) Alias for channel 1 WRITE_ADDR register

uint32_t CH1_AL3_TRANS_COUNT

(read-write) Alias for channel 1 TRANS_COUNT register

uint32_t CH1_AL3_READ_ADDR_TRIG

(read-write) Alias for channel 1 READ_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH2_READ_ADDR

(read-write) DMA Channel 2 Read Address pointer

This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

uint32_t CH2_WRITE_ADDR

(read-write) DMA Channel 2 Write Address pointer

This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

uint32_t CH2_TRANS_COUNT

(read-write) DMA Channel 2 Transfer Count

Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).

When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.

Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.

The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

uint32_t CH2_CTRL_TRIG

(read-write) DMA Channel 2 Control and Status

uint32_t CH2_AL1_CTRL

(read-write) Alias for channel 2 CTRL register

uint32_t CH2_AL1_READ_ADDR

(read-write) Alias for channel 2 READ_ADDR register

uint32_t CH2_AL1_WRITE_ADDR

(read-write) Alias for channel 2 WRITE_ADDR register

uint32_t CH2_AL1_TRANS_COUNT_TRIG

(read-write) Alias for channel 2 TRANS_COUNT register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH2_AL2_CTRL

(read-write) Alias for channel 2 CTRL register

uint32_t CH2_AL2_TRANS_COUNT

(read-write) Alias for channel 2 TRANS_COUNT register

uint32_t CH2_AL2_READ_ADDR

(read-write) Alias for channel 2 READ_ADDR register

uint32_t CH2_AL2_WRITE_ADDR_TRIG

(read-write) Alias for channel 2 WRITE_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH2_AL3_CTRL

(read-write) Alias for channel 2 CTRL register

uint32_t CH2_AL3_WRITE_ADDR

(read-write) Alias for channel 2 WRITE_ADDR register

uint32_t CH2_AL3_TRANS_COUNT

(read-write) Alias for channel 2 TRANS_COUNT register

uint32_t CH2_AL3_READ_ADDR_TRIG

(read-write) Alias for channel 2 READ_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH3_READ_ADDR

(read-write) DMA Channel 3 Read Address pointer

This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

uint32_t CH3_WRITE_ADDR

(read-write) DMA Channel 3 Write Address pointer

This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

uint32_t CH3_TRANS_COUNT

(read-write) DMA Channel 3 Transfer Count

Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).

When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.

Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.

The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

uint32_t CH3_CTRL_TRIG

(read-write) DMA Channel 3 Control and Status

uint32_t CH3_AL1_CTRL

(read-write) Alias for channel 3 CTRL register

uint32_t CH3_AL1_READ_ADDR

(read-write) Alias for channel 3 READ_ADDR register

uint32_t CH3_AL1_WRITE_ADDR

(read-write) Alias for channel 3 WRITE_ADDR register

uint32_t CH3_AL1_TRANS_COUNT_TRIG

(read-write) Alias for channel 3 TRANS_COUNT register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH3_AL2_CTRL

(read-write) Alias for channel 3 CTRL register

uint32_t CH3_AL2_TRANS_COUNT

(read-write) Alias for channel 3 TRANS_COUNT register

uint32_t CH3_AL2_READ_ADDR

(read-write) Alias for channel 3 READ_ADDR register

uint32_t CH3_AL2_WRITE_ADDR_TRIG

(read-write) Alias for channel 3 WRITE_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH3_AL3_CTRL

(read-write) Alias for channel 3 CTRL register

uint32_t CH3_AL3_WRITE_ADDR

(read-write) Alias for channel 3 WRITE_ADDR register

uint32_t CH3_AL3_TRANS_COUNT

(read-write) Alias for channel 3 TRANS_COUNT register

uint32_t CH3_AL3_READ_ADDR_TRIG

(read-write) Alias for channel 3 READ_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH4_READ_ADDR

(read-write) DMA Channel 4 Read Address pointer

This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

uint32_t CH4_WRITE_ADDR

(read-write) DMA Channel 4 Write Address pointer

This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

uint32_t CH4_TRANS_COUNT

(read-write) DMA Channel 4 Transfer Count

Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).

When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.

Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.

The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

uint32_t CH4_CTRL_TRIG

(read-write) DMA Channel 4 Control and Status

uint32_t CH4_AL1_CTRL

(read-write) Alias for channel 4 CTRL register

uint32_t CH4_AL1_READ_ADDR

(read-write) Alias for channel 4 READ_ADDR register

uint32_t CH4_AL1_WRITE_ADDR

(read-write) Alias for channel 4 WRITE_ADDR register

uint32_t CH4_AL1_TRANS_COUNT_TRIG

(read-write) Alias for channel 4 TRANS_COUNT register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH4_AL2_CTRL

(read-write) Alias for channel 4 CTRL register

uint32_t CH4_AL2_TRANS_COUNT

(read-write) Alias for channel 4 TRANS_COUNT register

uint32_t CH4_AL2_READ_ADDR

(read-write) Alias for channel 4 READ_ADDR register

uint32_t CH4_AL2_WRITE_ADDR_TRIG

(read-write) Alias for channel 4 WRITE_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH4_AL3_CTRL

(read-write) Alias for channel 4 CTRL register

uint32_t CH4_AL3_WRITE_ADDR

(read-write) Alias for channel 4 WRITE_ADDR register

uint32_t CH4_AL3_TRANS_COUNT

(read-write) Alias for channel 4 TRANS_COUNT register

uint32_t CH4_AL3_READ_ADDR_TRIG

(read-write) Alias for channel 4 READ_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH5_READ_ADDR

(read-write) DMA Channel 5 Read Address pointer

This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

uint32_t CH5_WRITE_ADDR

(read-write) DMA Channel 5 Write Address pointer

This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

uint32_t CH5_TRANS_COUNT

(read-write) DMA Channel 5 Transfer Count

Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).

When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.

Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.

The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

uint32_t CH5_CTRL_TRIG

(read-write) DMA Channel 5 Control and Status

uint32_t CH5_AL1_CTRL

(read-write) Alias for channel 5 CTRL register

uint32_t CH5_AL1_READ_ADDR

(read-write) Alias for channel 5 READ_ADDR register

uint32_t CH5_AL1_WRITE_ADDR

(read-write) Alias for channel 5 WRITE_ADDR register

uint32_t CH5_AL1_TRANS_COUNT_TRIG

(read-write) Alias for channel 5 TRANS_COUNT register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH5_AL2_CTRL

(read-write) Alias for channel 5 CTRL register

uint32_t CH5_AL2_TRANS_COUNT

(read-write) Alias for channel 5 TRANS_COUNT register

uint32_t CH5_AL2_READ_ADDR

(read-write) Alias for channel 5 READ_ADDR register

uint32_t CH5_AL2_WRITE_ADDR_TRIG

(read-write) Alias for channel 5 WRITE_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH5_AL3_CTRL

(read-write) Alias for channel 5 CTRL register

uint32_t CH5_AL3_WRITE_ADDR

(read-write) Alias for channel 5 WRITE_ADDR register

uint32_t CH5_AL3_TRANS_COUNT

(read-write) Alias for channel 5 TRANS_COUNT register

uint32_t CH5_AL3_READ_ADDR_TRIG

(read-write) Alias for channel 5 READ_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH6_READ_ADDR

(read-write) DMA Channel 6 Read Address pointer

This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

uint32_t CH6_WRITE_ADDR

(read-write) DMA Channel 6 Write Address pointer

This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

uint32_t CH6_TRANS_COUNT

(read-write) DMA Channel 6 Transfer Count

Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).

When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.

Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.

The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

uint32_t CH6_CTRL_TRIG

(read-write) DMA Channel 6 Control and Status

uint32_t CH6_AL1_CTRL

(read-write) Alias for channel 6 CTRL register

uint32_t CH6_AL1_READ_ADDR

(read-write) Alias for channel 6 READ_ADDR register

uint32_t CH6_AL1_WRITE_ADDR

(read-write) Alias for channel 6 WRITE_ADDR register

uint32_t CH6_AL1_TRANS_COUNT_TRIG

(read-write) Alias for channel 6 TRANS_COUNT register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH6_AL2_CTRL

(read-write) Alias for channel 6 CTRL register

uint32_t CH6_AL2_TRANS_COUNT

(read-write) Alias for channel 6 TRANS_COUNT register

uint32_t CH6_AL2_READ_ADDR

(read-write) Alias for channel 6 READ_ADDR register

uint32_t CH6_AL2_WRITE_ADDR_TRIG

(read-write) Alias for channel 6 WRITE_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH6_AL3_CTRL

(read-write) Alias for channel 6 CTRL register

uint32_t CH6_AL3_WRITE_ADDR

(read-write) Alias for channel 6 WRITE_ADDR register

uint32_t CH6_AL3_TRANS_COUNT

(read-write) Alias for channel 6 TRANS_COUNT register

uint32_t CH6_AL3_READ_ADDR_TRIG

(read-write) Alias for channel 6 READ_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH7_READ_ADDR

(read-write) DMA Channel 7 Read Address pointer

This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

uint32_t CH7_WRITE_ADDR

(read-write) DMA Channel 7 Write Address pointer

This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

uint32_t CH7_TRANS_COUNT

(read-write) DMA Channel 7 Transfer Count

Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).

When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.

Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.

The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

uint32_t CH7_CTRL_TRIG

(read-write) DMA Channel 7 Control and Status

uint32_t CH7_AL1_CTRL

(read-write) Alias for channel 7 CTRL register

uint32_t CH7_AL1_READ_ADDR

(read-write) Alias for channel 7 READ_ADDR register

uint32_t CH7_AL1_WRITE_ADDR

(read-write) Alias for channel 7 WRITE_ADDR register

uint32_t CH7_AL1_TRANS_COUNT_TRIG

(read-write) Alias for channel 7 TRANS_COUNT register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH7_AL2_CTRL

(read-write) Alias for channel 7 CTRL register

uint32_t CH7_AL2_TRANS_COUNT

(read-write) Alias for channel 7 TRANS_COUNT register

uint32_t CH7_AL2_READ_ADDR

(read-write) Alias for channel 7 READ_ADDR register

uint32_t CH7_AL2_WRITE_ADDR_TRIG

(read-write) Alias for channel 7 WRITE_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH7_AL3_CTRL

(read-write) Alias for channel 7 CTRL register

uint32_t CH7_AL3_WRITE_ADDR

(read-write) Alias for channel 7 WRITE_ADDR register

uint32_t CH7_AL3_TRANS_COUNT

(read-write) Alias for channel 7 TRANS_COUNT register

uint32_t CH7_AL3_READ_ADDR_TRIG

(read-write) Alias for channel 7 READ_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH8_READ_ADDR

(read-write) DMA Channel 8 Read Address pointer

This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

uint32_t CH8_WRITE_ADDR

(read-write) DMA Channel 8 Write Address pointer

This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

uint32_t CH8_TRANS_COUNT

(read-write) DMA Channel 8 Transfer Count

Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).

When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.

Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.

The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

uint32_t CH8_CTRL_TRIG

(read-write) DMA Channel 8 Control and Status

uint32_t CH8_AL1_CTRL

(read-write) Alias for channel 8 CTRL register

uint32_t CH8_AL1_READ_ADDR

(read-write) Alias for channel 8 READ_ADDR register

uint32_t CH8_AL1_WRITE_ADDR

(read-write) Alias for channel 8 WRITE_ADDR register

uint32_t CH8_AL1_TRANS_COUNT_TRIG

(read-write) Alias for channel 8 TRANS_COUNT register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH8_AL2_CTRL

(read-write) Alias for channel 8 CTRL register

uint32_t CH8_AL2_TRANS_COUNT

(read-write) Alias for channel 8 TRANS_COUNT register

uint32_t CH8_AL2_READ_ADDR

(read-write) Alias for channel 8 READ_ADDR register

uint32_t CH8_AL2_WRITE_ADDR_TRIG

(read-write) Alias for channel 8 WRITE_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH8_AL3_CTRL

(read-write) Alias for channel 8 CTRL register

uint32_t CH8_AL3_WRITE_ADDR

(read-write) Alias for channel 8 WRITE_ADDR register

uint32_t CH8_AL3_TRANS_COUNT

(read-write) Alias for channel 8 TRANS_COUNT register

uint32_t CH8_AL3_READ_ADDR_TRIG

(read-write) Alias for channel 8 READ_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH9_READ_ADDR

(read-write) DMA Channel 9 Read Address pointer

This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

uint32_t CH9_WRITE_ADDR

(read-write) DMA Channel 9 Write Address pointer

This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

uint32_t CH9_TRANS_COUNT

(read-write) DMA Channel 9 Transfer Count

Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).

When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.

Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.

The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

uint32_t CH9_CTRL_TRIG

(read-write) DMA Channel 9 Control and Status

uint32_t CH9_AL1_CTRL

(read-write) Alias for channel 9 CTRL register

uint32_t CH9_AL1_READ_ADDR

(read-write) Alias for channel 9 READ_ADDR register

uint32_t CH9_AL1_WRITE_ADDR

(read-write) Alias for channel 9 WRITE_ADDR register

uint32_t CH9_AL1_TRANS_COUNT_TRIG

(read-write) Alias for channel 9 TRANS_COUNT register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH9_AL2_CTRL

(read-write) Alias for channel 9 CTRL register

uint32_t CH9_AL2_TRANS_COUNT

(read-write) Alias for channel 9 TRANS_COUNT register

uint32_t CH9_AL2_READ_ADDR

(read-write) Alias for channel 9 READ_ADDR register

uint32_t CH9_AL2_WRITE_ADDR_TRIG

(read-write) Alias for channel 9 WRITE_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH9_AL3_CTRL

(read-write) Alias for channel 9 CTRL register

uint32_t CH9_AL3_WRITE_ADDR

(read-write) Alias for channel 9 WRITE_ADDR register

uint32_t CH9_AL3_TRANS_COUNT

(read-write) Alias for channel 9 TRANS_COUNT register

uint32_t CH9_AL3_READ_ADDR_TRIG

(read-write) Alias for channel 9 READ_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH10_READ_ADDR

(read-write) DMA Channel 10 Read Address pointer

This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

uint32_t CH10_WRITE_ADDR

(read-write) DMA Channel 10 Write Address pointer

This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

uint32_t CH10_TRANS_COUNT

(read-write) DMA Channel 10 Transfer Count

Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).

When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.

Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.

The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

uint32_t CH10_CTRL_TRIG

(read-write) DMA Channel 10 Control and Status

uint32_t CH10_AL1_CTRL

(read-write) Alias for channel 10 CTRL register

uint32_t CH10_AL1_READ_ADDR

(read-write) Alias for channel 10 READ_ADDR register

uint32_t CH10_AL1_WRITE_ADDR

(read-write) Alias for channel 10 WRITE_ADDR register

uint32_t CH10_AL1_TRANS_COUNT_TRIG

(read-write) Alias for channel 10 TRANS_COUNT register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH10_AL2_CTRL

(read-write) Alias for channel 10 CTRL register

uint32_t CH10_AL2_TRANS_COUNT

(read-write) Alias for channel 10 TRANS_COUNT register

uint32_t CH10_AL2_READ_ADDR

(read-write) Alias for channel 10 READ_ADDR register

uint32_t CH10_AL2_WRITE_ADDR_TRIG

(read-write) Alias for channel 10 WRITE_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH10_AL3_CTRL

(read-write) Alias for channel 10 CTRL register

uint32_t CH10_AL3_WRITE_ADDR

(read-write) Alias for channel 10 WRITE_ADDR register

uint32_t CH10_AL3_TRANS_COUNT

(read-write) Alias for channel 10 TRANS_COUNT register

uint32_t CH10_AL3_READ_ADDR_TRIG

(read-write) Alias for channel 10 READ_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH11_READ_ADDR

(read-write) DMA Channel 11 Read Address pointer

This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

uint32_t CH11_WRITE_ADDR

(read-write) DMA Channel 11 Write Address pointer

This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

uint32_t CH11_TRANS_COUNT

(read-write) DMA Channel 11 Transfer Count

Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).

When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.

Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.

The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

uint32_t CH11_CTRL_TRIG

(read-write) DMA Channel 11 Control and Status

uint32_t CH11_AL1_CTRL

(read-write) Alias for channel 11 CTRL register

uint32_t CH11_AL1_READ_ADDR

(read-write) Alias for channel 11 READ_ADDR register

uint32_t CH11_AL1_WRITE_ADDR

(read-write) Alias for channel 11 WRITE_ADDR register

uint32_t CH11_AL1_TRANS_COUNT_TRIG

(read-write) Alias for channel 11 TRANS_COUNT register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH11_AL2_CTRL

(read-write) Alias for channel 11 CTRL register

uint32_t CH11_AL2_TRANS_COUNT

(read-write) Alias for channel 11 TRANS_COUNT register

uint32_t CH11_AL2_READ_ADDR

(read-write) Alias for channel 11 READ_ADDR register

uint32_t CH11_AL2_WRITE_ADDR_TRIG

(read-write) Alias for channel 11 WRITE_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

uint32_t CH11_AL3_CTRL

(read-write) Alias for channel 11 CTRL register

uint32_t CH11_AL3_WRITE_ADDR

(read-write) Alias for channel 11 WRITE_ADDR register

uint32_t CH11_AL3_TRANS_COUNT

(read-write) Alias for channel 11 TRANS_COUNT register

uint32_t CH11_AL3_READ_ADDR_TRIG

(read-write) Alias for channel 11 READ_ADDR register

This is a trigger register (0xc). Writing a nonzero value will

reload the channel counter and start the channel.

const uint32_t reserved_padding0[reserved_padding0_length] = {}

uint32_t INTR

(read-write) Interrupt Status (raw)

uint32_t INTE0

(read-write) Interrupt Enables for IRQ 0

uint32_t INTF0

(read-write) Force Interrupts

uint32_t INTS0

(read-write) Interrupt Status for IRQ 0

const uint32_t reserved_padding1 = {}

uint32_t INTE1

(read-write) Interrupt Enables for IRQ 1

uint32_t INTF1

(read-write) Force Interrupts for IRQ 1

uint32_t INTS1

(read-write) Interrupt Status (masked) for IRQ 1

uint32_t TIMER0

(read-write) Pacing (X/Y) Fractional Timer

The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

uint32_t TIMER1

(read-write) Pacing (X/Y) Fractional Timer

The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

uint32_t TIMER2

(read-write) Pacing (X/Y) Fractional Timer

The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

uint32_t TIMER3

(read-write) Pacing (X/Y) Fractional Timer

The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

uint32_t MULTI_CHAN_TRIGGER

(read-write) Trigger one or more channels simultaneously

uint32_t SNIFF_CTRL

(read-write) Sniffer Control

uint32_t SNIFF_DATA

(read-write) Data accumulator for sniff hardware

Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.

const uint32_t reserved_padding2 = {}

const uint32_t FIFO_LEVELS = {}

(read-only) Debug RAF, WAF, TDF levels

uint32_t CHAN_ABORT

(read-write) Abort an in-progress transfer sequence on one or more channels

const uint32_t N_CHANNELS = {}

(read-only) The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.

const uint32_t reserved_padding3[reserved_padding3_length] = {}

uint32_t CH0_DBG_CTDREQ

(read-write) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

uint32_t CH0_DBG_TCR

(read-write) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

const uint32_t reserved_padding4[reserved_padding4_length] = {}

uint32_t CH1_DBG_CTDREQ

(read-write) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

uint32_t CH1_DBG_TCR

(read-write) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

const uint32_t reserved_padding5[reserved_padding5_length] = {}

uint32_t CH2_DBG_CTDREQ

(read-write) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

uint32_t CH2_DBG_TCR

(read-write) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

const uint32_t reserved_padding6[reserved_padding6_length] = {}

uint32_t CH3_DBG_CTDREQ

(read-write) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

uint32_t CH3_DBG_TCR

(read-write) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

const uint32_t reserved_padding7[reserved_padding7_length] = {}

uint32_t CH4_DBG_CTDREQ

(read-write) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

uint32_t CH4_DBG_TCR

(read-write) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

const uint32_t reserved_padding8[reserved_padding8_length] = {}

uint32_t CH5_DBG_CTDREQ

(read-write) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

uint32_t CH5_DBG_TCR

(read-write) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

const uint32_t reserved_padding9[reserved_padding9_length] = {}

uint32_t CH6_DBG_CTDREQ

(read-write) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

uint32_t CH6_DBG_TCR

(read-write) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

const uint32_t reserved_padding10[reserved_padding10_length] = {}

uint32_t CH7_DBG_CTDREQ

(read-write) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

uint32_t CH7_DBG_TCR

(read-write) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

const uint32_t reserved_padding11[reserved_padding11_length] = {}

uint32_t CH8_DBG_CTDREQ

(read-write) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

uint32_t CH8_DBG_TCR

(read-write) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

const uint32_t reserved_padding12[reserved_padding12_length] = {}

uint32_t CH9_DBG_CTDREQ

(read-write) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

uint32_t CH9_DBG_TCR

(read-write) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

const uint32_t reserved_padding13[reserved_padding13_length] = {}

uint32_t CH10_DBG_CTDREQ

(read-write) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

uint32_t CH10_DBG_TCR

(read-write) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

const uint32_t reserved_padding14[reserved_padding14_length] = {}

uint32_t CH11_DBG_CTDREQ

(read-write) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

uint32_t CH11_DBG_TCR

(read-write) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

Public Static Attributes

static constexpr std::size_t size = 2760

dma’s size in bytes.

static constexpr std::size_t reserved_padding0_length = 64

static constexpr std::size_t reserved_padding3_length = 237

static constexpr std::size_t reserved_padding4_length = 14

static constexpr std::size_t reserved_padding5_length = 14

static constexpr std::size_t reserved_padding6_length = 14

static constexpr std::size_t reserved_padding7_length = 14

static constexpr std::size_t reserved_padding8_length = 14

static constexpr std::size_t reserved_padding9_length = 14

static constexpr std::size_t reserved_padding10_length = 14

static constexpr std::size_t reserved_padding11_length = 14

static constexpr std::size_t reserved_padding12_length = 14

static constexpr std::size_t reserved_padding13_length = 14

static constexpr std::size_t reserved_padding14_length = 14