Struct pwm

• Defined in File pwm.h

Struct Documentation

struct pwm

Simple PWM

Public Functions

inline bool get_CH0_CSR_EN() volatile

Get CH0_CSR’s EN bit.

Enable the PWM channel.

inline void set_CH0_CSR_EN() volatile

Set CH0_CSR’s EN bit.

Enable the PWM channel.

inline void clear_CH0_CSR_EN() volatile

Clear CH0_CSR’s EN bit.

Enable the PWM channel.

inline void toggle_CH0_CSR_EN() volatile

Toggle CH0_CSR’s EN bit.

Enable the PWM channel.

inline bool get_CH0_CSR_PH_CORRECT() volatile

Get CH0_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void set_CH0_CSR_PH_CORRECT() volatile

Set CH0_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void clear_CH0_CSR_PH_CORRECT() volatile

Clear CH0_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void toggle_CH0_CSR_PH_CORRECT() volatile

Toggle CH0_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline bool get_CH0_CSR_A_INV() volatile

Get CH0_CSR’s A_INV bit.

Invert output A

inline void set_CH0_CSR_A_INV() volatile

Set CH0_CSR’s A_INV bit.

Invert output A

inline void clear_CH0_CSR_A_INV() volatile

Clear CH0_CSR’s A_INV bit.

Invert output A

inline void toggle_CH0_CSR_A_INV() volatile

Toggle CH0_CSR’s A_INV bit.

Invert output A

inline bool get_CH0_CSR_B_INV() volatile

Get CH0_CSR’s B_INV bit.

Invert output B

inline void set_CH0_CSR_B_INV() volatile

Set CH0_CSR’s B_INV bit.

Invert output B

inline void clear_CH0_CSR_B_INV() volatile

Clear CH0_CSR’s B_INV bit.

Invert output B

inline void toggle_CH0_CSR_B_INV() volatile

Toggle CH0_CSR’s B_INV bit.

Invert output B

inline PWM_CH0_CSR_DIVMODE get_CH0_CSR_DIVMODE() volatile

Get CH0_CSR’s DIVMODE field.

inline void set_CH0_CSR_DIVMODE(PWM_CH0_CSR_DIVMODE value) volatile

Set CH0_CSR’s DIVMODE field.

inline bool get_CH0_CSR_PH_RET() volatile

Get CH0_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void set_CH0_CSR_PH_RET() volatile

Set CH0_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void clear_CH0_CSR_PH_RET() volatile

Clear CH0_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void toggle_CH0_CSR_PH_RET() volatile

Toggle CH0_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline bool get_CH0_CSR_PH_ADV() volatile

Get CH0_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void set_CH0_CSR_PH_ADV() volatile

Set CH0_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void clear_CH0_CSR_PH_ADV() volatile

Clear CH0_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void toggle_CH0_CSR_PH_ADV() volatile

Toggle CH0_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void get_CH0_CSR(bool &EN, bool &PH_CORRECT, bool &A_INV, bool &B_INV, PWM_CH0_CSR_DIVMODE &DIVMODE, bool &PH_RET, bool &PH_ADV) volatile

Get all of CH0_CSR’s bit fields.

(read-write) Control and status register

inline void set_CH0_CSR(bool EN, bool PH_CORRECT, bool A_INV, bool B_INV, PWM_CH0_CSR_DIVMODE DIVMODE, bool PH_RET, bool PH_ADV) volatile

Set all of CH0_CSR’s bit fields.

(read-write) Control and status register

inline uint8_t get_CH0_DIV_FRAC() volatile

Get CH0_DIV’s FRAC field.

inline void set_CH0_DIV_FRAC(uint8_t value) volatile

Set CH0_DIV’s FRAC field.

inline uint8_t get_CH0_DIV_INT() volatile

Get CH0_DIV’s INT field.

inline void set_CH0_DIV_INT(uint8_t value) volatile

Set CH0_DIV’s INT field.

inline void get_CH0_DIV(uint8_t &FRAC, uint8_t &INT) volatile

Get all of CH0_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline void set_CH0_DIV(uint8_t FRAC, uint8_t INT) volatile

Set all of CH0_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline uint16_t get_CH0_CTR_CH0_CTR() volatile

Get CH0_CTR’s CH0_CTR field.

inline void set_CH0_CTR_CH0_CTR(uint16_t value) volatile

Set CH0_CTR’s CH0_CTR field.

inline uint16_t get_CH0_CC_A() volatile

Get CH0_CC’s A field.

inline void set_CH0_CC_A(uint16_t value) volatile

Set CH0_CC’s A field.

inline uint16_t get_CH0_CC_B() volatile

Get CH0_CC’s B field.

inline void set_CH0_CC_B(uint16_t value) volatile

Set CH0_CC’s B field.

inline void get_CH0_CC(uint16_t &A, uint16_t &B) volatile

Get all of CH0_CC’s bit fields.

(read-write) Counter compare values

inline void set_CH0_CC(uint16_t A, uint16_t B) volatile

Set all of CH0_CC’s bit fields.

(read-write) Counter compare values

inline uint16_t get_CH0_TOP_CH0_TOP() volatile

Get CH0_TOP’s CH0_TOP field.

inline void set_CH0_TOP_CH0_TOP(uint16_t value) volatile

Set CH0_TOP’s CH0_TOP field.

inline bool get_CH1_CSR_EN() volatile

Get CH1_CSR’s EN bit.

Enable the PWM channel.

inline void set_CH1_CSR_EN() volatile

Set CH1_CSR’s EN bit.

Enable the PWM channel.

inline void clear_CH1_CSR_EN() volatile

Clear CH1_CSR’s EN bit.

Enable the PWM channel.

inline void toggle_CH1_CSR_EN() volatile

Toggle CH1_CSR’s EN bit.

Enable the PWM channel.

inline bool get_CH1_CSR_PH_CORRECT() volatile

Get CH1_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void set_CH1_CSR_PH_CORRECT() volatile

Set CH1_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void clear_CH1_CSR_PH_CORRECT() volatile

Clear CH1_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void toggle_CH1_CSR_PH_CORRECT() volatile

Toggle CH1_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline bool get_CH1_CSR_A_INV() volatile

Get CH1_CSR’s A_INV bit.

Invert output A

inline void set_CH1_CSR_A_INV() volatile

Set CH1_CSR’s A_INV bit.

Invert output A

inline void clear_CH1_CSR_A_INV() volatile

Clear CH1_CSR’s A_INV bit.

Invert output A

inline void toggle_CH1_CSR_A_INV() volatile

Toggle CH1_CSR’s A_INV bit.

Invert output A

inline bool get_CH1_CSR_B_INV() volatile

Get CH1_CSR’s B_INV bit.

Invert output B

inline void set_CH1_CSR_B_INV() volatile

Set CH1_CSR’s B_INV bit.

Invert output B

inline void clear_CH1_CSR_B_INV() volatile

Clear CH1_CSR’s B_INV bit.

Invert output B

inline void toggle_CH1_CSR_B_INV() volatile

Toggle CH1_CSR’s B_INV bit.

Invert output B

inline PWM_CH1_CSR_DIVMODE get_CH1_CSR_DIVMODE() volatile

Get CH1_CSR’s DIVMODE field.

inline void set_CH1_CSR_DIVMODE(PWM_CH1_CSR_DIVMODE value) volatile

Set CH1_CSR’s DIVMODE field.

inline bool get_CH1_CSR_PH_RET() volatile

Get CH1_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void set_CH1_CSR_PH_RET() volatile

Set CH1_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void clear_CH1_CSR_PH_RET() volatile

Clear CH1_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void toggle_CH1_CSR_PH_RET() volatile

Toggle CH1_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline bool get_CH1_CSR_PH_ADV() volatile

Get CH1_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void set_CH1_CSR_PH_ADV() volatile

Set CH1_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void clear_CH1_CSR_PH_ADV() volatile

Clear CH1_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void toggle_CH1_CSR_PH_ADV() volatile

Toggle CH1_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void get_CH1_CSR(bool &EN, bool &PH_CORRECT, bool &A_INV, bool &B_INV, PWM_CH1_CSR_DIVMODE &DIVMODE, bool &PH_RET, bool &PH_ADV) volatile

Get all of CH1_CSR’s bit fields.

(read-write) Control and status register

inline void set_CH1_CSR(bool EN, bool PH_CORRECT, bool A_INV, bool B_INV, PWM_CH1_CSR_DIVMODE DIVMODE, bool PH_RET, bool PH_ADV) volatile

Set all of CH1_CSR’s bit fields.

(read-write) Control and status register

inline uint8_t get_CH1_DIV_FRAC() volatile

Get CH1_DIV’s FRAC field.

inline void set_CH1_DIV_FRAC(uint8_t value) volatile

Set CH1_DIV’s FRAC field.

inline uint8_t get_CH1_DIV_INT() volatile

Get CH1_DIV’s INT field.

inline void set_CH1_DIV_INT(uint8_t value) volatile

Set CH1_DIV’s INT field.

inline void get_CH1_DIV(uint8_t &FRAC, uint8_t &INT) volatile

Get all of CH1_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline void set_CH1_DIV(uint8_t FRAC, uint8_t INT) volatile

Set all of CH1_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline uint16_t get_CH1_CTR_CH1_CTR() volatile

Get CH1_CTR’s CH1_CTR field.

inline void set_CH1_CTR_CH1_CTR(uint16_t value) volatile

Set CH1_CTR’s CH1_CTR field.

inline uint16_t get_CH1_CC_A() volatile

Get CH1_CC’s A field.

inline void set_CH1_CC_A(uint16_t value) volatile

Set CH1_CC’s A field.

inline uint16_t get_CH1_CC_B() volatile

Get CH1_CC’s B field.

inline void set_CH1_CC_B(uint16_t value) volatile

Set CH1_CC’s B field.

inline void get_CH1_CC(uint16_t &A, uint16_t &B) volatile

Get all of CH1_CC’s bit fields.

(read-write) Counter compare values

inline void set_CH1_CC(uint16_t A, uint16_t B) volatile

Set all of CH1_CC’s bit fields.

(read-write) Counter compare values

inline uint16_t get_CH1_TOP_CH1_TOP() volatile

Get CH1_TOP’s CH1_TOP field.

inline void set_CH1_TOP_CH1_TOP(uint16_t value) volatile

Set CH1_TOP’s CH1_TOP field.

inline bool get_CH2_CSR_EN() volatile

Get CH2_CSR’s EN bit.

Enable the PWM channel.

inline void set_CH2_CSR_EN() volatile

Set CH2_CSR’s EN bit.

Enable the PWM channel.

inline void clear_CH2_CSR_EN() volatile

Clear CH2_CSR’s EN bit.

Enable the PWM channel.

inline void toggle_CH2_CSR_EN() volatile

Toggle CH2_CSR’s EN bit.

Enable the PWM channel.

inline bool get_CH2_CSR_PH_CORRECT() volatile

Get CH2_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void set_CH2_CSR_PH_CORRECT() volatile

Set CH2_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void clear_CH2_CSR_PH_CORRECT() volatile

Clear CH2_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void toggle_CH2_CSR_PH_CORRECT() volatile

Toggle CH2_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline bool get_CH2_CSR_A_INV() volatile

Get CH2_CSR’s A_INV bit.

Invert output A

inline void set_CH2_CSR_A_INV() volatile

Set CH2_CSR’s A_INV bit.

Invert output A

inline void clear_CH2_CSR_A_INV() volatile

Clear CH2_CSR’s A_INV bit.

Invert output A

inline void toggle_CH2_CSR_A_INV() volatile

Toggle CH2_CSR’s A_INV bit.

Invert output A

inline bool get_CH2_CSR_B_INV() volatile

Get CH2_CSR’s B_INV bit.

Invert output B

inline void set_CH2_CSR_B_INV() volatile

Set CH2_CSR’s B_INV bit.

Invert output B

inline void clear_CH2_CSR_B_INV() volatile

Clear CH2_CSR’s B_INV bit.

Invert output B

inline void toggle_CH2_CSR_B_INV() volatile

Toggle CH2_CSR’s B_INV bit.

Invert output B

inline PWM_CH2_CSR_DIVMODE get_CH2_CSR_DIVMODE() volatile

Get CH2_CSR’s DIVMODE field.

inline void set_CH2_CSR_DIVMODE(PWM_CH2_CSR_DIVMODE value) volatile

Set CH2_CSR’s DIVMODE field.

inline bool get_CH2_CSR_PH_RET() volatile

Get CH2_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void set_CH2_CSR_PH_RET() volatile

Set CH2_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void clear_CH2_CSR_PH_RET() volatile

Clear CH2_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void toggle_CH2_CSR_PH_RET() volatile

Toggle CH2_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline bool get_CH2_CSR_PH_ADV() volatile

Get CH2_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void set_CH2_CSR_PH_ADV() volatile

Set CH2_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void clear_CH2_CSR_PH_ADV() volatile

Clear CH2_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void toggle_CH2_CSR_PH_ADV() volatile

Toggle CH2_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void get_CH2_CSR(bool &EN, bool &PH_CORRECT, bool &A_INV, bool &B_INV, PWM_CH2_CSR_DIVMODE &DIVMODE, bool &PH_RET, bool &PH_ADV) volatile

Get all of CH2_CSR’s bit fields.

(read-write) Control and status register

inline void set_CH2_CSR(bool EN, bool PH_CORRECT, bool A_INV, bool B_INV, PWM_CH2_CSR_DIVMODE DIVMODE, bool PH_RET, bool PH_ADV) volatile

Set all of CH2_CSR’s bit fields.

(read-write) Control and status register

inline uint8_t get_CH2_DIV_FRAC() volatile

Get CH2_DIV’s FRAC field.

inline void set_CH2_DIV_FRAC(uint8_t value) volatile

Set CH2_DIV’s FRAC field.

inline uint8_t get_CH2_DIV_INT() volatile

Get CH2_DIV’s INT field.

inline void set_CH2_DIV_INT(uint8_t value) volatile

Set CH2_DIV’s INT field.

inline void get_CH2_DIV(uint8_t &FRAC, uint8_t &INT) volatile

Get all of CH2_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline void set_CH2_DIV(uint8_t FRAC, uint8_t INT) volatile

Set all of CH2_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline uint16_t get_CH2_CTR_CH2_CTR() volatile

Get CH2_CTR’s CH2_CTR field.

inline void set_CH2_CTR_CH2_CTR(uint16_t value) volatile

Set CH2_CTR’s CH2_CTR field.

inline uint16_t get_CH2_CC_A() volatile

Get CH2_CC’s A field.

inline void set_CH2_CC_A(uint16_t value) volatile

Set CH2_CC’s A field.

inline uint16_t get_CH2_CC_B() volatile

Get CH2_CC’s B field.

inline void set_CH2_CC_B(uint16_t value) volatile

Set CH2_CC’s B field.

inline void get_CH2_CC(uint16_t &A, uint16_t &B) volatile

Get all of CH2_CC’s bit fields.

(read-write) Counter compare values

inline void set_CH2_CC(uint16_t A, uint16_t B) volatile

Set all of CH2_CC’s bit fields.

(read-write) Counter compare values

inline uint16_t get_CH2_TOP_CH2_TOP() volatile

Get CH2_TOP’s CH2_TOP field.

inline void set_CH2_TOP_CH2_TOP(uint16_t value) volatile

Set CH2_TOP’s CH2_TOP field.

inline bool get_CH3_CSR_EN() volatile

Get CH3_CSR’s EN bit.

Enable the PWM channel.

inline void set_CH3_CSR_EN() volatile

Set CH3_CSR’s EN bit.

Enable the PWM channel.

inline void clear_CH3_CSR_EN() volatile

Clear CH3_CSR’s EN bit.

Enable the PWM channel.

inline void toggle_CH3_CSR_EN() volatile

Toggle CH3_CSR’s EN bit.

Enable the PWM channel.

inline bool get_CH3_CSR_PH_CORRECT() volatile

Get CH3_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void set_CH3_CSR_PH_CORRECT() volatile

Set CH3_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void clear_CH3_CSR_PH_CORRECT() volatile

Clear CH3_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void toggle_CH3_CSR_PH_CORRECT() volatile

Toggle CH3_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline bool get_CH3_CSR_A_INV() volatile

Get CH3_CSR’s A_INV bit.

Invert output A

inline void set_CH3_CSR_A_INV() volatile

Set CH3_CSR’s A_INV bit.

Invert output A

inline void clear_CH3_CSR_A_INV() volatile

Clear CH3_CSR’s A_INV bit.

Invert output A

inline void toggle_CH3_CSR_A_INV() volatile

Toggle CH3_CSR’s A_INV bit.

Invert output A

inline bool get_CH3_CSR_B_INV() volatile

Get CH3_CSR’s B_INV bit.

Invert output B

inline void set_CH3_CSR_B_INV() volatile

Set CH3_CSR’s B_INV bit.

Invert output B

inline void clear_CH3_CSR_B_INV() volatile

Clear CH3_CSR’s B_INV bit.

Invert output B

inline void toggle_CH3_CSR_B_INV() volatile

Toggle CH3_CSR’s B_INV bit.

Invert output B

inline PWM_CH3_CSR_DIVMODE get_CH3_CSR_DIVMODE() volatile

Get CH3_CSR’s DIVMODE field.

inline void set_CH3_CSR_DIVMODE(PWM_CH3_CSR_DIVMODE value) volatile

Set CH3_CSR’s DIVMODE field.

inline bool get_CH3_CSR_PH_RET() volatile

Get CH3_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void set_CH3_CSR_PH_RET() volatile

Set CH3_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void clear_CH3_CSR_PH_RET() volatile

Clear CH3_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void toggle_CH3_CSR_PH_RET() volatile

Toggle CH3_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline bool get_CH3_CSR_PH_ADV() volatile

Get CH3_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void set_CH3_CSR_PH_ADV() volatile

Set CH3_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void clear_CH3_CSR_PH_ADV() volatile

Clear CH3_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void toggle_CH3_CSR_PH_ADV() volatile

Toggle CH3_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void get_CH3_CSR(bool &EN, bool &PH_CORRECT, bool &A_INV, bool &B_INV, PWM_CH3_CSR_DIVMODE &DIVMODE, bool &PH_RET, bool &PH_ADV) volatile

Get all of CH3_CSR’s bit fields.

(read-write) Control and status register

inline void set_CH3_CSR(bool EN, bool PH_CORRECT, bool A_INV, bool B_INV, PWM_CH3_CSR_DIVMODE DIVMODE, bool PH_RET, bool PH_ADV) volatile

Set all of CH3_CSR’s bit fields.

(read-write) Control and status register

inline uint8_t get_CH3_DIV_FRAC() volatile

Get CH3_DIV’s FRAC field.

inline void set_CH3_DIV_FRAC(uint8_t value) volatile

Set CH3_DIV’s FRAC field.

inline uint8_t get_CH3_DIV_INT() volatile

Get CH3_DIV’s INT field.

inline void set_CH3_DIV_INT(uint8_t value) volatile

Set CH3_DIV’s INT field.

inline void get_CH3_DIV(uint8_t &FRAC, uint8_t &INT) volatile

Get all of CH3_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline void set_CH3_DIV(uint8_t FRAC, uint8_t INT) volatile

Set all of CH3_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline uint16_t get_CH3_CTR_CH3_CTR() volatile

Get CH3_CTR’s CH3_CTR field.

inline void set_CH3_CTR_CH3_CTR(uint16_t value) volatile

Set CH3_CTR’s CH3_CTR field.

inline uint16_t get_CH3_CC_A() volatile

Get CH3_CC’s A field.

inline void set_CH3_CC_A(uint16_t value) volatile

Set CH3_CC’s A field.

inline uint16_t get_CH3_CC_B() volatile

Get CH3_CC’s B field.

inline void set_CH3_CC_B(uint16_t value) volatile

Set CH3_CC’s B field.

inline void get_CH3_CC(uint16_t &A, uint16_t &B) volatile

Get all of CH3_CC’s bit fields.

(read-write) Counter compare values

inline void set_CH3_CC(uint16_t A, uint16_t B) volatile

Set all of CH3_CC’s bit fields.

(read-write) Counter compare values

inline uint16_t get_CH3_TOP_CH3_TOP() volatile

Get CH3_TOP’s CH3_TOP field.

inline void set_CH3_TOP_CH3_TOP(uint16_t value) volatile

Set CH3_TOP’s CH3_TOP field.

inline bool get_CH4_CSR_EN() volatile

Get CH4_CSR’s EN bit.

Enable the PWM channel.

inline void set_CH4_CSR_EN() volatile

Set CH4_CSR’s EN bit.

Enable the PWM channel.

inline void clear_CH4_CSR_EN() volatile

Clear CH4_CSR’s EN bit.

Enable the PWM channel.

inline void toggle_CH4_CSR_EN() volatile

Toggle CH4_CSR’s EN bit.

Enable the PWM channel.

inline bool get_CH4_CSR_PH_CORRECT() volatile

Get CH4_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void set_CH4_CSR_PH_CORRECT() volatile

Set CH4_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void clear_CH4_CSR_PH_CORRECT() volatile

Clear CH4_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void toggle_CH4_CSR_PH_CORRECT() volatile

Toggle CH4_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline bool get_CH4_CSR_A_INV() volatile

Get CH4_CSR’s A_INV bit.

Invert output A

inline void set_CH4_CSR_A_INV() volatile

Set CH4_CSR’s A_INV bit.

Invert output A

inline void clear_CH4_CSR_A_INV() volatile

Clear CH4_CSR’s A_INV bit.

Invert output A

inline void toggle_CH4_CSR_A_INV() volatile

Toggle CH4_CSR’s A_INV bit.

Invert output A

inline bool get_CH4_CSR_B_INV() volatile

Get CH4_CSR’s B_INV bit.

Invert output B

inline void set_CH4_CSR_B_INV() volatile

Set CH4_CSR’s B_INV bit.

Invert output B

inline void clear_CH4_CSR_B_INV() volatile

Clear CH4_CSR’s B_INV bit.

Invert output B

inline void toggle_CH4_CSR_B_INV() volatile

Toggle CH4_CSR’s B_INV bit.

Invert output B

inline PWM_CH4_CSR_DIVMODE get_CH4_CSR_DIVMODE() volatile

Get CH4_CSR’s DIVMODE field.

inline void set_CH4_CSR_DIVMODE(PWM_CH4_CSR_DIVMODE value) volatile

Set CH4_CSR’s DIVMODE field.

inline bool get_CH4_CSR_PH_RET() volatile

Get CH4_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void set_CH4_CSR_PH_RET() volatile

Set CH4_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void clear_CH4_CSR_PH_RET() volatile

Clear CH4_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void toggle_CH4_CSR_PH_RET() volatile

Toggle CH4_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline bool get_CH4_CSR_PH_ADV() volatile

Get CH4_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void set_CH4_CSR_PH_ADV() volatile

Set CH4_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void clear_CH4_CSR_PH_ADV() volatile

Clear CH4_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void toggle_CH4_CSR_PH_ADV() volatile

Toggle CH4_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void get_CH4_CSR(bool &EN, bool &PH_CORRECT, bool &A_INV, bool &B_INV, PWM_CH4_CSR_DIVMODE &DIVMODE, bool &PH_RET, bool &PH_ADV) volatile

Get all of CH4_CSR’s bit fields.

(read-write) Control and status register

inline void set_CH4_CSR(bool EN, bool PH_CORRECT, bool A_INV, bool B_INV, PWM_CH4_CSR_DIVMODE DIVMODE, bool PH_RET, bool PH_ADV) volatile

Set all of CH4_CSR’s bit fields.

(read-write) Control and status register

inline uint8_t get_CH4_DIV_FRAC() volatile

Get CH4_DIV’s FRAC field.

inline void set_CH4_DIV_FRAC(uint8_t value) volatile

Set CH4_DIV’s FRAC field.

inline uint8_t get_CH4_DIV_INT() volatile

Get CH4_DIV’s INT field.

inline void set_CH4_DIV_INT(uint8_t value) volatile

Set CH4_DIV’s INT field.

inline void get_CH4_DIV(uint8_t &FRAC, uint8_t &INT) volatile

Get all of CH4_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline void set_CH4_DIV(uint8_t FRAC, uint8_t INT) volatile

Set all of CH4_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline uint16_t get_CH4_CTR_CH4_CTR() volatile

Get CH4_CTR’s CH4_CTR field.

inline void set_CH4_CTR_CH4_CTR(uint16_t value) volatile

Set CH4_CTR’s CH4_CTR field.

inline uint16_t get_CH4_CC_A() volatile

Get CH4_CC’s A field.

inline void set_CH4_CC_A(uint16_t value) volatile

Set CH4_CC’s A field.

inline uint16_t get_CH4_CC_B() volatile

Get CH4_CC’s B field.

inline void set_CH4_CC_B(uint16_t value) volatile

Set CH4_CC’s B field.

inline void get_CH4_CC(uint16_t &A, uint16_t &B) volatile

Get all of CH4_CC’s bit fields.

(read-write) Counter compare values

inline void set_CH4_CC(uint16_t A, uint16_t B) volatile

Set all of CH4_CC’s bit fields.

(read-write) Counter compare values

inline uint16_t get_CH4_TOP_CH4_TOP() volatile

Get CH4_TOP’s CH4_TOP field.

inline void set_CH4_TOP_CH4_TOP(uint16_t value) volatile

Set CH4_TOP’s CH4_TOP field.

inline bool get_CH5_CSR_EN() volatile

Get CH5_CSR’s EN bit.

Enable the PWM channel.

inline void set_CH5_CSR_EN() volatile

Set CH5_CSR’s EN bit.

Enable the PWM channel.

inline void clear_CH5_CSR_EN() volatile

Clear CH5_CSR’s EN bit.

Enable the PWM channel.

inline void toggle_CH5_CSR_EN() volatile

Toggle CH5_CSR’s EN bit.

Enable the PWM channel.

inline bool get_CH5_CSR_PH_CORRECT() volatile

Get CH5_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void set_CH5_CSR_PH_CORRECT() volatile

Set CH5_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void clear_CH5_CSR_PH_CORRECT() volatile

Clear CH5_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void toggle_CH5_CSR_PH_CORRECT() volatile

Toggle CH5_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline bool get_CH5_CSR_A_INV() volatile

Get CH5_CSR’s A_INV bit.

Invert output A

inline void set_CH5_CSR_A_INV() volatile

Set CH5_CSR’s A_INV bit.

Invert output A

inline void clear_CH5_CSR_A_INV() volatile

Clear CH5_CSR’s A_INV bit.

Invert output A

inline void toggle_CH5_CSR_A_INV() volatile

Toggle CH5_CSR’s A_INV bit.

Invert output A

inline bool get_CH5_CSR_B_INV() volatile

Get CH5_CSR’s B_INV bit.

Invert output B

inline void set_CH5_CSR_B_INV() volatile

Set CH5_CSR’s B_INV bit.

Invert output B

inline void clear_CH5_CSR_B_INV() volatile

Clear CH5_CSR’s B_INV bit.

Invert output B

inline void toggle_CH5_CSR_B_INV() volatile

Toggle CH5_CSR’s B_INV bit.

Invert output B

inline PWM_CH5_CSR_DIVMODE get_CH5_CSR_DIVMODE() volatile

Get CH5_CSR’s DIVMODE field.

inline void set_CH5_CSR_DIVMODE(PWM_CH5_CSR_DIVMODE value) volatile

Set CH5_CSR’s DIVMODE field.

inline bool get_CH5_CSR_PH_RET() volatile

Get CH5_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void set_CH5_CSR_PH_RET() volatile

Set CH5_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void clear_CH5_CSR_PH_RET() volatile

Clear CH5_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void toggle_CH5_CSR_PH_RET() volatile

Toggle CH5_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline bool get_CH5_CSR_PH_ADV() volatile

Get CH5_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void set_CH5_CSR_PH_ADV() volatile

Set CH5_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void clear_CH5_CSR_PH_ADV() volatile

Clear CH5_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void toggle_CH5_CSR_PH_ADV() volatile

Toggle CH5_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void get_CH5_CSR(bool &EN, bool &PH_CORRECT, bool &A_INV, bool &B_INV, PWM_CH5_CSR_DIVMODE &DIVMODE, bool &PH_RET, bool &PH_ADV) volatile

Get all of CH5_CSR’s bit fields.

(read-write) Control and status register

inline void set_CH5_CSR(bool EN, bool PH_CORRECT, bool A_INV, bool B_INV, PWM_CH5_CSR_DIVMODE DIVMODE, bool PH_RET, bool PH_ADV) volatile

Set all of CH5_CSR’s bit fields.

(read-write) Control and status register

inline uint8_t get_CH5_DIV_FRAC() volatile

Get CH5_DIV’s FRAC field.

inline void set_CH5_DIV_FRAC(uint8_t value) volatile

Set CH5_DIV’s FRAC field.

inline uint8_t get_CH5_DIV_INT() volatile

Get CH5_DIV’s INT field.

inline void set_CH5_DIV_INT(uint8_t value) volatile

Set CH5_DIV’s INT field.

inline void get_CH5_DIV(uint8_t &FRAC, uint8_t &INT) volatile

Get all of CH5_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline void set_CH5_DIV(uint8_t FRAC, uint8_t INT) volatile

Set all of CH5_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline uint16_t get_CH5_CTR_CH5_CTR() volatile

Get CH5_CTR’s CH5_CTR field.

inline void set_CH5_CTR_CH5_CTR(uint16_t value) volatile

Set CH5_CTR’s CH5_CTR field.

inline uint16_t get_CH5_CC_A() volatile

Get CH5_CC’s A field.

inline void set_CH5_CC_A(uint16_t value) volatile

Set CH5_CC’s A field.

inline uint16_t get_CH5_CC_B() volatile

Get CH5_CC’s B field.

inline void set_CH5_CC_B(uint16_t value) volatile

Set CH5_CC’s B field.

inline void get_CH5_CC(uint16_t &A, uint16_t &B) volatile

Get all of CH5_CC’s bit fields.

(read-write) Counter compare values

inline void set_CH5_CC(uint16_t A, uint16_t B) volatile

Set all of CH5_CC’s bit fields.

(read-write) Counter compare values

inline uint16_t get_CH5_TOP_CH5_TOP() volatile

Get CH5_TOP’s CH5_TOP field.

inline void set_CH5_TOP_CH5_TOP(uint16_t value) volatile

Set CH5_TOP’s CH5_TOP field.

inline bool get_CH6_CSR_EN() volatile

Get CH6_CSR’s EN bit.

Enable the PWM channel.

inline void set_CH6_CSR_EN() volatile

Set CH6_CSR’s EN bit.

Enable the PWM channel.

inline void clear_CH6_CSR_EN() volatile

Clear CH6_CSR’s EN bit.

Enable the PWM channel.

inline void toggle_CH6_CSR_EN() volatile

Toggle CH6_CSR’s EN bit.

Enable the PWM channel.

inline bool get_CH6_CSR_PH_CORRECT() volatile

Get CH6_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void set_CH6_CSR_PH_CORRECT() volatile

Set CH6_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void clear_CH6_CSR_PH_CORRECT() volatile

Clear CH6_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void toggle_CH6_CSR_PH_CORRECT() volatile

Toggle CH6_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline bool get_CH6_CSR_A_INV() volatile

Get CH6_CSR’s A_INV bit.

Invert output A

inline void set_CH6_CSR_A_INV() volatile

Set CH6_CSR’s A_INV bit.

Invert output A

inline void clear_CH6_CSR_A_INV() volatile

Clear CH6_CSR’s A_INV bit.

Invert output A

inline void toggle_CH6_CSR_A_INV() volatile

Toggle CH6_CSR’s A_INV bit.

Invert output A

inline bool get_CH6_CSR_B_INV() volatile

Get CH6_CSR’s B_INV bit.

Invert output B

inline void set_CH6_CSR_B_INV() volatile

Set CH6_CSR’s B_INV bit.

Invert output B

inline void clear_CH6_CSR_B_INV() volatile

Clear CH6_CSR’s B_INV bit.

Invert output B

inline void toggle_CH6_CSR_B_INV() volatile

Toggle CH6_CSR’s B_INV bit.

Invert output B

inline PWM_CH6_CSR_DIVMODE get_CH6_CSR_DIVMODE() volatile

Get CH6_CSR’s DIVMODE field.

inline void set_CH6_CSR_DIVMODE(PWM_CH6_CSR_DIVMODE value) volatile

Set CH6_CSR’s DIVMODE field.

inline bool get_CH6_CSR_PH_RET() volatile

Get CH6_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void set_CH6_CSR_PH_RET() volatile

Set CH6_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void clear_CH6_CSR_PH_RET() volatile

Clear CH6_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void toggle_CH6_CSR_PH_RET() volatile

Toggle CH6_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline bool get_CH6_CSR_PH_ADV() volatile

Get CH6_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void set_CH6_CSR_PH_ADV() volatile

Set CH6_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void clear_CH6_CSR_PH_ADV() volatile

Clear CH6_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void toggle_CH6_CSR_PH_ADV() volatile

Toggle CH6_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void get_CH6_CSR(bool &EN, bool &PH_CORRECT, bool &A_INV, bool &B_INV, PWM_CH6_CSR_DIVMODE &DIVMODE, bool &PH_RET, bool &PH_ADV) volatile

Get all of CH6_CSR’s bit fields.

(read-write) Control and status register

inline void set_CH6_CSR(bool EN, bool PH_CORRECT, bool A_INV, bool B_INV, PWM_CH6_CSR_DIVMODE DIVMODE, bool PH_RET, bool PH_ADV) volatile

Set all of CH6_CSR’s bit fields.

(read-write) Control and status register

inline uint8_t get_CH6_DIV_FRAC() volatile

Get CH6_DIV’s FRAC field.

inline void set_CH6_DIV_FRAC(uint8_t value) volatile

Set CH6_DIV’s FRAC field.

inline uint8_t get_CH6_DIV_INT() volatile

Get CH6_DIV’s INT field.

inline void set_CH6_DIV_INT(uint8_t value) volatile

Set CH6_DIV’s INT field.

inline void get_CH6_DIV(uint8_t &FRAC, uint8_t &INT) volatile

Get all of CH6_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline void set_CH6_DIV(uint8_t FRAC, uint8_t INT) volatile

Set all of CH6_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline uint16_t get_CH6_CTR_CH6_CTR() volatile

Get CH6_CTR’s CH6_CTR field.

inline void set_CH6_CTR_CH6_CTR(uint16_t value) volatile

Set CH6_CTR’s CH6_CTR field.

inline uint16_t get_CH6_CC_A() volatile

Get CH6_CC’s A field.

inline void set_CH6_CC_A(uint16_t value) volatile

Set CH6_CC’s A field.

inline uint16_t get_CH6_CC_B() volatile

Get CH6_CC’s B field.

inline void set_CH6_CC_B(uint16_t value) volatile

Set CH6_CC’s B field.

inline void get_CH6_CC(uint16_t &A, uint16_t &B) volatile

Get all of CH6_CC’s bit fields.

(read-write) Counter compare values

inline void set_CH6_CC(uint16_t A, uint16_t B) volatile

Set all of CH6_CC’s bit fields.

(read-write) Counter compare values

inline uint16_t get_CH6_TOP_CH6_TOP() volatile

Get CH6_TOP’s CH6_TOP field.

inline void set_CH6_TOP_CH6_TOP(uint16_t value) volatile

Set CH6_TOP’s CH6_TOP field.

inline bool get_CH7_CSR_EN() volatile

Get CH7_CSR’s EN bit.

Enable the PWM channel.

inline void set_CH7_CSR_EN() volatile

Set CH7_CSR’s EN bit.

Enable the PWM channel.

inline void clear_CH7_CSR_EN() volatile

Clear CH7_CSR’s EN bit.

Enable the PWM channel.

inline void toggle_CH7_CSR_EN() volatile

Toggle CH7_CSR’s EN bit.

Enable the PWM channel.

inline bool get_CH7_CSR_PH_CORRECT() volatile

Get CH7_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void set_CH7_CSR_PH_CORRECT() volatile

Set CH7_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void clear_CH7_CSR_PH_CORRECT() volatile

Clear CH7_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline void toggle_CH7_CSR_PH_CORRECT() volatile

Toggle CH7_CSR’s PH_CORRECT bit.

1: Enable phase-correct modulation. 0: Trailing-edge

inline bool get_CH7_CSR_A_INV() volatile

Get CH7_CSR’s A_INV bit.

Invert output A

inline void set_CH7_CSR_A_INV() volatile

Set CH7_CSR’s A_INV bit.

Invert output A

inline void clear_CH7_CSR_A_INV() volatile

Clear CH7_CSR’s A_INV bit.

Invert output A

inline void toggle_CH7_CSR_A_INV() volatile

Toggle CH7_CSR’s A_INV bit.

Invert output A

inline bool get_CH7_CSR_B_INV() volatile

Get CH7_CSR’s B_INV bit.

Invert output B

inline void set_CH7_CSR_B_INV() volatile

Set CH7_CSR’s B_INV bit.

Invert output B

inline void clear_CH7_CSR_B_INV() volatile

Clear CH7_CSR’s B_INV bit.

Invert output B

inline void toggle_CH7_CSR_B_INV() volatile

Toggle CH7_CSR’s B_INV bit.

Invert output B

inline PWM_CH7_CSR_DIVMODE get_CH7_CSR_DIVMODE() volatile

Get CH7_CSR’s DIVMODE field.

inline void set_CH7_CSR_DIVMODE(PWM_CH7_CSR_DIVMODE value) volatile

Set CH7_CSR’s DIVMODE field.

inline bool get_CH7_CSR_PH_RET() volatile

Get CH7_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void set_CH7_CSR_PH_RET() volatile

Set CH7_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void clear_CH7_CSR_PH_RET() volatile

Clear CH7_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline void toggle_CH7_CSR_PH_RET() volatile

Toggle CH7_CSR’s PH_RET bit.

Retard the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running.

inline bool get_CH7_CSR_PH_ADV() volatile

Get CH7_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void set_CH7_CSR_PH_ADV() volatile

Set CH7_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void clear_CH7_CSR_PH_ADV() volatile

Clear CH7_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void toggle_CH7_CSR_PH_ADV() volatile

Toggle CH7_CSR’s PH_ADV bit.

Advance the phase of the counter by 1 count, while it is running.

Self-clearing. Write a 1, and poll until low. Counter must be running

at less than full speed (div_int + div_frac / 16 > 1)

inline void get_CH7_CSR(bool &EN, bool &PH_CORRECT, bool &A_INV, bool &B_INV, PWM_CH7_CSR_DIVMODE &DIVMODE, bool &PH_RET, bool &PH_ADV) volatile

Get all of CH7_CSR’s bit fields.

(read-write) Control and status register

inline void set_CH7_CSR(bool EN, bool PH_CORRECT, bool A_INV, bool B_INV, PWM_CH7_CSR_DIVMODE DIVMODE, bool PH_RET, bool PH_ADV) volatile

Set all of CH7_CSR’s bit fields.

(read-write) Control and status register

inline uint8_t get_CH7_DIV_FRAC() volatile

Get CH7_DIV’s FRAC field.

inline void set_CH7_DIV_FRAC(uint8_t value) volatile

Set CH7_DIV’s FRAC field.

inline uint8_t get_CH7_DIV_INT() volatile

Get CH7_DIV’s INT field.

inline void set_CH7_DIV_INT(uint8_t value) volatile

Set CH7_DIV’s INT field.

inline void get_CH7_DIV(uint8_t &FRAC, uint8_t &INT) volatile

Get all of CH7_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline void set_CH7_DIV(uint8_t FRAC, uint8_t INT) volatile

Set all of CH7_DIV’s bit fields.

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

inline uint16_t get_CH7_CTR_CH7_CTR() volatile

Get CH7_CTR’s CH7_CTR field.

inline void set_CH7_CTR_CH7_CTR(uint16_t value) volatile

Set CH7_CTR’s CH7_CTR field.

inline uint16_t get_CH7_CC_A() volatile

Get CH7_CC’s A field.

inline void set_CH7_CC_A(uint16_t value) volatile

Set CH7_CC’s A field.

inline uint16_t get_CH7_CC_B() volatile

Get CH7_CC’s B field.

inline void set_CH7_CC_B(uint16_t value) volatile

Set CH7_CC’s B field.

inline void get_CH7_CC(uint16_t &A, uint16_t &B) volatile

Get all of CH7_CC’s bit fields.

(read-write) Counter compare values

inline void set_CH7_CC(uint16_t A, uint16_t B) volatile

Set all of CH7_CC’s bit fields.

(read-write) Counter compare values

inline uint16_t get_CH7_TOP_CH7_TOP() volatile

Get CH7_TOP’s CH7_TOP field.

inline void set_CH7_TOP_CH7_TOP(uint16_t value) volatile

Set CH7_TOP’s CH7_TOP field.

inline bool get_EN_CH0() volatile

Get EN’s CH0 bit.

inline void set_EN_CH0() volatile

Set EN’s CH0 bit.

inline void clear_EN_CH0() volatile

Clear EN’s CH0 bit.

inline void toggle_EN_CH0() volatile

Toggle EN’s CH0 bit.

inline bool get_EN_CH1() volatile

Get EN’s CH1 bit.

inline void set_EN_CH1() volatile

Set EN’s CH1 bit.

inline void clear_EN_CH1() volatile

Clear EN’s CH1 bit.

inline void toggle_EN_CH1() volatile

Toggle EN’s CH1 bit.

inline bool get_EN_CH2() volatile

Get EN’s CH2 bit.

inline void set_EN_CH2() volatile

Set EN’s CH2 bit.

inline void clear_EN_CH2() volatile

Clear EN’s CH2 bit.

inline void toggle_EN_CH2() volatile

Toggle EN’s CH2 bit.

inline bool get_EN_CH3() volatile

Get EN’s CH3 bit.

inline void set_EN_CH3() volatile

Set EN’s CH3 bit.

inline void clear_EN_CH3() volatile

Clear EN’s CH3 bit.

inline void toggle_EN_CH3() volatile

Toggle EN’s CH3 bit.

inline bool get_EN_CH4() volatile

Get EN’s CH4 bit.

inline void set_EN_CH4() volatile

Set EN’s CH4 bit.

inline void clear_EN_CH4() volatile

Clear EN’s CH4 bit.

inline void toggle_EN_CH4() volatile

Toggle EN’s CH4 bit.

inline bool get_EN_CH5() volatile

Get EN’s CH5 bit.

inline void set_EN_CH5() volatile

Set EN’s CH5 bit.

inline void clear_EN_CH5() volatile

Clear EN’s CH5 bit.

inline void toggle_EN_CH5() volatile

Toggle EN’s CH5 bit.

inline bool get_EN_CH6() volatile

Get EN’s CH6 bit.

inline void set_EN_CH6() volatile

Set EN’s CH6 bit.

inline void clear_EN_CH6() volatile

Clear EN’s CH6 bit.

inline void toggle_EN_CH6() volatile

Toggle EN’s CH6 bit.

inline bool get_EN_CH7() volatile

Get EN’s CH7 bit.

inline void set_EN_CH7() volatile

Set EN’s CH7 bit.

inline void clear_EN_CH7() volatile

Clear EN’s CH7 bit.

inline void toggle_EN_CH7() volatile

Toggle EN’s CH7 bit.

inline void get_EN(bool &CH0, bool &CH1, bool &CH2, bool &CH3, bool &CH4, bool &CH5, bool &CH6, bool &CH7) volatile

Get all of EN’s bit fields.

(read-write) This register aliases the CSR_EN bits for all channels.

Writing to this register allows multiple channels to be enabled

or disabled simultaneously, so they can run in perfect sync.

For each channel, there is only one physical EN register bit,

which can be accessed through here or CHx_CSR.

inline void set_EN(bool CH0, bool CH1, bool CH2, bool CH3, bool CH4, bool CH5, bool CH6, bool CH7) volatile

Set all of EN’s bit fields.

(read-write) This register aliases the CSR_EN bits for all channels.

Writing to this register allows multiple channels to be enabled

or disabled simultaneously, so they can run in perfect sync.

For each channel, there is only one physical EN register bit,

which can be accessed through here or CHx_CSR.

inline bool get_INTR_CH0() volatile

Get INTR’s CH0 bit.

inline void set_INTR_CH0() volatile

Set INTR’s CH0 bit.

inline void clear_INTR_CH0() volatile

Clear INTR’s CH0 bit.

inline void toggle_INTR_CH0() volatile

Toggle INTR’s CH0 bit.

inline bool get_INTR_CH1() volatile

Get INTR’s CH1 bit.

inline void set_INTR_CH1() volatile

Set INTR’s CH1 bit.

inline void clear_INTR_CH1() volatile

Clear INTR’s CH1 bit.

inline void toggle_INTR_CH1() volatile

Toggle INTR’s CH1 bit.

inline bool get_INTR_CH2() volatile

Get INTR’s CH2 bit.

inline void set_INTR_CH2() volatile

Set INTR’s CH2 bit.

inline void clear_INTR_CH2() volatile

Clear INTR’s CH2 bit.

inline void toggle_INTR_CH2() volatile

Toggle INTR’s CH2 bit.

inline bool get_INTR_CH3() volatile

Get INTR’s CH3 bit.

inline void set_INTR_CH3() volatile

Set INTR’s CH3 bit.

inline void clear_INTR_CH3() volatile

Clear INTR’s CH3 bit.

inline void toggle_INTR_CH3() volatile

Toggle INTR’s CH3 bit.

inline bool get_INTR_CH4() volatile

Get INTR’s CH4 bit.

inline void set_INTR_CH4() volatile

Set INTR’s CH4 bit.

inline void clear_INTR_CH4() volatile

Clear INTR’s CH4 bit.

inline void toggle_INTR_CH4() volatile

Toggle INTR’s CH4 bit.

inline bool get_INTR_CH5() volatile

Get INTR’s CH5 bit.

inline void set_INTR_CH5() volatile

Set INTR’s CH5 bit.

inline void clear_INTR_CH5() volatile

Clear INTR’s CH5 bit.

inline void toggle_INTR_CH5() volatile

Toggle INTR’s CH5 bit.

inline bool get_INTR_CH6() volatile

Get INTR’s CH6 bit.

inline void set_INTR_CH6() volatile

Set INTR’s CH6 bit.

inline void clear_INTR_CH6() volatile

Clear INTR’s CH6 bit.

inline void toggle_INTR_CH6() volatile

Toggle INTR’s CH6 bit.

inline bool get_INTR_CH7() volatile

Get INTR’s CH7 bit.

inline void set_INTR_CH7() volatile

Set INTR’s CH7 bit.

inline void clear_INTR_CH7() volatile

Clear INTR’s CH7 bit.

inline void toggle_INTR_CH7() volatile

Toggle INTR’s CH7 bit.

inline void get_INTR(bool &CH0, bool &CH1, bool &CH2, bool &CH3, bool &CH4, bool &CH5, bool &CH6, bool &CH7) volatile

Get all of INTR’s bit fields.

(read-write) Raw Interrupts

inline void set_INTR(bool CH0, bool CH1, bool CH2, bool CH3, bool CH4, bool CH5, bool CH6, bool CH7) volatile

Set all of INTR’s bit fields.

(read-write) Raw Interrupts

inline bool get_INTE_CH0() volatile

Get INTE’s CH0 bit.

inline void set_INTE_CH0() volatile

Set INTE’s CH0 bit.

inline void clear_INTE_CH0() volatile

Clear INTE’s CH0 bit.

inline void toggle_INTE_CH0() volatile

Toggle INTE’s CH0 bit.

inline bool get_INTE_CH1() volatile

Get INTE’s CH1 bit.

inline void set_INTE_CH1() volatile

Set INTE’s CH1 bit.

inline void clear_INTE_CH1() volatile

Clear INTE’s CH1 bit.

inline void toggle_INTE_CH1() volatile

Toggle INTE’s CH1 bit.

inline bool get_INTE_CH2() volatile

Get INTE’s CH2 bit.

inline void set_INTE_CH2() volatile

Set INTE’s CH2 bit.

inline void clear_INTE_CH2() volatile

Clear INTE’s CH2 bit.

inline void toggle_INTE_CH2() volatile

Toggle INTE’s CH2 bit.

inline bool get_INTE_CH3() volatile

Get INTE’s CH3 bit.

inline void set_INTE_CH3() volatile

Set INTE’s CH3 bit.

inline void clear_INTE_CH3() volatile

Clear INTE’s CH3 bit.

inline void toggle_INTE_CH3() volatile

Toggle INTE’s CH3 bit.

inline bool get_INTE_CH4() volatile

Get INTE’s CH4 bit.

inline void set_INTE_CH4() volatile

Set INTE’s CH4 bit.

inline void clear_INTE_CH4() volatile

Clear INTE’s CH4 bit.

inline void toggle_INTE_CH4() volatile

Toggle INTE’s CH4 bit.

inline bool get_INTE_CH5() volatile

Get INTE’s CH5 bit.

inline void set_INTE_CH5() volatile

Set INTE’s CH5 bit.

inline void clear_INTE_CH5() volatile

Clear INTE’s CH5 bit.

inline void toggle_INTE_CH5() volatile

Toggle INTE’s CH5 bit.

inline bool get_INTE_CH6() volatile

Get INTE’s CH6 bit.

inline void set_INTE_CH6() volatile

Set INTE’s CH6 bit.

inline void clear_INTE_CH6() volatile

Clear INTE’s CH6 bit.

inline void toggle_INTE_CH6() volatile

Toggle INTE’s CH6 bit.

inline bool get_INTE_CH7() volatile

Get INTE’s CH7 bit.

inline void set_INTE_CH7() volatile

Set INTE’s CH7 bit.

inline void clear_INTE_CH7() volatile

Clear INTE’s CH7 bit.

inline void toggle_INTE_CH7() volatile

Toggle INTE’s CH7 bit.

inline void get_INTE(bool &CH0, bool &CH1, bool &CH2, bool &CH3, bool &CH4, bool &CH5, bool &CH6, bool &CH7) volatile

Get all of INTE’s bit fields.

(read-write) Interrupt Enable

inline void set_INTE(bool CH0, bool CH1, bool CH2, bool CH3, bool CH4, bool CH5, bool CH6, bool CH7) volatile

Set all of INTE’s bit fields.

(read-write) Interrupt Enable

inline bool get_INTF_CH0() volatile

Get INTF’s CH0 bit.

inline void set_INTF_CH0() volatile

Set INTF’s CH0 bit.

inline void clear_INTF_CH0() volatile

Clear INTF’s CH0 bit.

inline void toggle_INTF_CH0() volatile

Toggle INTF’s CH0 bit.

inline bool get_INTF_CH1() volatile

Get INTF’s CH1 bit.

inline void set_INTF_CH1() volatile

Set INTF’s CH1 bit.

inline void clear_INTF_CH1() volatile

Clear INTF’s CH1 bit.

inline void toggle_INTF_CH1() volatile

Toggle INTF’s CH1 bit.

inline bool get_INTF_CH2() volatile

Get INTF’s CH2 bit.

inline void set_INTF_CH2() volatile

Set INTF’s CH2 bit.

inline void clear_INTF_CH2() volatile

Clear INTF’s CH2 bit.

inline void toggle_INTF_CH2() volatile

Toggle INTF’s CH2 bit.

inline bool get_INTF_CH3() volatile

Get INTF’s CH3 bit.

inline void set_INTF_CH3() volatile

Set INTF’s CH3 bit.

inline void clear_INTF_CH3() volatile

Clear INTF’s CH3 bit.

inline void toggle_INTF_CH3() volatile

Toggle INTF’s CH3 bit.

inline bool get_INTF_CH4() volatile

Get INTF’s CH4 bit.

inline void set_INTF_CH4() volatile

Set INTF’s CH4 bit.

inline void clear_INTF_CH4() volatile

Clear INTF’s CH4 bit.

inline void toggle_INTF_CH4() volatile

Toggle INTF’s CH4 bit.

inline bool get_INTF_CH5() volatile

Get INTF’s CH5 bit.

inline void set_INTF_CH5() volatile

Set INTF’s CH5 bit.

inline void clear_INTF_CH5() volatile

Clear INTF’s CH5 bit.

inline void toggle_INTF_CH5() volatile

Toggle INTF’s CH5 bit.

inline bool get_INTF_CH6() volatile

Get INTF’s CH6 bit.

inline void set_INTF_CH6() volatile

Set INTF’s CH6 bit.

inline void clear_INTF_CH6() volatile

Clear INTF’s CH6 bit.

inline void toggle_INTF_CH6() volatile

Toggle INTF’s CH6 bit.

inline bool get_INTF_CH7() volatile

Get INTF’s CH7 bit.

inline void set_INTF_CH7() volatile

Set INTF’s CH7 bit.

inline void clear_INTF_CH7() volatile

Clear INTF’s CH7 bit.

inline void toggle_INTF_CH7() volatile

Toggle INTF’s CH7 bit.

inline void get_INTF(bool &CH0, bool &CH1, bool &CH2, bool &CH3, bool &CH4, bool &CH5, bool &CH6, bool &CH7) volatile

Get all of INTF’s bit fields.

(read-write) Interrupt Force

inline void set_INTF(bool CH0, bool CH1, bool CH2, bool CH3, bool CH4, bool CH5, bool CH6, bool CH7) volatile

Set all of INTF’s bit fields.

(read-write) Interrupt Force

inline bool get_INTS_CH0() volatile

Get INTS’s CH0 bit.

inline bool get_INTS_CH1() volatile

Get INTS’s CH1 bit.

inline bool get_INTS_CH2() volatile

Get INTS’s CH2 bit.

inline bool get_INTS_CH3() volatile

Get INTS’s CH3 bit.

inline bool get_INTS_CH4() volatile

Get INTS’s CH4 bit.

inline bool get_INTS_CH5() volatile

Get INTS’s CH5 bit.

inline bool get_INTS_CH6() volatile

Get INTS’s CH6 bit.

inline bool get_INTS_CH7() volatile

Get INTS’s CH7 bit.

inline void get_INTS(bool &CH0, bool &CH1, bool &CH2, bool &CH3, bool &CH4, bool &CH5, bool &CH6, bool &CH7) volatile

Get all of INTS’s bit fields.

(read-only) Interrupt status after masking & forcing

Public Members

uint32_t CH0_CSR

(read-write) Control and status register

uint32_t CH0_DIV

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

uint32_t CH0_CTR

(read-write) Direct access to the PWM counter

uint32_t CH0_CC

(read-write) Counter compare values

uint32_t CH0_TOP

(read-write) Counter wrap value

uint32_t CH1_CSR

(read-write) Control and status register

uint32_t CH1_DIV

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

uint32_t CH1_CTR

(read-write) Direct access to the PWM counter

uint32_t CH1_CC

(read-write) Counter compare values

uint32_t CH1_TOP

(read-write) Counter wrap value

uint32_t CH2_CSR

(read-write) Control and status register

uint32_t CH2_DIV

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

uint32_t CH2_CTR

(read-write) Direct access to the PWM counter

uint32_t CH2_CC

(read-write) Counter compare values

uint32_t CH2_TOP

(read-write) Counter wrap value

uint32_t CH3_CSR

(read-write) Control and status register

uint32_t CH3_DIV

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

uint32_t CH3_CTR

(read-write) Direct access to the PWM counter

uint32_t CH3_CC

(read-write) Counter compare values

uint32_t CH3_TOP

(read-write) Counter wrap value

uint32_t CH4_CSR

(read-write) Control and status register

uint32_t CH4_DIV

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

uint32_t CH4_CTR

(read-write) Direct access to the PWM counter

uint32_t CH4_CC

(read-write) Counter compare values

uint32_t CH4_TOP

(read-write) Counter wrap value

uint32_t CH5_CSR

(read-write) Control and status register

uint32_t CH5_DIV

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

uint32_t CH5_CTR

(read-write) Direct access to the PWM counter

uint32_t CH5_CC

(read-write) Counter compare values

uint32_t CH5_TOP

(read-write) Counter wrap value

uint32_t CH6_CSR

(read-write) Control and status register

uint32_t CH6_DIV

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

uint32_t CH6_CTR

(read-write) Direct access to the PWM counter

uint32_t CH6_CC

(read-write) Counter compare values

uint32_t CH6_TOP

(read-write) Counter wrap value

uint32_t CH7_CSR

(read-write) Control and status register

uint32_t CH7_DIV

(read-write) INT and FRAC form a fixed-point fractional number.

Counting rate is system clock frequency divided by this number.

Fractional division uses simple 1st-order sigma-delta.

uint32_t CH7_CTR

(read-write) Direct access to the PWM counter

uint32_t CH7_CC

(read-write) Counter compare values

uint32_t CH7_TOP

(read-write) Counter wrap value

uint32_t EN

(read-write) This register aliases the CSR_EN bits for all channels.

Writing to this register allows multiple channels to be enabled

or disabled simultaneously, so they can run in perfect sync.

For each channel, there is only one physical EN register bit,

which can be accessed through here or CHx_CSR.

uint32_t INTR

(read-write) Raw Interrupts

uint32_t INTE

(read-write) Interrupt Enable

uint32_t INTF

(read-write) Interrupt Force

const uint32_t INTS = {}

(read-only) Interrupt status after masking & forcing

Public Static Attributes

static constexpr std::size_t size = 180

pwm’s size in bytes.