Struct xip_ssi#

Defined in File xip_ssi.h

Struct Documentation#

struct xip_ssi#

DW_apb_ssi has the following features:

APB interface - Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.
APB3 and APB4 protocol support.
Scalable APB data bus width - Supports APB data bus widths of 8, 16, and 32 bits.
Serial-master or serial-slave operation - Enables serial communication with serial-master or serial-slave peripheral devices.
Programmable Dual/Quad/Octal SPI support in Master Mode.
Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.
Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.
eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.
DMA Controller Interface - Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.
Independent masking of interrupts - Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.
Multi-master contention detection - Informs the processor of multiple serial-master accesses on the serial bus.
Bypass of meta-stability flip-flops for synchronous clocks - When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.
Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.
Programmable features:
Serial interface operation - Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.
Clock bit-rate - Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.
Data Item size (4 to 32 bits) - Item size of each data transfer under the control of the programmer.
Configured features:
FIFO depth - 16 words deep. The FIFO width is fixed at 32 bits.
1 slave select output.
Hardware slave-select - Dedicated hardware slave-select line.
Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.
Interrupt polarity - active high interrupt lines.
Serial clock polarity - low serial-clock polarity directly after reset.
Serial clock phase - capture on first edge of serial-clock directly after reset.

Public Functions

inline uint8_t get_CTRLR0_DFS() volatile#

Get CTRLR0’s DFS field.

Data frame size

inline void set_CTRLR0_DFS(uint8_t value) volatile#

Set CTRLR0’s DFS field.

Data frame size

inline uint8_t get_CTRLR0_FRF() volatile#

Get CTRLR0’s FRF field.

Frame format

inline void set_CTRLR0_FRF(uint8_t value) volatile#

Set CTRLR0’s FRF field.

Frame format

inline bool get_CTRLR0_SCPH() volatile#

Get CTRLR0’s SCPH bit.

Serial clock phase

inline void set_CTRLR0_SCPH() volatile#

Set CTRLR0’s SCPH bit.

Serial clock phase

inline void clear_CTRLR0_SCPH() volatile#

Clear CTRLR0’s SCPH bit.

Serial clock phase

inline void toggle_CTRLR0_SCPH() volatile#

Toggle CTRLR0’s SCPH bit.

Serial clock phase

inline bool get_CTRLR0_SCPOL() volatile#

Get CTRLR0’s SCPOL bit.

Serial clock polarity

inline void set_CTRLR0_SCPOL() volatile#

Set CTRLR0’s SCPOL bit.

Serial clock polarity

inline void clear_CTRLR0_SCPOL() volatile#

Clear CTRLR0’s SCPOL bit.

Serial clock polarity

inline void toggle_CTRLR0_SCPOL() volatile#

Toggle CTRLR0’s SCPOL bit.

Serial clock polarity

inline XIP_SSI_CTRLR0_TMOD get_CTRLR0_TMOD() volatile#

Get CTRLR0’s TMOD field.

Transfer mode

inline void set_CTRLR0_TMOD(XIP_SSI_CTRLR0_TMOD value) volatile#

Set CTRLR0’s TMOD field.

Transfer mode

inline bool get_CTRLR0_SLV_OE() volatile#

Get CTRLR0’s SLV_OE bit.

Slave output enable

inline void set_CTRLR0_SLV_OE() volatile#

Set CTRLR0’s SLV_OE bit.

Slave output enable

inline void clear_CTRLR0_SLV_OE() volatile#

Clear CTRLR0’s SLV_OE bit.

Slave output enable

inline void toggle_CTRLR0_SLV_OE() volatile#

Toggle CTRLR0’s SLV_OE bit.

Slave output enable

inline bool get_CTRLR0_SRL() volatile#

Get CTRLR0’s SRL bit.

Shift register loop (test mode)

inline void set_CTRLR0_SRL() volatile#

Set CTRLR0’s SRL bit.

Shift register loop (test mode)

inline void clear_CTRLR0_SRL() volatile#

Clear CTRLR0’s SRL bit.

Shift register loop (test mode)

inline void toggle_CTRLR0_SRL() volatile#

Toggle CTRLR0’s SRL bit.

Shift register loop (test mode)

inline uint8_t get_CTRLR0_CFS() volatile#

Get CTRLR0’s CFS field.

Control frame size

Value of n -> n+1 clocks per frame.

inline void set_CTRLR0_CFS(uint8_t value) volatile#

Set CTRLR0’s CFS field.

Control frame size

Value of n -> n+1 clocks per frame.

inline uint8_t get_CTRLR0_DFS_32() volatile#

Get CTRLR0’s DFS_32 field.

Data frame size in 32b transfer mode

Value of n -> n+1 clocks per frame.

inline void set_CTRLR0_DFS_32(uint8_t value) volatile#

Set CTRLR0’s DFS_32 field.

Data frame size in 32b transfer mode

Value of n -> n+1 clocks per frame.

inline XIP_SSI_CTRLR0_SPI_FRF get_CTRLR0_SPI_FRF() volatile#

Get CTRLR0’s SPI_FRF field.

SPI frame format

inline void set_CTRLR0_SPI_FRF(XIP_SSI_CTRLR0_SPI_FRF value) volatile#

Set CTRLR0’s SPI_FRF field.

SPI frame format

inline bool get_CTRLR0_SSTE() volatile#

Get CTRLR0’s SSTE bit.

Slave select toggle enable

inline void set_CTRLR0_SSTE() volatile#

Set CTRLR0’s SSTE bit.

Slave select toggle enable

inline void clear_CTRLR0_SSTE() volatile#

Clear CTRLR0’s SSTE bit.

Slave select toggle enable

inline void toggle_CTRLR0_SSTE() volatile#

Toggle CTRLR0’s SSTE bit.

Slave select toggle enable

inline void get_CTRLR0(uint8_t &DFS, uint8_t &FRF, bool &SCPH, bool &SCPOL, XIP_SSI_CTRLR0_TMOD &TMOD, bool &SLV_OE, bool &SRL, uint8_t &CFS, uint8_t &DFS_32, XIP_SSI_CTRLR0_SPI_FRF &SPI_FRF, bool &SSTE) volatile#

Get all of CTRLR0’s bit fields.

(read-write) Control register 0

inline void set_CTRLR0(uint8_t DFS, uint8_t FRF, bool SCPH, bool SCPOL, XIP_SSI_CTRLR0_TMOD TMOD, bool SLV_OE, bool SRL, uint8_t CFS, uint8_t DFS_32, XIP_SSI_CTRLR0_SPI_FRF SPI_FRF, bool SSTE) volatile#

Set all of CTRLR0’s bit fields.

(read-write) Control register 0

inline uint16_t get_CTRLR1_NDF() volatile#

Get CTRLR1’s NDF field.

Number of data frames

inline void set_CTRLR1_NDF(uint16_t value) volatile#

Set CTRLR1’s NDF field.

Number of data frames

inline bool get_SSIENR_SSI_EN() volatile#

Get SSIENR’s SSI_EN bit.

SSI enable

inline void set_SSIENR_SSI_EN() volatile#

Set SSIENR’s SSI_EN bit.

SSI enable

inline void clear_SSIENR_SSI_EN() volatile#

Clear SSIENR’s SSI_EN bit.

SSI enable

inline void toggle_SSIENR_SSI_EN() volatile#

Toggle SSIENR’s SSI_EN bit.

SSI enable

inline bool get_MWCR_MWMOD() volatile#

Get MWCR’s MWMOD bit.

Microwire transfer mode

inline void set_MWCR_MWMOD() volatile#

Set MWCR’s MWMOD bit.

Microwire transfer mode

inline void clear_MWCR_MWMOD() volatile#

Clear MWCR’s MWMOD bit.

Microwire transfer mode

inline void toggle_MWCR_MWMOD() volatile#

Toggle MWCR’s MWMOD bit.

Microwire transfer mode

inline bool get_MWCR_MDD() volatile#

Get MWCR’s MDD bit.

Microwire control

inline void set_MWCR_MDD() volatile#

Set MWCR’s MDD bit.

Microwire control

inline void clear_MWCR_MDD() volatile#

Clear MWCR’s MDD bit.

Microwire control

inline void toggle_MWCR_MDD() volatile#

Toggle MWCR’s MDD bit.

Microwire control

inline bool get_MWCR_MHS() volatile#

Get MWCR’s MHS bit.

Microwire handshaking

inline void set_MWCR_MHS() volatile#

Set MWCR’s MHS bit.

Microwire handshaking

inline void clear_MWCR_MHS() volatile#

Clear MWCR’s MHS bit.

Microwire handshaking

inline void toggle_MWCR_MHS() volatile#

Toggle MWCR’s MHS bit.

Microwire handshaking

inline void get_MWCR(bool &MWMOD, bool &MDD, bool &MHS) volatile#

Get all of MWCR’s bit fields.

(read-write) Microwire Control

inline void set_MWCR(bool MWMOD, bool MDD, bool MHS) volatile#

Set all of MWCR’s bit fields.

(read-write) Microwire Control

inline bool get_SER_SER() volatile#

Get SER’s SER bit.

For each bit:

0 -> slave not selected

1 -> slave selected

inline void set_SER_SER() volatile#

Set SER’s SER bit.

For each bit:

0 -> slave not selected

1 -> slave selected

inline void clear_SER_SER() volatile#

Clear SER’s SER bit.

For each bit:

0 -> slave not selected

1 -> slave selected

inline void toggle_SER_SER() volatile#

Toggle SER’s SER bit.

For each bit:

0 -> slave not selected

1 -> slave selected

inline uint16_t get_BAUDR_SCKDV() volatile#

Get BAUDR’s SCKDV field.

SSI clock divider

inline void set_BAUDR_SCKDV(uint16_t value) volatile#

Set BAUDR’s SCKDV field.

SSI clock divider

inline uint8_t get_TXFTLR_TFT() volatile#

Get TXFTLR’s TFT field.

Transmit FIFO threshold

inline void set_TXFTLR_TFT(uint8_t value) volatile#

Set TXFTLR’s TFT field.

Transmit FIFO threshold

inline uint8_t get_RXFTLR_RFT() volatile#

Get RXFTLR’s RFT field.

Receive FIFO threshold

inline void set_RXFTLR_RFT(uint8_t value) volatile#

Set RXFTLR’s RFT field.

Receive FIFO threshold

inline uint8_t get_TXFLR_TFTFL() volatile#

Get TXFLR’s TFTFL field.

Transmit FIFO level

inline uint8_t get_RXFLR_RXTFL() volatile#

Get RXFLR’s RXTFL field.

Receive FIFO level

inline bool get_SR_BUSY() volatile#

Get SR’s BUSY bit.

SSI busy flag

inline bool get_SR_TFNF() volatile#

Get SR’s TFNF bit.

Transmit FIFO not full

inline bool get_SR_TFE() volatile#

Get SR’s TFE bit.

Transmit FIFO empty

inline bool get_SR_RFNE() volatile#

Get SR’s RFNE bit.

Receive FIFO not empty

inline bool get_SR_RFF() volatile#

Get SR’s RFF bit.

Receive FIFO full

inline bool get_SR_TXE() volatile#

Get SR’s TXE bit.

Transmission error

inline bool get_SR_DCOL() volatile#

Get SR’s DCOL bit.

Data collision error

inline void get_SR(bool &BUSY, bool &TFNF, bool &TFE, bool &RFNE, bool &RFF, bool &TXE, bool &DCOL) volatile#

Get all of SR’s bit fields.

(read-only) Status register

inline bool get_IMR_TXEIM() volatile#

Get IMR’s TXEIM bit.

Transmit FIFO empty interrupt mask

inline void set_IMR_TXEIM() volatile#

Set IMR’s TXEIM bit.

Transmit FIFO empty interrupt mask

inline void clear_IMR_TXEIM() volatile#

Clear IMR’s TXEIM bit.

Transmit FIFO empty interrupt mask

inline void toggle_IMR_TXEIM() volatile#

Toggle IMR’s TXEIM bit.

Transmit FIFO empty interrupt mask

inline bool get_IMR_TXOIM() volatile#

Get IMR’s TXOIM bit.

Transmit FIFO overflow interrupt mask

inline void set_IMR_TXOIM() volatile#

Set IMR’s TXOIM bit.

Transmit FIFO overflow interrupt mask

inline void clear_IMR_TXOIM() volatile#

Clear IMR’s TXOIM bit.

Transmit FIFO overflow interrupt mask

inline void toggle_IMR_TXOIM() volatile#

Toggle IMR’s TXOIM bit.

Transmit FIFO overflow interrupt mask

inline bool get_IMR_RXUIM() volatile#

Get IMR’s RXUIM bit.

Receive FIFO underflow interrupt mask

inline void set_IMR_RXUIM() volatile#

Set IMR’s RXUIM bit.

Receive FIFO underflow interrupt mask

inline void clear_IMR_RXUIM() volatile#

Clear IMR’s RXUIM bit.

Receive FIFO underflow interrupt mask

inline void toggle_IMR_RXUIM() volatile#

Toggle IMR’s RXUIM bit.

Receive FIFO underflow interrupt mask

inline bool get_IMR_RXOIM() volatile#

Get IMR’s RXOIM bit.

Receive FIFO overflow interrupt mask

inline void set_IMR_RXOIM() volatile#

Set IMR’s RXOIM bit.

Receive FIFO overflow interrupt mask

inline void clear_IMR_RXOIM() volatile#

Clear IMR’s RXOIM bit.

Receive FIFO overflow interrupt mask

inline void toggle_IMR_RXOIM() volatile#

Toggle IMR’s RXOIM bit.

Receive FIFO overflow interrupt mask

inline bool get_IMR_RXFIM() volatile#

Get IMR’s RXFIM bit.

Receive FIFO full interrupt mask

inline void set_IMR_RXFIM() volatile#

Set IMR’s RXFIM bit.

Receive FIFO full interrupt mask

inline void clear_IMR_RXFIM() volatile#

Clear IMR’s RXFIM bit.

Receive FIFO full interrupt mask

inline void toggle_IMR_RXFIM() volatile#

Toggle IMR’s RXFIM bit.

Receive FIFO full interrupt mask

inline bool get_IMR_MSTIM() volatile#

Get IMR’s MSTIM bit.

Multi-master contention interrupt mask

inline void set_IMR_MSTIM() volatile#

Set IMR’s MSTIM bit.

Multi-master contention interrupt mask

inline void clear_IMR_MSTIM() volatile#

Clear IMR’s MSTIM bit.

Multi-master contention interrupt mask

inline void toggle_IMR_MSTIM() volatile#

Toggle IMR’s MSTIM bit.

Multi-master contention interrupt mask

inline void get_IMR(bool &TXEIM, bool &TXOIM, bool &RXUIM, bool &RXOIM, bool &RXFIM, bool &MSTIM) volatile#

Get all of IMR’s bit fields.

(read-write) Interrupt mask

inline void set_IMR(bool TXEIM, bool TXOIM, bool RXUIM, bool RXOIM, bool RXFIM, bool MSTIM) volatile#

Set all of IMR’s bit fields.

(read-write) Interrupt mask

inline bool get_ISR_TXEIS() volatile#

Get ISR’s TXEIS bit.

Transmit FIFO empty interrupt status

inline bool get_ISR_TXOIS() volatile#

Get ISR’s TXOIS bit.

Transmit FIFO overflow interrupt status

inline bool get_ISR_RXUIS() volatile#

Get ISR’s RXUIS bit.

Receive FIFO underflow interrupt status

inline bool get_ISR_RXOIS() volatile#

Get ISR’s RXOIS bit.

Receive FIFO overflow interrupt status

inline bool get_ISR_RXFIS() volatile#

Get ISR’s RXFIS bit.

Receive FIFO full interrupt status

inline bool get_ISR_MSTIS() volatile#

Get ISR’s MSTIS bit.

Multi-master contention interrupt status

inline void get_ISR(bool &TXEIS, bool &TXOIS, bool &RXUIS, bool &RXOIS, bool &RXFIS, bool &MSTIS) volatile#

Get all of ISR’s bit fields.

(read-only) Interrupt status

inline bool get_RISR_TXEIR() volatile#

Get RISR’s TXEIR bit.

Transmit FIFO empty raw interrupt status

inline bool get_RISR_TXOIR() volatile#

Get RISR’s TXOIR bit.

Transmit FIFO overflow raw interrupt status

inline bool get_RISR_RXUIR() volatile#

Get RISR’s RXUIR bit.

Receive FIFO underflow raw interrupt status

inline bool get_RISR_RXOIR() volatile#

Get RISR’s RXOIR bit.

Receive FIFO overflow raw interrupt status

inline bool get_RISR_RXFIR() volatile#

Get RISR’s RXFIR bit.

Receive FIFO full raw interrupt status

inline bool get_RISR_MSTIR() volatile#

Get RISR’s MSTIR bit.

Multi-master contention raw interrupt status

inline void get_RISR(bool &TXEIR, bool &TXOIR, bool &RXUIR, bool &RXOIR, bool &RXFIR, bool &MSTIR) volatile#

Get all of RISR’s bit fields.

(read-only) Raw interrupt status

inline bool get_TXOICR_TXOICR() volatile#

Get TXOICR’s TXOICR bit.

Clear-on-read transmit FIFO overflow interrupt

inline bool get_RXOICR_RXOICR() volatile#

Get RXOICR’s RXOICR bit.

Clear-on-read receive FIFO overflow interrupt

inline bool get_RXUICR_RXUICR() volatile#

Get RXUICR’s RXUICR bit.

Clear-on-read receive FIFO underflow interrupt

inline bool get_MSTICR_MSTICR() volatile#

Get MSTICR’s MSTICR bit.

Clear-on-read multi-master contention interrupt

inline bool get_ICR_ICR() volatile#

Get ICR’s ICR bit.

Clear-on-read all active interrupts

inline bool get_DMACR_RDMAE() volatile#

Get DMACR’s RDMAE bit.

Receive DMA enable

inline void set_DMACR_RDMAE() volatile#

Set DMACR’s RDMAE bit.

Receive DMA enable

inline void clear_DMACR_RDMAE() volatile#

Clear DMACR’s RDMAE bit.

Receive DMA enable

inline void toggle_DMACR_RDMAE() volatile#

Toggle DMACR’s RDMAE bit.

Receive DMA enable

inline bool get_DMACR_TDMAE() volatile#

Get DMACR’s TDMAE bit.

Transmit DMA enable

inline void set_DMACR_TDMAE() volatile#

Set DMACR’s TDMAE bit.

Transmit DMA enable

inline void clear_DMACR_TDMAE() volatile#

Clear DMACR’s TDMAE bit.

Transmit DMA enable

inline void toggle_DMACR_TDMAE() volatile#

Toggle DMACR’s TDMAE bit.

Transmit DMA enable

inline void get_DMACR(bool &RDMAE, bool &TDMAE) volatile#

Get all of DMACR’s bit fields.

(read-write) DMA control

inline void set_DMACR(bool RDMAE, bool TDMAE) volatile#

Set all of DMACR’s bit fields.

(read-write) DMA control

inline uint8_t get_DMATDLR_DMATDL() volatile#

Get DMATDLR’s DMATDL field.

Transmit data watermark level

inline void set_DMATDLR_DMATDL(uint8_t value) volatile#

Set DMATDLR’s DMATDL field.

Transmit data watermark level

inline uint8_t get_DMARDLR_DMARDL() volatile#

Get DMARDLR’s DMARDL field.

Receive data watermark level (DMARDLR+1)

inline void set_DMARDLR_DMARDL(uint8_t value) volatile#

Set DMARDLR’s DMARDL field.

Receive data watermark level (DMARDLR+1)

inline uint32_t get_IDR_IDCODE() volatile#

Get IDR’s IDCODE field.

Peripheral dentification code

inline uint32_t get_SSI_VERSION_ID_SSI_COMP_VERSION() volatile#

Get SSI_VERSION_ID’s SSI_COMP_VERSION field.

SNPS component version (format X.YY)

inline uint32_t get_DR0_DR() volatile#

Get DR0’s DR field.

First data register of 36

inline void set_DR0_DR(uint32_t value) volatile#

Set DR0’s DR field.

First data register of 36

inline uint8_t get_RX_SAMPLE_DLY_RSD() volatile#

Get RX_SAMPLE_DLY’s RSD field.

RXD sample delay (in SCLK cycles)

inline void set_RX_SAMPLE_DLY_RSD(uint8_t value) volatile#

Set RX_SAMPLE_DLY’s RSD field.

RXD sample delay (in SCLK cycles)

inline XIP_SSI_SPI_CTRLR0_TRANS_TYPE get_SPI_CTRLR0_TRANS_TYPE() volatile#

Get SPI_CTRLR0’s TRANS_TYPE field.

Address and instruction transfer format

inline void set_SPI_CTRLR0_TRANS_TYPE(XIP_SSI_SPI_CTRLR0_TRANS_TYPE value) volatile#

Set SPI_CTRLR0’s TRANS_TYPE field.

Address and instruction transfer format

inline uint8_t get_SPI_CTRLR0_ADDR_L() volatile#

Get SPI_CTRLR0’s ADDR_L field.

Address length (0b-60b in 4b increments)

inline void set_SPI_CTRLR0_ADDR_L(uint8_t value) volatile#

Set SPI_CTRLR0’s ADDR_L field.

Address length (0b-60b in 4b increments)

inline XIP_SSI_SPI_CTRLR0_INST_L get_SPI_CTRLR0_INST_L() volatile#

Get SPI_CTRLR0’s INST_L field.

Instruction length (0/4/8/16b)

inline void set_SPI_CTRLR0_INST_L(XIP_SSI_SPI_CTRLR0_INST_L value) volatile#

Set SPI_CTRLR0’s INST_L field.

Instruction length (0/4/8/16b)

inline uint8_t get_SPI_CTRLR0_WAIT_CYCLES() volatile#

Get SPI_CTRLR0’s WAIT_CYCLES field.

Wait cycles between control frame transmit and data reception (in SCLK cycles)

inline void set_SPI_CTRLR0_WAIT_CYCLES(uint8_t value) volatile#

Set SPI_CTRLR0’s WAIT_CYCLES field.

Wait cycles between control frame transmit and data reception (in SCLK cycles)

inline bool get_SPI_CTRLR0_SPI_DDR_EN() volatile#

Get SPI_CTRLR0’s SPI_DDR_EN bit.

SPI DDR transfer enable

inline void set_SPI_CTRLR0_SPI_DDR_EN() volatile#

Set SPI_CTRLR0’s SPI_DDR_EN bit.

SPI DDR transfer enable

inline void clear_SPI_CTRLR0_SPI_DDR_EN() volatile#

Clear SPI_CTRLR0’s SPI_DDR_EN bit.

SPI DDR transfer enable

inline void toggle_SPI_CTRLR0_SPI_DDR_EN() volatile#

Toggle SPI_CTRLR0’s SPI_DDR_EN bit.

SPI DDR transfer enable

inline bool get_SPI_CTRLR0_INST_DDR_EN() volatile#

Get SPI_CTRLR0’s INST_DDR_EN bit.

Instruction DDR transfer enable

inline void set_SPI_CTRLR0_INST_DDR_EN() volatile#

Set SPI_CTRLR0’s INST_DDR_EN bit.

Instruction DDR transfer enable

inline void clear_SPI_CTRLR0_INST_DDR_EN() volatile#

Clear SPI_CTRLR0’s INST_DDR_EN bit.

Instruction DDR transfer enable

inline void toggle_SPI_CTRLR0_INST_DDR_EN() volatile#

Toggle SPI_CTRLR0’s INST_DDR_EN bit.

Instruction DDR transfer enable

inline bool get_SPI_CTRLR0_SPI_RXDS_EN() volatile#

Get SPI_CTRLR0’s SPI_RXDS_EN bit.

Read data strobe enable

inline void set_SPI_CTRLR0_SPI_RXDS_EN() volatile#

Set SPI_CTRLR0’s SPI_RXDS_EN bit.

Read data strobe enable

inline void clear_SPI_CTRLR0_SPI_RXDS_EN() volatile#

Clear SPI_CTRLR0’s SPI_RXDS_EN bit.

Read data strobe enable

inline void toggle_SPI_CTRLR0_SPI_RXDS_EN() volatile#

Toggle SPI_CTRLR0’s SPI_RXDS_EN bit.

Read data strobe enable

inline uint8_t get_SPI_CTRLR0_XIP_CMD() volatile#

Get SPI_CTRLR0’s XIP_CMD field.

SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)

inline void set_SPI_CTRLR0_XIP_CMD(uint8_t value) volatile#

Set SPI_CTRLR0’s XIP_CMD field.

SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)

inline void get_SPI_CTRLR0(XIP_SSI_SPI_CTRLR0_TRANS_TYPE &TRANS_TYPE, uint8_t &ADDR_L, XIP_SSI_SPI_CTRLR0_INST_L &INST_L, uint8_t &WAIT_CYCLES, bool &SPI_DDR_EN, bool &INST_DDR_EN, bool &SPI_RXDS_EN, uint8_t &XIP_CMD) volatile#

Get all of SPI_CTRLR0’s bit fields.

(read-write) SPI control

inline void set_SPI_CTRLR0(XIP_SSI_SPI_CTRLR0_TRANS_TYPE TRANS_TYPE, uint8_t ADDR_L, XIP_SSI_SPI_CTRLR0_INST_L INST_L, uint8_t WAIT_CYCLES, bool SPI_DDR_EN, bool INST_DDR_EN, bool SPI_RXDS_EN, uint8_t XIP_CMD) volatile#

Set all of SPI_CTRLR0’s bit fields.

(read-write) SPI control

inline uint8_t get_TXD_DRIVE_EDGE_TDE() volatile#

Get TXD_DRIVE_EDGE’s TDE field.

TXD drive edge

inline void set_TXD_DRIVE_EDGE_TDE(uint8_t value) volatile#

Set TXD_DRIVE_EDGE’s TDE field.

TXD drive edge

Public Members

uint32_t CTRLR0#: (read-write) Control register 0

uint32_t CTRLR1#: (read-write) Master Control register 1

uint32_t SSIENR#: (read-write) SSI Enable

uint32_t MWCR#: (read-write) Microwire Control

uint32_t SER#: (read-write) Slave enable

uint32_t BAUDR#: (read-write) Baud rate

uint32_t TXFTLR#: (read-write) TX FIFO threshold level

uint32_t RXFTLR#: (read-write) RX FIFO threshold level

const uint32_t TXFLR = {}#: (read-only) TX FIFO level

const uint32_t RXFLR = {}#: (read-only) RX FIFO level

const uint32_t SR = {}#: (read-only) Status register

uint32_t IMR#: (read-write) Interrupt mask

const uint32_t ISR = {}#: (read-only) Interrupt status

const uint32_t RISR = {}#: (read-only) Raw interrupt status

const uint32_t TXOICR = {}#: (read-only) TX FIFO overflow interrupt clear

const uint32_t RXOICR = {}#: (read-only) RX FIFO overflow interrupt clear

const uint32_t RXUICR = {}#: (read-only) RX FIFO underflow interrupt clear

const uint32_t MSTICR = {}#: (read-only) Multi-master interrupt clear

const uint32_t ICR = {}#: (read-only) Interrupt clear

uint32_t DMACR#: (read-write) DMA control

uint32_t DMATDLR#: (read-write) DMA TX data level

uint32_t DMARDLR#: (read-write) DMA RX data level

const uint32_t IDR = {}#: (read-only) Identification register

const uint32_t SSI_VERSION_ID = {}#: (read-only) Version ID

uint32_t DR0#: (read-write) Data Register 0 (of 36)

const uint32_t reserved_padding0[reserved_padding0_length] = {}#

uint32_t RX_SAMPLE_DLY#: (read-write) RX sample delay

uint32_t SPI_CTRLR0#: (read-write) SPI control

uint32_t TXD_DRIVE_EDGE#: (read-write) TX drive edge

Public Static Attributes

static constexpr std::size_t size = 252#: xip_ssi’s size in bytes.

static constexpr std::size_t reserved_padding0_length = 35#

Struct xip_ssi

Contents

Struct xip_ssi#

Struct Documentation#