Program Listing for File sio.h

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#pragma once

#include "../ifgen/common.h"

namespace RP2040
{

struct [[gnu::packed]] sio
{
    /* Constant attributes. */
    static constexpr std::size_t size = 384;
    /* Fields. */
    uint32_t CPUID;
    const uint32_t GPIO_IN = {};
    const uint32_t GPIO_HI_IN =
        {};
    const uint32_t reserved_padding0 = {};
    uint32_t GPIO_OUT;
    uint32_t GPIO_OUT_SET;
    uint32_t GPIO_OUT_CLR;
    uint32_t GPIO_OUT_XOR;
    uint32_t GPIO_OE;
    uint32_t GPIO_OE_SET;
    uint32_t GPIO_OE_CLR;
    uint32_t GPIO_OE_XOR;
    uint32_t GPIO_HI_OUT;
    uint32_t GPIO_HI_OUT_SET;
    uint32_t GPIO_HI_OUT_CLR;
    uint32_t GPIO_HI_OUT_XOR;
    uint32_t GPIO_HI_OE;
    uint32_t GPIO_HI_OE_SET;
    uint32_t GPIO_HI_OE_CLR;
    uint32_t GPIO_HI_OE_XOR;
    uint32_t FIFO_ST;
    uint32_t FIFO_WR;
    uint32_t FIFO_RD;
    uint32_t SPINLOCK_ST;
    uint32_t DIV_UDIVIDEND;
    uint32_t DIV_UDIVISOR;
    uint32_t DIV_SDIVIDEND;
    uint32_t DIV_SDIVISOR;
    uint32_t DIV_QUOTIENT;
    uint32_t DIV_REMAINDER;
    const uint32_t DIV_CSR =
        {};
    const uint32_t reserved_padding1 = {};
    uint32_t
        INTERP0_ACCUM0;
    uint32_t
        INTERP0_ACCUM1;
    uint32_t INTERP0_BASE0;
    uint32_t INTERP0_BASE1;
    uint32_t INTERP0_BASE2;
    uint32_t INTERP0_POP_LANE0;
    uint32_t INTERP0_POP_LANE1;
    uint32_t INTERP0_POP_FULL;
    uint32_t INTERP0_PEEK_LANE0;
    uint32_t INTERP0_PEEK_LANE1;
    uint32_t INTERP0_PEEK_FULL;
    uint32_t
        INTERP0_CTRL_LANE0;
    uint32_t
        INTERP0_CTRL_LANE1;
    uint32_t INTERP0_ACCUM0_ADD;
    uint32_t INTERP0_ACCUM1_ADD;
    uint32_t INTERP0_BASE_1AND0;
    uint32_t
        INTERP1_ACCUM0;
    uint32_t
        INTERP1_ACCUM1;
    uint32_t INTERP1_BASE0;
    uint32_t INTERP1_BASE1;
    uint32_t INTERP1_BASE2;
    uint32_t INTERP1_POP_LANE0;
    uint32_t INTERP1_POP_LANE1;
    uint32_t INTERP1_POP_FULL;
    uint32_t INTERP1_PEEK_LANE0;
    uint32_t INTERP1_PEEK_LANE1;
    uint32_t INTERP1_PEEK_FULL;
    uint32_t
        INTERP1_CTRL_LANE0;
    uint32_t
        INTERP1_CTRL_LANE1;
    uint32_t INTERP1_ACCUM0_ADD;
    uint32_t INTERP1_ACCUM1_ADD;
    uint32_t INTERP1_BASE_1AND0;
    uint32_t
        SPINLOCK0;
    uint32_t
        SPINLOCK1;
    uint32_t
        SPINLOCK2;
    uint32_t
        SPINLOCK3;
    uint32_t
        SPINLOCK4;
    uint32_t
        SPINLOCK5;
    uint32_t
        SPINLOCK6;
    uint32_t
        SPINLOCK7;
    uint32_t
        SPINLOCK8;
    uint32_t
        SPINLOCK9;
    uint32_t
        SPINLOCK10;
    uint32_t
        SPINLOCK11;
    uint32_t
        SPINLOCK12;
    uint32_t
        SPINLOCK13;
    uint32_t
        SPINLOCK14;
    uint32_t
        SPINLOCK15;
    uint32_t
        SPINLOCK16;
    uint32_t
        SPINLOCK17;
    uint32_t
        SPINLOCK18;
    uint32_t
        SPINLOCK19;
    uint32_t
        SPINLOCK20;
    uint32_t
        SPINLOCK21;
    uint32_t
        SPINLOCK22;
    uint32_t
        SPINLOCK23;
    uint32_t
        SPINLOCK24;
    uint32_t
        SPINLOCK25;
    uint32_t
        SPINLOCK26;
    uint32_t
        SPINLOCK27;
    uint32_t
        SPINLOCK28;
    uint32_t
        SPINLOCK29;
    uint32_t
        SPINLOCK30;
    uint32_t
        SPINLOCK31;
    /* Methods. */

    inline uint32_t get_GPIO_IN_GPIO_IN() volatile
    {
        return (GPIO_IN >> 0u) & 0b111111111111111111111111111111u;
    }

    inline uint8_t get_GPIO_HI_IN_GPIO_HI_IN() volatile
    {
        return (GPIO_HI_IN >> 0u) & 0b111111u;
    }

    inline uint32_t get_GPIO_OUT_GPIO_OUT() volatile
    {
        return (GPIO_OUT >> 0u) & 0b111111111111111111111111111111u;
    }

    inline void set_GPIO_OUT_GPIO_OUT(uint32_t value) volatile
    {
        uint32_t curr = GPIO_OUT;

        curr &= ~(0b111111111111111111111111111111u << 0u);
        curr |= (value & 0b111111111111111111111111111111u) << 0u;

        GPIO_OUT = curr;
    }

    inline void set_GPIO_OUT_SET_GPIO_OUT_SET(uint32_t value) volatile
    {
        uint32_t curr = GPIO_OUT_SET;

        curr &= ~(0b111111111111111111111111111111u << 0u);
        curr |= (value & 0b111111111111111111111111111111u) << 0u;

        GPIO_OUT_SET = curr;
    }

    inline void set_GPIO_OUT_CLR_GPIO_OUT_CLR(uint32_t value) volatile
    {
        uint32_t curr = GPIO_OUT_CLR;

        curr &= ~(0b111111111111111111111111111111u << 0u);
        curr |= (value & 0b111111111111111111111111111111u) << 0u;

        GPIO_OUT_CLR = curr;
    }

    inline void set_GPIO_OUT_XOR_GPIO_OUT_XOR(uint32_t value) volatile
    {
        uint32_t curr = GPIO_OUT_XOR;

        curr &= ~(0b111111111111111111111111111111u << 0u);
        curr |= (value & 0b111111111111111111111111111111u) << 0u;

        GPIO_OUT_XOR = curr;
    }

    inline uint32_t get_GPIO_OE_GPIO_OE() volatile
    {
        return (GPIO_OE >> 0u) & 0b111111111111111111111111111111u;
    }

    inline void set_GPIO_OE_GPIO_OE(uint32_t value) volatile
    {
        uint32_t curr = GPIO_OE;

        curr &= ~(0b111111111111111111111111111111u << 0u);
        curr |= (value & 0b111111111111111111111111111111u) << 0u;

        GPIO_OE = curr;
    }

    inline void set_GPIO_OE_SET_GPIO_OE_SET(uint32_t value) volatile
    {
        uint32_t curr = GPIO_OE_SET;

        curr &= ~(0b111111111111111111111111111111u << 0u);
        curr |= (value & 0b111111111111111111111111111111u) << 0u;

        GPIO_OE_SET = curr;
    }

    inline void set_GPIO_OE_CLR_GPIO_OE_CLR(uint32_t value) volatile
    {
        uint32_t curr = GPIO_OE_CLR;

        curr &= ~(0b111111111111111111111111111111u << 0u);
        curr |= (value & 0b111111111111111111111111111111u) << 0u;

        GPIO_OE_CLR = curr;
    }

    inline void set_GPIO_OE_XOR_GPIO_OE_XOR(uint32_t value) volatile
    {
        uint32_t curr = GPIO_OE_XOR;

        curr &= ~(0b111111111111111111111111111111u << 0u);
        curr |= (value & 0b111111111111111111111111111111u) << 0u;

        GPIO_OE_XOR = curr;
    }

    inline uint8_t get_GPIO_HI_OUT_GPIO_HI_OUT() volatile
    {
        return (GPIO_HI_OUT >> 0u) & 0b111111u;
    }

    inline void set_GPIO_HI_OUT_GPIO_HI_OUT(uint8_t value) volatile
    {
        uint32_t curr = GPIO_HI_OUT;

        curr &= ~(0b111111u << 0u);
        curr |= (value & 0b111111u) << 0u;

        GPIO_HI_OUT = curr;
    }

    inline void set_GPIO_HI_OUT_SET_GPIO_HI_OUT_SET(uint8_t value) volatile
    {
        uint32_t curr = GPIO_HI_OUT_SET;

        curr &= ~(0b111111u << 0u);
        curr |= (value & 0b111111u) << 0u;

        GPIO_HI_OUT_SET = curr;
    }

    inline void set_GPIO_HI_OUT_CLR_GPIO_HI_OUT_CLR(uint8_t value) volatile
    {
        uint32_t curr = GPIO_HI_OUT_CLR;

        curr &= ~(0b111111u << 0u);
        curr |= (value & 0b111111u) << 0u;

        GPIO_HI_OUT_CLR = curr;
    }

    inline void set_GPIO_HI_OUT_XOR_GPIO_HI_OUT_XOR(uint8_t value) volatile
    {
        uint32_t curr = GPIO_HI_OUT_XOR;

        curr &= ~(0b111111u << 0u);
        curr |= (value & 0b111111u) << 0u;

        GPIO_HI_OUT_XOR = curr;
    }

    inline uint8_t get_GPIO_HI_OE_GPIO_HI_OE() volatile
    {
        return (GPIO_HI_OE >> 0u) & 0b111111u;
    }

    inline void set_GPIO_HI_OE_GPIO_HI_OE(uint8_t value) volatile
    {
        uint32_t curr = GPIO_HI_OE;

        curr &= ~(0b111111u << 0u);
        curr |= (value & 0b111111u) << 0u;

        GPIO_HI_OE = curr;
    }

    inline void set_GPIO_HI_OE_SET_GPIO_HI_OE_SET(uint8_t value) volatile
    {
        uint32_t curr = GPIO_HI_OE_SET;

        curr &= ~(0b111111u << 0u);
        curr |= (value & 0b111111u) << 0u;

        GPIO_HI_OE_SET = curr;
    }

    inline void set_GPIO_HI_OE_CLR_GPIO_HI_OE_CLR(uint8_t value) volatile
    {
        uint32_t curr = GPIO_HI_OE_CLR;

        curr &= ~(0b111111u << 0u);
        curr |= (value & 0b111111u) << 0u;

        GPIO_HI_OE_CLR = curr;
    }

    inline void set_GPIO_HI_OE_XOR_GPIO_HI_OE_XOR(uint8_t value) volatile
    {
        uint32_t curr = GPIO_HI_OE_XOR;

        curr &= ~(0b111111u << 0u);
        curr |= (value & 0b111111u) << 0u;

        GPIO_HI_OE_XOR = curr;
    }

    inline bool get_FIFO_ST_VLD() volatile
    {
        return FIFO_ST & (1u << 0u);
    }

    inline bool get_FIFO_ST_RDY() volatile
    {
        return FIFO_ST & (1u << 1u);
    }

    inline bool get_FIFO_ST_WOF() volatile
    {
        return FIFO_ST & (1u << 2u);
    }

    inline void set_FIFO_ST_WOF() volatile
    {
        FIFO_ST |= 1u << 2u;
    }

    inline void clear_FIFO_ST_WOF() volatile
    {
        FIFO_ST &= ~(1u << 2u);
    }

    inline void toggle_FIFO_ST_WOF() volatile
    {
        FIFO_ST ^= 1u << 2u;
    }

    inline bool get_FIFO_ST_ROE() volatile
    {
        return FIFO_ST & (1u << 3u);
    }

    inline void set_FIFO_ST_ROE() volatile
    {
        FIFO_ST |= 1u << 3u;
    }

    inline void clear_FIFO_ST_ROE() volatile
    {
        FIFO_ST &= ~(1u << 3u);
    }

    inline void toggle_FIFO_ST_ROE() volatile
    {
        FIFO_ST ^= 1u << 3u;
    }

    inline void get_FIFO_ST(bool &VLD, bool &RDY, bool &WOF,
                            bool &ROE) volatile
    {
        uint32_t curr = FIFO_ST;

        VLD = curr & (1u << 0u);
        RDY = curr & (1u << 1u);
        WOF = curr & (1u << 2u);
        ROE = curr & (1u << 3u);
    }

    inline void set_FIFO_ST(bool WOF, bool ROE) volatile
    {
        uint32_t curr = FIFO_ST;

        curr &= ~(0b1u << 2u);
        curr |= (WOF & 0b1u) << 2u;
        curr &= ~(0b1u << 3u);
        curr |= (ROE & 0b1u) << 3u;

        FIFO_ST = curr;
    }

    inline bool get_DIV_CSR_READY() volatile
    {
        return DIV_CSR & (1u << 0u);
    }

    inline bool get_DIV_CSR_DIRTY() volatile
    {
        return DIV_CSR & (1u << 1u);
    }

    inline void get_DIV_CSR(bool &READY, bool &DIRTY) volatile
    {
        uint32_t curr = DIV_CSR;

        READY = curr & (1u << 0u);
        DIRTY = curr & (1u << 1u);
    }

    inline uint8_t get_INTERP0_CTRL_LANE0_SHIFT() volatile
    {
        return (INTERP0_CTRL_LANE0 >> 0u) & 0b11111u;
    }

    inline void set_INTERP0_CTRL_LANE0_SHIFT(uint8_t value) volatile
    {
        uint32_t curr = INTERP0_CTRL_LANE0;

        curr &= ~(0b11111u << 0u);
        curr |= (value & 0b11111u) << 0u;

        INTERP0_CTRL_LANE0 = curr;
    }

    inline uint8_t get_INTERP0_CTRL_LANE0_MASK_LSB() volatile
    {
        return (INTERP0_CTRL_LANE0 >> 5u) & 0b11111u;
    }

    inline void set_INTERP0_CTRL_LANE0_MASK_LSB(uint8_t value) volatile
    {
        uint32_t curr = INTERP0_CTRL_LANE0;

        curr &= ~(0b11111u << 5u);
        curr |= (value & 0b11111u) << 5u;

        INTERP0_CTRL_LANE0 = curr;
    }

    inline uint8_t get_INTERP0_CTRL_LANE0_MASK_MSB() volatile
    {
        return (INTERP0_CTRL_LANE0 >> 10u) & 0b11111u;
    }

    inline void set_INTERP0_CTRL_LANE0_MASK_MSB(uint8_t value) volatile
    {
        uint32_t curr = INTERP0_CTRL_LANE0;

        curr &= ~(0b11111u << 10u);
        curr |= (value & 0b11111u) << 10u;

        INTERP0_CTRL_LANE0 = curr;
    }

    inline bool get_INTERP0_CTRL_LANE0_SIGNED() volatile
    {
        return INTERP0_CTRL_LANE0 & (1u << 15u);
    }

    inline void set_INTERP0_CTRL_LANE0_SIGNED() volatile
    {
        INTERP0_CTRL_LANE0 |= 1u << 15u;
    }

    inline void clear_INTERP0_CTRL_LANE0_SIGNED() volatile
    {
        INTERP0_CTRL_LANE0 &= ~(1u << 15u);
    }

    inline void toggle_INTERP0_CTRL_LANE0_SIGNED() volatile
    {
        INTERP0_CTRL_LANE0 ^= 1u << 15u;
    }

    inline bool get_INTERP0_CTRL_LANE0_CROSS_INPUT() volatile
    {
        return INTERP0_CTRL_LANE0 & (1u << 16u);
    }

    inline void set_INTERP0_CTRL_LANE0_CROSS_INPUT() volatile
    {
        INTERP0_CTRL_LANE0 |= 1u << 16u;
    }

    inline void clear_INTERP0_CTRL_LANE0_CROSS_INPUT() volatile
    {
        INTERP0_CTRL_LANE0 &= ~(1u << 16u);
    }

    inline void toggle_INTERP0_CTRL_LANE0_CROSS_INPUT() volatile
    {
        INTERP0_CTRL_LANE0 ^= 1u << 16u;
    }

    inline bool get_INTERP0_CTRL_LANE0_CROSS_RESULT() volatile
    {
        return INTERP0_CTRL_LANE0 & (1u << 17u);
    }

    inline void set_INTERP0_CTRL_LANE0_CROSS_RESULT() volatile
    {
        INTERP0_CTRL_LANE0 |= 1u << 17u;
    }

    inline void clear_INTERP0_CTRL_LANE0_CROSS_RESULT() volatile
    {
        INTERP0_CTRL_LANE0 &= ~(1u << 17u);
    }

    inline void toggle_INTERP0_CTRL_LANE0_CROSS_RESULT() volatile
    {
        INTERP0_CTRL_LANE0 ^= 1u << 17u;
    }

    inline bool get_INTERP0_CTRL_LANE0_ADD_RAW() volatile
    {
        return INTERP0_CTRL_LANE0 & (1u << 18u);
    }

    inline void set_INTERP0_CTRL_LANE0_ADD_RAW() volatile
    {
        INTERP0_CTRL_LANE0 |= 1u << 18u;
    }

    inline void clear_INTERP0_CTRL_LANE0_ADD_RAW() volatile
    {
        INTERP0_CTRL_LANE0 &= ~(1u << 18u);
    }

    inline void toggle_INTERP0_CTRL_LANE0_ADD_RAW() volatile
    {
        INTERP0_CTRL_LANE0 ^= 1u << 18u;
    }

    inline uint8_t get_INTERP0_CTRL_LANE0_FORCE_MSB() volatile
    {
        return (INTERP0_CTRL_LANE0 >> 19u) & 0b11u;
    }

    inline void set_INTERP0_CTRL_LANE0_FORCE_MSB(uint8_t value) volatile
    {
        uint32_t curr = INTERP0_CTRL_LANE0;

        curr &= ~(0b11u << 19u);
        curr |= (value & 0b11u) << 19u;

        INTERP0_CTRL_LANE0 = curr;
    }

    inline bool get_INTERP0_CTRL_LANE0_BLEND() volatile
    {
        return INTERP0_CTRL_LANE0 & (1u << 21u);
    }

    inline void set_INTERP0_CTRL_LANE0_BLEND() volatile
    {
        INTERP0_CTRL_LANE0 |= 1u << 21u;
    }

    inline void clear_INTERP0_CTRL_LANE0_BLEND() volatile
    {
        INTERP0_CTRL_LANE0 &= ~(1u << 21u);
    }

    inline void toggle_INTERP0_CTRL_LANE0_BLEND() volatile
    {
        INTERP0_CTRL_LANE0 ^= 1u << 21u;
    }

    inline bool get_INTERP0_CTRL_LANE0_OVERF0() volatile
    {
        return INTERP0_CTRL_LANE0 & (1u << 23u);
    }

    inline bool get_INTERP0_CTRL_LANE0_OVERF1() volatile
    {
        return INTERP0_CTRL_LANE0 & (1u << 24u);
    }

    inline bool get_INTERP0_CTRL_LANE0_OVERF() volatile
    {
        return INTERP0_CTRL_LANE0 & (1u << 25u);
    }

    inline void get_INTERP0_CTRL_LANE0(uint8_t &SHIFT, uint8_t &MASK_LSB,
                                       uint8_t &MASK_MSB, bool &SIGNED,
                                       bool &CROSS_INPUT, bool &CROSS_RESULT,
                                       bool &ADD_RAW, uint8_t &FORCE_MSB,
                                       bool &BLEND, bool &OVERF0, bool &OVERF1,
                                       bool &OVERF) volatile
    {
        uint32_t curr = INTERP0_CTRL_LANE0;

        SHIFT = (curr >> 0u) & 0b11111u;
        MASK_LSB = (curr >> 5u) & 0b11111u;
        MASK_MSB = (curr >> 10u) & 0b11111u;
        SIGNED = curr & (1u << 15u);
        CROSS_INPUT = curr & (1u << 16u);
        CROSS_RESULT = curr & (1u << 17u);
        ADD_RAW = curr & (1u << 18u);
        FORCE_MSB = (curr >> 19u) & 0b11u;
        BLEND = curr & (1u << 21u);
        OVERF0 = curr & (1u << 23u);
        OVERF1 = curr & (1u << 24u);
        OVERF = curr & (1u << 25u);
    }

    inline void set_INTERP0_CTRL_LANE0(uint8_t SHIFT, uint8_t MASK_LSB,
                                       uint8_t MASK_MSB, bool SIGNED,
                                       bool CROSS_INPUT, bool CROSS_RESULT,
                                       bool ADD_RAW, uint8_t FORCE_MSB,
                                       bool BLEND) volatile
    {
        uint32_t curr = INTERP0_CTRL_LANE0;

        curr &= ~(0b11111u << 0u);
        curr |= (SHIFT & 0b11111u) << 0u;
        curr &= ~(0b11111u << 5u);
        curr |= (MASK_LSB & 0b11111u) << 5u;
        curr &= ~(0b11111u << 10u);
        curr |= (MASK_MSB & 0b11111u) << 10u;
        curr &= ~(0b1u << 15u);
        curr |= (SIGNED & 0b1u) << 15u;
        curr &= ~(0b1u << 16u);
        curr |= (CROSS_INPUT & 0b1u) << 16u;
        curr &= ~(0b1u << 17u);
        curr |= (CROSS_RESULT & 0b1u) << 17u;
        curr &= ~(0b1u << 18u);
        curr |= (ADD_RAW & 0b1u) << 18u;
        curr &= ~(0b11u << 19u);
        curr |= (FORCE_MSB & 0b11u) << 19u;
        curr &= ~(0b1u << 21u);
        curr |= (BLEND & 0b1u) << 21u;

        INTERP0_CTRL_LANE0 = curr;
    }

    inline uint8_t get_INTERP0_CTRL_LANE1_SHIFT() volatile
    {
        return (INTERP0_CTRL_LANE1 >> 0u) & 0b11111u;
    }

    inline void set_INTERP0_CTRL_LANE1_SHIFT(uint8_t value) volatile
    {
        uint32_t curr = INTERP0_CTRL_LANE1;

        curr &= ~(0b11111u << 0u);
        curr |= (value & 0b11111u) << 0u;

        INTERP0_CTRL_LANE1 = curr;
    }

    inline uint8_t get_INTERP0_CTRL_LANE1_MASK_LSB() volatile
    {
        return (INTERP0_CTRL_LANE1 >> 5u) & 0b11111u;
    }

    inline void set_INTERP0_CTRL_LANE1_MASK_LSB(uint8_t value) volatile
    {
        uint32_t curr = INTERP0_CTRL_LANE1;

        curr &= ~(0b11111u << 5u);
        curr |= (value & 0b11111u) << 5u;

        INTERP0_CTRL_LANE1 = curr;
    }

    inline uint8_t get_INTERP0_CTRL_LANE1_MASK_MSB() volatile
    {
        return (INTERP0_CTRL_LANE1 >> 10u) & 0b11111u;
    }

    inline void set_INTERP0_CTRL_LANE1_MASK_MSB(uint8_t value) volatile
    {
        uint32_t curr = INTERP0_CTRL_LANE1;

        curr &= ~(0b11111u << 10u);
        curr |= (value & 0b11111u) << 10u;

        INTERP0_CTRL_LANE1 = curr;
    }

    inline bool get_INTERP0_CTRL_LANE1_SIGNED() volatile
    {
        return INTERP0_CTRL_LANE1 & (1u << 15u);
    }

    inline void set_INTERP0_CTRL_LANE1_SIGNED() volatile
    {
        INTERP0_CTRL_LANE1 |= 1u << 15u;
    }

    inline void clear_INTERP0_CTRL_LANE1_SIGNED() volatile
    {
        INTERP0_CTRL_LANE1 &= ~(1u << 15u);
    }

    inline void toggle_INTERP0_CTRL_LANE1_SIGNED() volatile
    {
        INTERP0_CTRL_LANE1 ^= 1u << 15u;
    }

    inline bool get_INTERP0_CTRL_LANE1_CROSS_INPUT() volatile
    {
        return INTERP0_CTRL_LANE1 & (1u << 16u);
    }

    inline void set_INTERP0_CTRL_LANE1_CROSS_INPUT() volatile
    {
        INTERP0_CTRL_LANE1 |= 1u << 16u;
    }

    inline void clear_INTERP0_CTRL_LANE1_CROSS_INPUT() volatile
    {
        INTERP0_CTRL_LANE1 &= ~(1u << 16u);
    }

    inline void toggle_INTERP0_CTRL_LANE1_CROSS_INPUT() volatile
    {
        INTERP0_CTRL_LANE1 ^= 1u << 16u;
    }

    inline bool get_INTERP0_CTRL_LANE1_CROSS_RESULT() volatile
    {
        return INTERP0_CTRL_LANE1 & (1u << 17u);
    }

    inline void set_INTERP0_CTRL_LANE1_CROSS_RESULT() volatile
    {
        INTERP0_CTRL_LANE1 |= 1u << 17u;
    }

    inline void clear_INTERP0_CTRL_LANE1_CROSS_RESULT() volatile
    {
        INTERP0_CTRL_LANE1 &= ~(1u << 17u);
    }

    inline void toggle_INTERP0_CTRL_LANE1_CROSS_RESULT() volatile
    {
        INTERP0_CTRL_LANE1 ^= 1u << 17u;
    }

    inline bool get_INTERP0_CTRL_LANE1_ADD_RAW() volatile
    {
        return INTERP0_CTRL_LANE1 & (1u << 18u);
    }

    inline void set_INTERP0_CTRL_LANE1_ADD_RAW() volatile
    {
        INTERP0_CTRL_LANE1 |= 1u << 18u;
    }

    inline void clear_INTERP0_CTRL_LANE1_ADD_RAW() volatile
    {
        INTERP0_CTRL_LANE1 &= ~(1u << 18u);
    }

    inline void toggle_INTERP0_CTRL_LANE1_ADD_RAW() volatile
    {
        INTERP0_CTRL_LANE1 ^= 1u << 18u;
    }

    inline uint8_t get_INTERP0_CTRL_LANE1_FORCE_MSB() volatile
    {
        return (INTERP0_CTRL_LANE1 >> 19u) & 0b11u;
    }

    inline void set_INTERP0_CTRL_LANE1_FORCE_MSB(uint8_t value) volatile
    {
        uint32_t curr = INTERP0_CTRL_LANE1;

        curr &= ~(0b11u << 19u);
        curr |= (value & 0b11u) << 19u;

        INTERP0_CTRL_LANE1 = curr;
    }

    inline void get_INTERP0_CTRL_LANE1(uint8_t &SHIFT, uint8_t &MASK_LSB,
                                       uint8_t &MASK_MSB, bool &SIGNED,
                                       bool &CROSS_INPUT, bool &CROSS_RESULT,
                                       bool &ADD_RAW,
                                       uint8_t &FORCE_MSB) volatile
    {
        uint32_t curr = INTERP0_CTRL_LANE1;

        SHIFT = (curr >> 0u) & 0b11111u;
        MASK_LSB = (curr >> 5u) & 0b11111u;
        MASK_MSB = (curr >> 10u) & 0b11111u;
        SIGNED = curr & (1u << 15u);
        CROSS_INPUT = curr & (1u << 16u);
        CROSS_RESULT = curr & (1u << 17u);
        ADD_RAW = curr & (1u << 18u);
        FORCE_MSB = (curr >> 19u) & 0b11u;
    }

    inline void set_INTERP0_CTRL_LANE1(uint8_t SHIFT, uint8_t MASK_LSB,
                                       uint8_t MASK_MSB, bool SIGNED,
                                       bool CROSS_INPUT, bool CROSS_RESULT,
                                       bool ADD_RAW,
                                       uint8_t FORCE_MSB) volatile
    {
        uint32_t curr = INTERP0_CTRL_LANE1;

        curr &= ~(0b11111u << 0u);
        curr |= (SHIFT & 0b11111u) << 0u;
        curr &= ~(0b11111u << 5u);
        curr |= (MASK_LSB & 0b11111u) << 5u;
        curr &= ~(0b11111u << 10u);
        curr |= (MASK_MSB & 0b11111u) << 10u;
        curr &= ~(0b1u << 15u);
        curr |= (SIGNED & 0b1u) << 15u;
        curr &= ~(0b1u << 16u);
        curr |= (CROSS_INPUT & 0b1u) << 16u;
        curr &= ~(0b1u << 17u);
        curr |= (CROSS_RESULT & 0b1u) << 17u;
        curr &= ~(0b1u << 18u);
        curr |= (ADD_RAW & 0b1u) << 18u;
        curr &= ~(0b11u << 19u);
        curr |= (FORCE_MSB & 0b11u) << 19u;

        INTERP0_CTRL_LANE1 = curr;
    }

    inline uint32_t get_INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD() volatile
    {
        return (INTERP0_ACCUM0_ADD >> 0u) & 0b111111111111111111111111u;
    }

    inline void set_INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD(
        uint32_t value) volatile
    {
        uint32_t curr = INTERP0_ACCUM0_ADD;

        curr &= ~(0b111111111111111111111111u << 0u);
        curr |= (value & 0b111111111111111111111111u) << 0u;

        INTERP0_ACCUM0_ADD = curr;
    }

    inline uint32_t get_INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD() volatile
    {
        return (INTERP0_ACCUM1_ADD >> 0u) & 0b111111111111111111111111u;
    }

    inline void set_INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD(
        uint32_t value) volatile
    {
        uint32_t curr = INTERP0_ACCUM1_ADD;

        curr &= ~(0b111111111111111111111111u << 0u);
        curr |= (value & 0b111111111111111111111111u) << 0u;

        INTERP0_ACCUM1_ADD = curr;
    }

    inline uint8_t get_INTERP1_CTRL_LANE0_SHIFT() volatile
    {
        return (INTERP1_CTRL_LANE0 >> 0u) & 0b11111u;
    }

    inline void set_INTERP1_CTRL_LANE0_SHIFT(uint8_t value) volatile
    {
        uint32_t curr = INTERP1_CTRL_LANE0;

        curr &= ~(0b11111u << 0u);
        curr |= (value & 0b11111u) << 0u;

        INTERP1_CTRL_LANE0 = curr;
    }

    inline uint8_t get_INTERP1_CTRL_LANE0_MASK_LSB() volatile
    {
        return (INTERP1_CTRL_LANE0 >> 5u) & 0b11111u;
    }

    inline void set_INTERP1_CTRL_LANE0_MASK_LSB(uint8_t value) volatile
    {
        uint32_t curr = INTERP1_CTRL_LANE0;

        curr &= ~(0b11111u << 5u);
        curr |= (value & 0b11111u) << 5u;

        INTERP1_CTRL_LANE0 = curr;
    }

    inline uint8_t get_INTERP1_CTRL_LANE0_MASK_MSB() volatile
    {
        return (INTERP1_CTRL_LANE0 >> 10u) & 0b11111u;
    }

    inline void set_INTERP1_CTRL_LANE0_MASK_MSB(uint8_t value) volatile
    {
        uint32_t curr = INTERP1_CTRL_LANE0;

        curr &= ~(0b11111u << 10u);
        curr |= (value & 0b11111u) << 10u;

        INTERP1_CTRL_LANE0 = curr;
    }

    inline bool get_INTERP1_CTRL_LANE0_SIGNED() volatile
    {
        return INTERP1_CTRL_LANE0 & (1u << 15u);
    }

    inline void set_INTERP1_CTRL_LANE0_SIGNED() volatile
    {
        INTERP1_CTRL_LANE0 |= 1u << 15u;
    }

    inline void clear_INTERP1_CTRL_LANE0_SIGNED() volatile
    {
        INTERP1_CTRL_LANE0 &= ~(1u << 15u);
    }

    inline void toggle_INTERP1_CTRL_LANE0_SIGNED() volatile
    {
        INTERP1_CTRL_LANE0 ^= 1u << 15u;
    }

    inline bool get_INTERP1_CTRL_LANE0_CROSS_INPUT() volatile
    {
        return INTERP1_CTRL_LANE0 & (1u << 16u);
    }

    inline void set_INTERP1_CTRL_LANE0_CROSS_INPUT() volatile
    {
        INTERP1_CTRL_LANE0 |= 1u << 16u;
    }

    inline void clear_INTERP1_CTRL_LANE0_CROSS_INPUT() volatile
    {
        INTERP1_CTRL_LANE0 &= ~(1u << 16u);
    }

    inline void toggle_INTERP1_CTRL_LANE0_CROSS_INPUT() volatile
    {
        INTERP1_CTRL_LANE0 ^= 1u << 16u;
    }

    inline bool get_INTERP1_CTRL_LANE0_CROSS_RESULT() volatile
    {
        return INTERP1_CTRL_LANE0 & (1u << 17u);
    }

    inline void set_INTERP1_CTRL_LANE0_CROSS_RESULT() volatile
    {
        INTERP1_CTRL_LANE0 |= 1u << 17u;
    }

    inline void clear_INTERP1_CTRL_LANE0_CROSS_RESULT() volatile
    {
        INTERP1_CTRL_LANE0 &= ~(1u << 17u);
    }

    inline void toggle_INTERP1_CTRL_LANE0_CROSS_RESULT() volatile
    {
        INTERP1_CTRL_LANE0 ^= 1u << 17u;
    }

    inline bool get_INTERP1_CTRL_LANE0_ADD_RAW() volatile
    {
        return INTERP1_CTRL_LANE0 & (1u << 18u);
    }

    inline void set_INTERP1_CTRL_LANE0_ADD_RAW() volatile
    {
        INTERP1_CTRL_LANE0 |= 1u << 18u;
    }

    inline void clear_INTERP1_CTRL_LANE0_ADD_RAW() volatile
    {
        INTERP1_CTRL_LANE0 &= ~(1u << 18u);
    }

    inline void toggle_INTERP1_CTRL_LANE0_ADD_RAW() volatile
    {
        INTERP1_CTRL_LANE0 ^= 1u << 18u;
    }

    inline uint8_t get_INTERP1_CTRL_LANE0_FORCE_MSB() volatile
    {
        return (INTERP1_CTRL_LANE0 >> 19u) & 0b11u;
    }

    inline void set_INTERP1_CTRL_LANE0_FORCE_MSB(uint8_t value) volatile
    {
        uint32_t curr = INTERP1_CTRL_LANE0;

        curr &= ~(0b11u << 19u);
        curr |= (value & 0b11u) << 19u;

        INTERP1_CTRL_LANE0 = curr;
    }

    inline bool get_INTERP1_CTRL_LANE0_CLAMP() volatile
    {
        return INTERP1_CTRL_LANE0 & (1u << 22u);
    }

    inline void set_INTERP1_CTRL_LANE0_CLAMP() volatile
    {
        INTERP1_CTRL_LANE0 |= 1u << 22u;
    }

    inline void clear_INTERP1_CTRL_LANE0_CLAMP() volatile
    {
        INTERP1_CTRL_LANE0 &= ~(1u << 22u);
    }

    inline void toggle_INTERP1_CTRL_LANE0_CLAMP() volatile
    {
        INTERP1_CTRL_LANE0 ^= 1u << 22u;
    }

    inline bool get_INTERP1_CTRL_LANE0_OVERF0() volatile
    {
        return INTERP1_CTRL_LANE0 & (1u << 23u);
    }

    inline bool get_INTERP1_CTRL_LANE0_OVERF1() volatile
    {
        return INTERP1_CTRL_LANE0 & (1u << 24u);
    }

    inline bool get_INTERP1_CTRL_LANE0_OVERF() volatile
    {
        return INTERP1_CTRL_LANE0 & (1u << 25u);
    }

    inline void get_INTERP1_CTRL_LANE0(uint8_t &SHIFT, uint8_t &MASK_LSB,
                                       uint8_t &MASK_MSB, bool &SIGNED,
                                       bool &CROSS_INPUT, bool &CROSS_RESULT,
                                       bool &ADD_RAW, uint8_t &FORCE_MSB,
                                       bool &CLAMP, bool &OVERF0, bool &OVERF1,
                                       bool &OVERF) volatile
    {
        uint32_t curr = INTERP1_CTRL_LANE0;

        SHIFT = (curr >> 0u) & 0b11111u;
        MASK_LSB = (curr >> 5u) & 0b11111u;
        MASK_MSB = (curr >> 10u) & 0b11111u;
        SIGNED = curr & (1u << 15u);
        CROSS_INPUT = curr & (1u << 16u);
        CROSS_RESULT = curr & (1u << 17u);
        ADD_RAW = curr & (1u << 18u);
        FORCE_MSB = (curr >> 19u) & 0b11u;
        CLAMP = curr & (1u << 22u);
        OVERF0 = curr & (1u << 23u);
        OVERF1 = curr & (1u << 24u);
        OVERF = curr & (1u << 25u);
    }

    inline void set_INTERP1_CTRL_LANE0(uint8_t SHIFT, uint8_t MASK_LSB,
                                       uint8_t MASK_MSB, bool SIGNED,
                                       bool CROSS_INPUT, bool CROSS_RESULT,
                                       bool ADD_RAW, uint8_t FORCE_MSB,
                                       bool CLAMP) volatile
    {
        uint32_t curr = INTERP1_CTRL_LANE0;

        curr &= ~(0b11111u << 0u);
        curr |= (SHIFT & 0b11111u) << 0u;
        curr &= ~(0b11111u << 5u);
        curr |= (MASK_LSB & 0b11111u) << 5u;
        curr &= ~(0b11111u << 10u);
        curr |= (MASK_MSB & 0b11111u) << 10u;
        curr &= ~(0b1u << 15u);
        curr |= (SIGNED & 0b1u) << 15u;
        curr &= ~(0b1u << 16u);
        curr |= (CROSS_INPUT & 0b1u) << 16u;
        curr &= ~(0b1u << 17u);
        curr |= (CROSS_RESULT & 0b1u) << 17u;
        curr &= ~(0b1u << 18u);
        curr |= (ADD_RAW & 0b1u) << 18u;
        curr &= ~(0b11u << 19u);
        curr |= (FORCE_MSB & 0b11u) << 19u;
        curr &= ~(0b1u << 22u);
        curr |= (CLAMP & 0b1u) << 22u;

        INTERP1_CTRL_LANE0 = curr;
    }

    inline uint8_t get_INTERP1_CTRL_LANE1_SHIFT() volatile
    {
        return (INTERP1_CTRL_LANE1 >> 0u) & 0b11111u;
    }

    inline void set_INTERP1_CTRL_LANE1_SHIFT(uint8_t value) volatile
    {
        uint32_t curr = INTERP1_CTRL_LANE1;

        curr &= ~(0b11111u << 0u);
        curr |= (value & 0b11111u) << 0u;

        INTERP1_CTRL_LANE1 = curr;
    }

    inline uint8_t get_INTERP1_CTRL_LANE1_MASK_LSB() volatile
    {
        return (INTERP1_CTRL_LANE1 >> 5u) & 0b11111u;
    }

    inline void set_INTERP1_CTRL_LANE1_MASK_LSB(uint8_t value) volatile
    {
        uint32_t curr = INTERP1_CTRL_LANE1;

        curr &= ~(0b11111u << 5u);
        curr |= (value & 0b11111u) << 5u;

        INTERP1_CTRL_LANE1 = curr;
    }

    inline uint8_t get_INTERP1_CTRL_LANE1_MASK_MSB() volatile
    {
        return (INTERP1_CTRL_LANE1 >> 10u) & 0b11111u;
    }

    inline void set_INTERP1_CTRL_LANE1_MASK_MSB(uint8_t value) volatile
    {
        uint32_t curr = INTERP1_CTRL_LANE1;

        curr &= ~(0b11111u << 10u);
        curr |= (value & 0b11111u) << 10u;

        INTERP1_CTRL_LANE1 = curr;
    }

    inline bool get_INTERP1_CTRL_LANE1_SIGNED() volatile
    {
        return INTERP1_CTRL_LANE1 & (1u << 15u);
    }

    inline void set_INTERP1_CTRL_LANE1_SIGNED() volatile
    {
        INTERP1_CTRL_LANE1 |= 1u << 15u;
    }

    inline void clear_INTERP1_CTRL_LANE1_SIGNED() volatile
    {
        INTERP1_CTRL_LANE1 &= ~(1u << 15u);
    }

    inline void toggle_INTERP1_CTRL_LANE1_SIGNED() volatile
    {
        INTERP1_CTRL_LANE1 ^= 1u << 15u;
    }

    inline bool get_INTERP1_CTRL_LANE1_CROSS_INPUT() volatile
    {
        return INTERP1_CTRL_LANE1 & (1u << 16u);
    }

    inline void set_INTERP1_CTRL_LANE1_CROSS_INPUT() volatile
    {
        INTERP1_CTRL_LANE1 |= 1u << 16u;
    }

    inline void clear_INTERP1_CTRL_LANE1_CROSS_INPUT() volatile
    {
        INTERP1_CTRL_LANE1 &= ~(1u << 16u);
    }

    inline void toggle_INTERP1_CTRL_LANE1_CROSS_INPUT() volatile
    {
        INTERP1_CTRL_LANE1 ^= 1u << 16u;
    }

    inline bool get_INTERP1_CTRL_LANE1_CROSS_RESULT() volatile
    {
        return INTERP1_CTRL_LANE1 & (1u << 17u);
    }

    inline void set_INTERP1_CTRL_LANE1_CROSS_RESULT() volatile
    {
        INTERP1_CTRL_LANE1 |= 1u << 17u;
    }

    inline void clear_INTERP1_CTRL_LANE1_CROSS_RESULT() volatile
    {
        INTERP1_CTRL_LANE1 &= ~(1u << 17u);
    }

    inline void toggle_INTERP1_CTRL_LANE1_CROSS_RESULT() volatile
    {
        INTERP1_CTRL_LANE1 ^= 1u << 17u;
    }

    inline bool get_INTERP1_CTRL_LANE1_ADD_RAW() volatile
    {
        return INTERP1_CTRL_LANE1 & (1u << 18u);
    }

    inline void set_INTERP1_CTRL_LANE1_ADD_RAW() volatile
    {
        INTERP1_CTRL_LANE1 |= 1u << 18u;
    }

    inline void clear_INTERP1_CTRL_LANE1_ADD_RAW() volatile
    {
        INTERP1_CTRL_LANE1 &= ~(1u << 18u);
    }

    inline void toggle_INTERP1_CTRL_LANE1_ADD_RAW() volatile
    {
        INTERP1_CTRL_LANE1 ^= 1u << 18u;
    }

    inline uint8_t get_INTERP1_CTRL_LANE1_FORCE_MSB() volatile
    {
        return (INTERP1_CTRL_LANE1 >> 19u) & 0b11u;
    }

    inline void set_INTERP1_CTRL_LANE1_FORCE_MSB(uint8_t value) volatile
    {
        uint32_t curr = INTERP1_CTRL_LANE1;

        curr &= ~(0b11u << 19u);
        curr |= (value & 0b11u) << 19u;

        INTERP1_CTRL_LANE1 = curr;
    }

    inline void get_INTERP1_CTRL_LANE1(uint8_t &SHIFT, uint8_t &MASK_LSB,
                                       uint8_t &MASK_MSB, bool &SIGNED,
                                       bool &CROSS_INPUT, bool &CROSS_RESULT,
                                       bool &ADD_RAW,
                                       uint8_t &FORCE_MSB) volatile
    {
        uint32_t curr = INTERP1_CTRL_LANE1;

        SHIFT = (curr >> 0u) & 0b11111u;
        MASK_LSB = (curr >> 5u) & 0b11111u;
        MASK_MSB = (curr >> 10u) & 0b11111u;
        SIGNED = curr & (1u << 15u);
        CROSS_INPUT = curr & (1u << 16u);
        CROSS_RESULT = curr & (1u << 17u);
        ADD_RAW = curr & (1u << 18u);
        FORCE_MSB = (curr >> 19u) & 0b11u;
    }

    inline void set_INTERP1_CTRL_LANE1(uint8_t SHIFT, uint8_t MASK_LSB,
                                       uint8_t MASK_MSB, bool SIGNED,
                                       bool CROSS_INPUT, bool CROSS_RESULT,
                                       bool ADD_RAW,
                                       uint8_t FORCE_MSB) volatile
    {
        uint32_t curr = INTERP1_CTRL_LANE1;

        curr &= ~(0b11111u << 0u);
        curr |= (SHIFT & 0b11111u) << 0u;
        curr &= ~(0b11111u << 5u);
        curr |= (MASK_LSB & 0b11111u) << 5u;
        curr &= ~(0b11111u << 10u);
        curr |= (MASK_MSB & 0b11111u) << 10u;
        curr &= ~(0b1u << 15u);
        curr |= (SIGNED & 0b1u) << 15u;
        curr &= ~(0b1u << 16u);
        curr |= (CROSS_INPUT & 0b1u) << 16u;
        curr &= ~(0b1u << 17u);
        curr |= (CROSS_RESULT & 0b1u) << 17u;
        curr &= ~(0b1u << 18u);
        curr |= (ADD_RAW & 0b1u) << 18u;
        curr &= ~(0b11u << 19u);
        curr |= (FORCE_MSB & 0b11u) << 19u;

        INTERP1_CTRL_LANE1 = curr;
    }

    inline uint32_t get_INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD() volatile
    {
        return (INTERP1_ACCUM0_ADD >> 0u) & 0b111111111111111111111111u;
    }

    inline void set_INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD(
        uint32_t value) volatile
    {
        uint32_t curr = INTERP1_ACCUM0_ADD;

        curr &= ~(0b111111111111111111111111u << 0u);
        curr |= (value & 0b111111111111111111111111u) << 0u;

        INTERP1_ACCUM0_ADD = curr;
    }

    inline uint32_t get_INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD() volatile
    {
        return (INTERP1_ACCUM1_ADD >> 0u) & 0b111111111111111111111111u;
    }

    inline void set_INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD(
        uint32_t value) volatile
    {
        uint32_t curr = INTERP1_ACCUM1_ADD;

        curr &= ~(0b111111111111111111111111u << 0u);
        curr |= (value & 0b111111111111111111111111u) << 0u;

        INTERP1_ACCUM1_ADD = curr;
    }
};

static_assert(sizeof(sio) == sio::size);

static volatile sio *const SIO = reinterpret_cast<sio *>(0xd0000000);

}; // namespace RP2040