Program Listing for File rosc.h

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#pragma once

#include "../enums/ROSC_CTRL_ENABLE.h"
#include "../enums/ROSC_CTRL_FREQ_RANGE.h"
#include "../enums/ROSC_DIV_DIV.h"
#include "../enums/ROSC_FREQA_PASSWD.h"
#include "../enums/ROSC_FREQB_PASSWD.h"
#include "../ifgen/common.h"

namespace RP2040
{

struct [[gnu::packed]] rosc
{
    /* Constant attributes. */
    static constexpr std::size_t size = 36;
    /* Fields. */
    uint32_t CTRL;
    uint32_t FREQA;
    uint32_t FREQB;
    uint32_t DORMANT;
    uint32_t DIV;
    uint32_t PHASE;
    uint32_t STATUS;
    const uint32_t RANDOMBIT =
        {};
    uint32_t COUNT;
    /* Methods. */

    inline ROSC_CTRL_FREQ_RANGE get_CTRL_FREQ_RANGE() volatile
    {
        return ROSC_CTRL_FREQ_RANGE((CTRL >> 0u) & 0b111111111111u);
    }

    inline void set_CTRL_FREQ_RANGE(ROSC_CTRL_FREQ_RANGE value) volatile
    {
        uint32_t curr = CTRL;

        curr &= ~(0b111111111111u << 0u);
        curr |= (std::to_underlying(value) & 0b111111111111u) << 0u;

        CTRL = curr;
    }

    inline ROSC_CTRL_ENABLE get_CTRL_ENABLE() volatile
    {
        return ROSC_CTRL_ENABLE((CTRL >> 12u) & 0b111111111111u);
    }

    inline void set_CTRL_ENABLE(ROSC_CTRL_ENABLE value) volatile
    {
        uint32_t curr = CTRL;

        curr &= ~(0b111111111111u << 12u);
        curr |= (std::to_underlying(value) & 0b111111111111u) << 12u;

        CTRL = curr;
    }

    inline void get_CTRL(ROSC_CTRL_FREQ_RANGE &FREQ_RANGE,
                         ROSC_CTRL_ENABLE &ENABLE) volatile
    {
        uint32_t curr = CTRL;

        FREQ_RANGE = ROSC_CTRL_FREQ_RANGE((curr >> 0u) & 0b111111111111u);
        ENABLE = ROSC_CTRL_ENABLE((curr >> 12u) & 0b111111111111u);
    }

    inline void set_CTRL(ROSC_CTRL_FREQ_RANGE FREQ_RANGE,
                         ROSC_CTRL_ENABLE ENABLE) volatile
    {
        uint32_t curr = CTRL;

        curr &= ~(0b111111111111u << 0u);
        curr |= (std::to_underlying(FREQ_RANGE) & 0b111111111111u) << 0u;
        curr &= ~(0b111111111111u << 12u);
        curr |= (std::to_underlying(ENABLE) & 0b111111111111u) << 12u;

        CTRL = curr;
    }

    inline uint8_t get_FREQA_DS0() volatile
    {
        return (FREQA >> 0u) & 0b111u;
    }

    inline void set_FREQA_DS0(uint8_t value) volatile
    {
        uint32_t curr = FREQA;

        curr &= ~(0b111u << 0u);
        curr |= (value & 0b111u) << 0u;

        FREQA = curr;
    }

    inline uint8_t get_FREQA_DS1() volatile
    {
        return (FREQA >> 4u) & 0b111u;
    }

    inline void set_FREQA_DS1(uint8_t value) volatile
    {
        uint32_t curr = FREQA;

        curr &= ~(0b111u << 4u);
        curr |= (value & 0b111u) << 4u;

        FREQA = curr;
    }

    inline uint8_t get_FREQA_DS2() volatile
    {
        return (FREQA >> 8u) & 0b111u;
    }

    inline void set_FREQA_DS2(uint8_t value) volatile
    {
        uint32_t curr = FREQA;

        curr &= ~(0b111u << 8u);
        curr |= (value & 0b111u) << 8u;

        FREQA = curr;
    }

    inline uint8_t get_FREQA_DS3() volatile
    {
        return (FREQA >> 12u) & 0b111u;
    }

    inline void set_FREQA_DS3(uint8_t value) volatile
    {
        uint32_t curr = FREQA;

        curr &= ~(0b111u << 12u);
        curr |= (value & 0b111u) << 12u;

        FREQA = curr;
    }

    inline ROSC_FREQA_PASSWD get_FREQA_PASSWD() volatile
    {
        return ROSC_FREQA_PASSWD((FREQA >> 16u) & 0b1111111111111111u);
    }

    inline void set_FREQA_PASSWD(ROSC_FREQA_PASSWD value) volatile
    {
        uint32_t curr = FREQA;

        curr &= ~(0b1111111111111111u << 16u);
        curr |= (std::to_underlying(value) & 0b1111111111111111u) << 16u;

        FREQA = curr;
    }

    inline void get_FREQA(uint8_t &DS0, uint8_t &DS1, uint8_t &DS2,
                          uint8_t &DS3, ROSC_FREQA_PASSWD &PASSWD) volatile
    {
        uint32_t curr = FREQA;

        DS0 = (curr >> 0u) & 0b111u;
        DS1 = (curr >> 4u) & 0b111u;
        DS2 = (curr >> 8u) & 0b111u;
        DS3 = (curr >> 12u) & 0b111u;
        PASSWD = ROSC_FREQA_PASSWD((curr >> 16u) & 0b1111111111111111u);
    }

    inline void set_FREQA(uint8_t DS0, uint8_t DS1, uint8_t DS2, uint8_t DS3,
                          ROSC_FREQA_PASSWD PASSWD) volatile
    {
        uint32_t curr = FREQA;

        curr &= ~(0b111u << 0u);
        curr |= (DS0 & 0b111u) << 0u;
        curr &= ~(0b111u << 4u);
        curr |= (DS1 & 0b111u) << 4u;
        curr &= ~(0b111u << 8u);
        curr |= (DS2 & 0b111u) << 8u;
        curr &= ~(0b111u << 12u);
        curr |= (DS3 & 0b111u) << 12u;
        curr &= ~(0b1111111111111111u << 16u);
        curr |= (std::to_underlying(PASSWD) & 0b1111111111111111u) << 16u;

        FREQA = curr;
    }

    inline uint8_t get_FREQB_DS4() volatile
    {
        return (FREQB >> 0u) & 0b111u;
    }

    inline void set_FREQB_DS4(uint8_t value) volatile
    {
        uint32_t curr = FREQB;

        curr &= ~(0b111u << 0u);
        curr |= (value & 0b111u) << 0u;

        FREQB = curr;
    }

    inline uint8_t get_FREQB_DS5() volatile
    {
        return (FREQB >> 4u) & 0b111u;
    }

    inline void set_FREQB_DS5(uint8_t value) volatile
    {
        uint32_t curr = FREQB;

        curr &= ~(0b111u << 4u);
        curr |= (value & 0b111u) << 4u;

        FREQB = curr;
    }

    inline uint8_t get_FREQB_DS6() volatile
    {
        return (FREQB >> 8u) & 0b111u;
    }

    inline void set_FREQB_DS6(uint8_t value) volatile
    {
        uint32_t curr = FREQB;

        curr &= ~(0b111u << 8u);
        curr |= (value & 0b111u) << 8u;

        FREQB = curr;
    }

    inline uint8_t get_FREQB_DS7() volatile
    {
        return (FREQB >> 12u) & 0b111u;
    }

    inline void set_FREQB_DS7(uint8_t value) volatile
    {
        uint32_t curr = FREQB;

        curr &= ~(0b111u << 12u);
        curr |= (value & 0b111u) << 12u;

        FREQB = curr;
    }

    inline ROSC_FREQB_PASSWD get_FREQB_PASSWD() volatile
    {
        return ROSC_FREQB_PASSWD((FREQB >> 16u) & 0b1111111111111111u);
    }

    inline void set_FREQB_PASSWD(ROSC_FREQB_PASSWD value) volatile
    {
        uint32_t curr = FREQB;

        curr &= ~(0b1111111111111111u << 16u);
        curr |= (std::to_underlying(value) & 0b1111111111111111u) << 16u;

        FREQB = curr;
    }

    inline void get_FREQB(uint8_t &DS4, uint8_t &DS5, uint8_t &DS6,
                          uint8_t &DS7, ROSC_FREQB_PASSWD &PASSWD) volatile
    {
        uint32_t curr = FREQB;

        DS4 = (curr >> 0u) & 0b111u;
        DS5 = (curr >> 4u) & 0b111u;
        DS6 = (curr >> 8u) & 0b111u;
        DS7 = (curr >> 12u) & 0b111u;
        PASSWD = ROSC_FREQB_PASSWD((curr >> 16u) & 0b1111111111111111u);
    }

    inline void set_FREQB(uint8_t DS4, uint8_t DS5, uint8_t DS6, uint8_t DS7,
                          ROSC_FREQB_PASSWD PASSWD) volatile
    {
        uint32_t curr = FREQB;

        curr &= ~(0b111u << 0u);
        curr |= (DS4 & 0b111u) << 0u;
        curr &= ~(0b111u << 4u);
        curr |= (DS5 & 0b111u) << 4u;
        curr &= ~(0b111u << 8u);
        curr |= (DS6 & 0b111u) << 8u;
        curr &= ~(0b111u << 12u);
        curr |= (DS7 & 0b111u) << 12u;
        curr &= ~(0b1111111111111111u << 16u);
        curr |= (std::to_underlying(PASSWD) & 0b1111111111111111u) << 16u;

        FREQB = curr;
    }

    inline ROSC_DIV_DIV get_DIV_DIV() volatile
    {
        return ROSC_DIV_DIV((DIV >> 0u) & 0b111111111111u);
    }

    inline void set_DIV_DIV(ROSC_DIV_DIV value) volatile
    {
        uint32_t curr = DIV;

        curr &= ~(0b111111111111u << 0u);
        curr |= (std::to_underlying(value) & 0b111111111111u) << 0u;

        DIV = curr;
    }

    inline uint8_t get_PHASE_SHIFT() volatile
    {
        return (PHASE >> 0u) & 0b11u;
    }

    inline void set_PHASE_SHIFT(uint8_t value) volatile
    {
        uint32_t curr = PHASE;

        curr &= ~(0b11u << 0u);
        curr |= (value & 0b11u) << 0u;

        PHASE = curr;
    }

    inline bool get_PHASE_FLIP() volatile
    {
        return PHASE & (1u << 2u);
    }

    inline void set_PHASE_FLIP() volatile
    {
        PHASE |= 1u << 2u;
    }

    inline void clear_PHASE_FLIP() volatile
    {
        PHASE &= ~(1u << 2u);
    }

    inline void toggle_PHASE_FLIP() volatile
    {
        PHASE ^= 1u << 2u;
    }

    inline bool get_PHASE_ENABLE() volatile
    {
        return PHASE & (1u << 3u);
    }

    inline void set_PHASE_ENABLE() volatile
    {
        PHASE |= 1u << 3u;
    }

    inline void clear_PHASE_ENABLE() volatile
    {
        PHASE &= ~(1u << 3u);
    }

    inline void toggle_PHASE_ENABLE() volatile
    {
        PHASE ^= 1u << 3u;
    }

    inline uint8_t get_PHASE_PASSWD() volatile
    {
        return (PHASE >> 4u) & 0b11111111u;
    }

    inline void set_PHASE_PASSWD(uint8_t value) volatile
    {
        uint32_t curr = PHASE;

        curr &= ~(0b11111111u << 4u);
        curr |= (value & 0b11111111u) << 4u;

        PHASE = curr;
    }

    inline void get_PHASE(uint8_t &SHIFT, bool &FLIP, bool &ENABLE,
                          uint8_t &PASSWD) volatile
    {
        uint32_t curr = PHASE;

        SHIFT = (curr >> 0u) & 0b11u;
        FLIP = curr & (1u << 2u);
        ENABLE = curr & (1u << 3u);
        PASSWD = (curr >> 4u) & 0b11111111u;
    }

    inline void set_PHASE(uint8_t SHIFT, bool FLIP, bool ENABLE,
                          uint8_t PASSWD) volatile
    {
        uint32_t curr = PHASE;

        curr &= ~(0b11u << 0u);
        curr |= (SHIFT & 0b11u) << 0u;
        curr &= ~(0b1u << 2u);
        curr |= (FLIP & 0b1u) << 2u;
        curr &= ~(0b1u << 3u);
        curr |= (ENABLE & 0b1u) << 3u;
        curr &= ~(0b11111111u << 4u);
        curr |= (PASSWD & 0b11111111u) << 4u;

        PHASE = curr;
    }

    inline bool get_STATUS_ENABLED() volatile
    {
        return STATUS & (1u << 12u);
    }

    inline bool get_STATUS_DIV_RUNNING() volatile
    {
        return STATUS & (1u << 16u);
    }

    inline bool get_STATUS_BADWRITE() volatile
    {
        return STATUS & (1u << 24u);
    }

    inline void set_STATUS_BADWRITE() volatile
    {
        STATUS |= 1u << 24u;
    }

    inline void clear_STATUS_BADWRITE() volatile
    {
        STATUS &= ~(1u << 24u);
    }

    inline void toggle_STATUS_BADWRITE() volatile
    {
        STATUS ^= 1u << 24u;
    }

    inline bool get_STATUS_STABLE() volatile
    {
        return STATUS & (1u << 31u);
    }

    inline void get_STATUS(bool &ENABLED, bool &DIV_RUNNING, bool &BADWRITE,
                           bool &STABLE) volatile
    {
        uint32_t curr = STATUS;

        ENABLED = curr & (1u << 12u);
        DIV_RUNNING = curr & (1u << 16u);
        BADWRITE = curr & (1u << 24u);
        STABLE = curr & (1u << 31u);
    }

    inline bool get_RANDOMBIT_RANDOMBIT() volatile
    {
        return RANDOMBIT & (1u << 0u);
    }

    inline uint8_t get_COUNT_COUNT() volatile
    {
        return (COUNT >> 0u) & 0b11111111u;
    }

    inline void set_COUNT_COUNT(uint8_t value) volatile
    {
        uint32_t curr = COUNT;

        curr &= ~(0b11111111u << 0u);
        curr |= (value & 0b11111111u) << 0u;

        COUNT = curr;
    }
};

static_assert(sizeof(rosc) == rosc::size);

static volatile rosc *const ROSC = reinterpret_cast<rosc *>(0x40060000);

}; // namespace RP2040