Program Listing for File psm.h

↰ Return to documentation for file (src/generated/structs/psm.h)

#pragma once

#include "../ifgen/common.h"

namespace RP2040
{

struct [[gnu::packed]] psm
{
    /* Constant attributes. */
    static constexpr std::size_t size = 16;
    /* Fields. */
    uint32_t FRCE_ON;
    uint32_t
        FRCE_OFF;
    uint32_t WDSEL;
    const uint32_t DONE = {};
    /* Methods. */

    inline bool get_FRCE_ON_rosc() volatile
    {
        return FRCE_ON & (1u << 0u);
    }

    inline void set_FRCE_ON_rosc() volatile
    {
        FRCE_ON |= 1u << 0u;
    }

    inline void clear_FRCE_ON_rosc() volatile
    {
        FRCE_ON &= ~(1u << 0u);
    }

    inline void toggle_FRCE_ON_rosc() volatile
    {
        FRCE_ON ^= 1u << 0u;
    }

    inline bool get_FRCE_ON_xosc() volatile
    {
        return FRCE_ON & (1u << 1u);
    }

    inline void set_FRCE_ON_xosc() volatile
    {
        FRCE_ON |= 1u << 1u;
    }

    inline void clear_FRCE_ON_xosc() volatile
    {
        FRCE_ON &= ~(1u << 1u);
    }

    inline void toggle_FRCE_ON_xosc() volatile
    {
        FRCE_ON ^= 1u << 1u;
    }

    inline bool get_FRCE_ON_clocks() volatile
    {
        return FRCE_ON & (1u << 2u);
    }

    inline void set_FRCE_ON_clocks() volatile
    {
        FRCE_ON |= 1u << 2u;
    }

    inline void clear_FRCE_ON_clocks() volatile
    {
        FRCE_ON &= ~(1u << 2u);
    }

    inline void toggle_FRCE_ON_clocks() volatile
    {
        FRCE_ON ^= 1u << 2u;
    }

    inline bool get_FRCE_ON_resets() volatile
    {
        return FRCE_ON & (1u << 3u);
    }

    inline void set_FRCE_ON_resets() volatile
    {
        FRCE_ON |= 1u << 3u;
    }

    inline void clear_FRCE_ON_resets() volatile
    {
        FRCE_ON &= ~(1u << 3u);
    }

    inline void toggle_FRCE_ON_resets() volatile
    {
        FRCE_ON ^= 1u << 3u;
    }

    inline bool get_FRCE_ON_busfabric() volatile
    {
        return FRCE_ON & (1u << 4u);
    }

    inline void set_FRCE_ON_busfabric() volatile
    {
        FRCE_ON |= 1u << 4u;
    }

    inline void clear_FRCE_ON_busfabric() volatile
    {
        FRCE_ON &= ~(1u << 4u);
    }

    inline void toggle_FRCE_ON_busfabric() volatile
    {
        FRCE_ON ^= 1u << 4u;
    }

    inline bool get_FRCE_ON_rom() volatile
    {
        return FRCE_ON & (1u << 5u);
    }

    inline void set_FRCE_ON_rom() volatile
    {
        FRCE_ON |= 1u << 5u;
    }

    inline void clear_FRCE_ON_rom() volatile
    {
        FRCE_ON &= ~(1u << 5u);
    }

    inline void toggle_FRCE_ON_rom() volatile
    {
        FRCE_ON ^= 1u << 5u;
    }

    inline bool get_FRCE_ON_sram0() volatile
    {
        return FRCE_ON & (1u << 6u);
    }

    inline void set_FRCE_ON_sram0() volatile
    {
        FRCE_ON |= 1u << 6u;
    }

    inline void clear_FRCE_ON_sram0() volatile
    {
        FRCE_ON &= ~(1u << 6u);
    }

    inline void toggle_FRCE_ON_sram0() volatile
    {
        FRCE_ON ^= 1u << 6u;
    }

    inline bool get_FRCE_ON_sram1() volatile
    {
        return FRCE_ON & (1u << 7u);
    }

    inline void set_FRCE_ON_sram1() volatile
    {
        FRCE_ON |= 1u << 7u;
    }

    inline void clear_FRCE_ON_sram1() volatile
    {
        FRCE_ON &= ~(1u << 7u);
    }

    inline void toggle_FRCE_ON_sram1() volatile
    {
        FRCE_ON ^= 1u << 7u;
    }

    inline bool get_FRCE_ON_sram2() volatile
    {
        return FRCE_ON & (1u << 8u);
    }

    inline void set_FRCE_ON_sram2() volatile
    {
        FRCE_ON |= 1u << 8u;
    }

    inline void clear_FRCE_ON_sram2() volatile
    {
        FRCE_ON &= ~(1u << 8u);
    }

    inline void toggle_FRCE_ON_sram2() volatile
    {
        FRCE_ON ^= 1u << 8u;
    }

    inline bool get_FRCE_ON_sram3() volatile
    {
        return FRCE_ON & (1u << 9u);
    }

    inline void set_FRCE_ON_sram3() volatile
    {
        FRCE_ON |= 1u << 9u;
    }

    inline void clear_FRCE_ON_sram3() volatile
    {
        FRCE_ON &= ~(1u << 9u);
    }

    inline void toggle_FRCE_ON_sram3() volatile
    {
        FRCE_ON ^= 1u << 9u;
    }

    inline bool get_FRCE_ON_sram4() volatile
    {
        return FRCE_ON & (1u << 10u);
    }

    inline void set_FRCE_ON_sram4() volatile
    {
        FRCE_ON |= 1u << 10u;
    }

    inline void clear_FRCE_ON_sram4() volatile
    {
        FRCE_ON &= ~(1u << 10u);
    }

    inline void toggle_FRCE_ON_sram4() volatile
    {
        FRCE_ON ^= 1u << 10u;
    }

    inline bool get_FRCE_ON_sram5() volatile
    {
        return FRCE_ON & (1u << 11u);
    }

    inline void set_FRCE_ON_sram5() volatile
    {
        FRCE_ON |= 1u << 11u;
    }

    inline void clear_FRCE_ON_sram5() volatile
    {
        FRCE_ON &= ~(1u << 11u);
    }

    inline void toggle_FRCE_ON_sram5() volatile
    {
        FRCE_ON ^= 1u << 11u;
    }

    inline bool get_FRCE_ON_xip() volatile
    {
        return FRCE_ON & (1u << 12u);
    }

    inline void set_FRCE_ON_xip() volatile
    {
        FRCE_ON |= 1u << 12u;
    }

    inline void clear_FRCE_ON_xip() volatile
    {
        FRCE_ON &= ~(1u << 12u);
    }

    inline void toggle_FRCE_ON_xip() volatile
    {
        FRCE_ON ^= 1u << 12u;
    }

    inline bool get_FRCE_ON_vreg_and_chip_reset() volatile
    {
        return FRCE_ON & (1u << 13u);
    }

    inline void set_FRCE_ON_vreg_and_chip_reset() volatile
    {
        FRCE_ON |= 1u << 13u;
    }

    inline void clear_FRCE_ON_vreg_and_chip_reset() volatile
    {
        FRCE_ON &= ~(1u << 13u);
    }

    inline void toggle_FRCE_ON_vreg_and_chip_reset() volatile
    {
        FRCE_ON ^= 1u << 13u;
    }

    inline bool get_FRCE_ON_sio() volatile
    {
        return FRCE_ON & (1u << 14u);
    }

    inline void set_FRCE_ON_sio() volatile
    {
        FRCE_ON |= 1u << 14u;
    }

    inline void clear_FRCE_ON_sio() volatile
    {
        FRCE_ON &= ~(1u << 14u);
    }

    inline void toggle_FRCE_ON_sio() volatile
    {
        FRCE_ON ^= 1u << 14u;
    }

    inline bool get_FRCE_ON_proc0() volatile
    {
        return FRCE_ON & (1u << 15u);
    }

    inline void set_FRCE_ON_proc0() volatile
    {
        FRCE_ON |= 1u << 15u;
    }

    inline void clear_FRCE_ON_proc0() volatile
    {
        FRCE_ON &= ~(1u << 15u);
    }

    inline void toggle_FRCE_ON_proc0() volatile
    {
        FRCE_ON ^= 1u << 15u;
    }

    inline bool get_FRCE_ON_proc1() volatile
    {
        return FRCE_ON & (1u << 16u);
    }

    inline void set_FRCE_ON_proc1() volatile
    {
        FRCE_ON |= 1u << 16u;
    }

    inline void clear_FRCE_ON_proc1() volatile
    {
        FRCE_ON &= ~(1u << 16u);
    }

    inline void toggle_FRCE_ON_proc1() volatile
    {
        FRCE_ON ^= 1u << 16u;
    }

    inline void get_FRCE_ON(bool &rosc, bool &xosc, bool &clocks, bool &resets,
                            bool &busfabric, bool &rom, bool &sram0,
                            bool &sram1, bool &sram2, bool &sram3, bool &sram4,
                            bool &sram5, bool &xip, bool &vreg_and_chip_reset,
                            bool &sio, bool &proc0, bool &proc1) volatile
    {
        uint32_t curr = FRCE_ON;

        rosc = curr & (1u << 0u);
        xosc = curr & (1u << 1u);
        clocks = curr & (1u << 2u);
        resets = curr & (1u << 3u);
        busfabric = curr & (1u << 4u);
        rom = curr & (1u << 5u);
        sram0 = curr & (1u << 6u);
        sram1 = curr & (1u << 7u);
        sram2 = curr & (1u << 8u);
        sram3 = curr & (1u << 9u);
        sram4 = curr & (1u << 10u);
        sram5 = curr & (1u << 11u);
        xip = curr & (1u << 12u);
        vreg_and_chip_reset = curr & (1u << 13u);
        sio = curr & (1u << 14u);
        proc0 = curr & (1u << 15u);
        proc1 = curr & (1u << 16u);
    }

    inline void set_FRCE_ON(bool rosc, bool xosc, bool clocks, bool resets,
                            bool busfabric, bool rom, bool sram0, bool sram1,
                            bool sram2, bool sram3, bool sram4, bool sram5,
                            bool xip, bool vreg_and_chip_reset, bool sio,
                            bool proc0, bool proc1) volatile
    {
        uint32_t curr = FRCE_ON;

        curr &= ~(0b1u << 0u);
        curr |= (rosc & 0b1u) << 0u;
        curr &= ~(0b1u << 1u);
        curr |= (xosc & 0b1u) << 1u;
        curr &= ~(0b1u << 2u);
        curr |= (clocks & 0b1u) << 2u;
        curr &= ~(0b1u << 3u);
        curr |= (resets & 0b1u) << 3u;
        curr &= ~(0b1u << 4u);
        curr |= (busfabric & 0b1u) << 4u;
        curr &= ~(0b1u << 5u);
        curr |= (rom & 0b1u) << 5u;
        curr &= ~(0b1u << 6u);
        curr |= (sram0 & 0b1u) << 6u;
        curr &= ~(0b1u << 7u);
        curr |= (sram1 & 0b1u) << 7u;
        curr &= ~(0b1u << 8u);
        curr |= (sram2 & 0b1u) << 8u;
        curr &= ~(0b1u << 9u);
        curr |= (sram3 & 0b1u) << 9u;
        curr &= ~(0b1u << 10u);
        curr |= (sram4 & 0b1u) << 10u;
        curr &= ~(0b1u << 11u);
        curr |= (sram5 & 0b1u) << 11u;
        curr &= ~(0b1u << 12u);
        curr |= (xip & 0b1u) << 12u;
        curr &= ~(0b1u << 13u);
        curr |= (vreg_and_chip_reset & 0b1u) << 13u;
        curr &= ~(0b1u << 14u);
        curr |= (sio & 0b1u) << 14u;
        curr &= ~(0b1u << 15u);
        curr |= (proc0 & 0b1u) << 15u;
        curr &= ~(0b1u << 16u);
        curr |= (proc1 & 0b1u) << 16u;

        FRCE_ON = curr;
    }

    inline bool get_FRCE_OFF_rosc() volatile
    {
        return FRCE_OFF & (1u << 0u);
    }

    inline void set_FRCE_OFF_rosc() volatile
    {
        FRCE_OFF |= 1u << 0u;
    }

    inline void clear_FRCE_OFF_rosc() volatile
    {
        FRCE_OFF &= ~(1u << 0u);
    }

    inline void toggle_FRCE_OFF_rosc() volatile
    {
        FRCE_OFF ^= 1u << 0u;
    }

    inline bool get_FRCE_OFF_xosc() volatile
    {
        return FRCE_OFF & (1u << 1u);
    }

    inline void set_FRCE_OFF_xosc() volatile
    {
        FRCE_OFF |= 1u << 1u;
    }

    inline void clear_FRCE_OFF_xosc() volatile
    {
        FRCE_OFF &= ~(1u << 1u);
    }

    inline void toggle_FRCE_OFF_xosc() volatile
    {
        FRCE_OFF ^= 1u << 1u;
    }

    inline bool get_FRCE_OFF_clocks() volatile
    {
        return FRCE_OFF & (1u << 2u);
    }

    inline void set_FRCE_OFF_clocks() volatile
    {
        FRCE_OFF |= 1u << 2u;
    }

    inline void clear_FRCE_OFF_clocks() volatile
    {
        FRCE_OFF &= ~(1u << 2u);
    }

    inline void toggle_FRCE_OFF_clocks() volatile
    {
        FRCE_OFF ^= 1u << 2u;
    }

    inline bool get_FRCE_OFF_resets() volatile
    {
        return FRCE_OFF & (1u << 3u);
    }

    inline void set_FRCE_OFF_resets() volatile
    {
        FRCE_OFF |= 1u << 3u;
    }

    inline void clear_FRCE_OFF_resets() volatile
    {
        FRCE_OFF &= ~(1u << 3u);
    }

    inline void toggle_FRCE_OFF_resets() volatile
    {
        FRCE_OFF ^= 1u << 3u;
    }

    inline bool get_FRCE_OFF_busfabric() volatile
    {
        return FRCE_OFF & (1u << 4u);
    }

    inline void set_FRCE_OFF_busfabric() volatile
    {
        FRCE_OFF |= 1u << 4u;
    }

    inline void clear_FRCE_OFF_busfabric() volatile
    {
        FRCE_OFF &= ~(1u << 4u);
    }

    inline void toggle_FRCE_OFF_busfabric() volatile
    {
        FRCE_OFF ^= 1u << 4u;
    }

    inline bool get_FRCE_OFF_rom() volatile
    {
        return FRCE_OFF & (1u << 5u);
    }

    inline void set_FRCE_OFF_rom() volatile
    {
        FRCE_OFF |= 1u << 5u;
    }

    inline void clear_FRCE_OFF_rom() volatile
    {
        FRCE_OFF &= ~(1u << 5u);
    }

    inline void toggle_FRCE_OFF_rom() volatile
    {
        FRCE_OFF ^= 1u << 5u;
    }

    inline bool get_FRCE_OFF_sram0() volatile
    {
        return FRCE_OFF & (1u << 6u);
    }

    inline void set_FRCE_OFF_sram0() volatile
    {
        FRCE_OFF |= 1u << 6u;
    }

    inline void clear_FRCE_OFF_sram0() volatile
    {
        FRCE_OFF &= ~(1u << 6u);
    }

    inline void toggle_FRCE_OFF_sram0() volatile
    {
        FRCE_OFF ^= 1u << 6u;
    }

    inline bool get_FRCE_OFF_sram1() volatile
    {
        return FRCE_OFF & (1u << 7u);
    }

    inline void set_FRCE_OFF_sram1() volatile
    {
        FRCE_OFF |= 1u << 7u;
    }

    inline void clear_FRCE_OFF_sram1() volatile
    {
        FRCE_OFF &= ~(1u << 7u);
    }

    inline void toggle_FRCE_OFF_sram1() volatile
    {
        FRCE_OFF ^= 1u << 7u;
    }

    inline bool get_FRCE_OFF_sram2() volatile
    {
        return FRCE_OFF & (1u << 8u);
    }

    inline void set_FRCE_OFF_sram2() volatile
    {
        FRCE_OFF |= 1u << 8u;
    }

    inline void clear_FRCE_OFF_sram2() volatile
    {
        FRCE_OFF &= ~(1u << 8u);
    }

    inline void toggle_FRCE_OFF_sram2() volatile
    {
        FRCE_OFF ^= 1u << 8u;
    }

    inline bool get_FRCE_OFF_sram3() volatile
    {
        return FRCE_OFF & (1u << 9u);
    }

    inline void set_FRCE_OFF_sram3() volatile
    {
        FRCE_OFF |= 1u << 9u;
    }

    inline void clear_FRCE_OFF_sram3() volatile
    {
        FRCE_OFF &= ~(1u << 9u);
    }

    inline void toggle_FRCE_OFF_sram3() volatile
    {
        FRCE_OFF ^= 1u << 9u;
    }

    inline bool get_FRCE_OFF_sram4() volatile
    {
        return FRCE_OFF & (1u << 10u);
    }

    inline void set_FRCE_OFF_sram4() volatile
    {
        FRCE_OFF |= 1u << 10u;
    }

    inline void clear_FRCE_OFF_sram4() volatile
    {
        FRCE_OFF &= ~(1u << 10u);
    }

    inline void toggle_FRCE_OFF_sram4() volatile
    {
        FRCE_OFF ^= 1u << 10u;
    }

    inline bool get_FRCE_OFF_sram5() volatile
    {
        return FRCE_OFF & (1u << 11u);
    }

    inline void set_FRCE_OFF_sram5() volatile
    {
        FRCE_OFF |= 1u << 11u;
    }

    inline void clear_FRCE_OFF_sram5() volatile
    {
        FRCE_OFF &= ~(1u << 11u);
    }

    inline void toggle_FRCE_OFF_sram5() volatile
    {
        FRCE_OFF ^= 1u << 11u;
    }

    inline bool get_FRCE_OFF_xip() volatile
    {
        return FRCE_OFF & (1u << 12u);
    }

    inline void set_FRCE_OFF_xip() volatile
    {
        FRCE_OFF |= 1u << 12u;
    }

    inline void clear_FRCE_OFF_xip() volatile
    {
        FRCE_OFF &= ~(1u << 12u);
    }

    inline void toggle_FRCE_OFF_xip() volatile
    {
        FRCE_OFF ^= 1u << 12u;
    }

    inline bool get_FRCE_OFF_vreg_and_chip_reset() volatile
    {
        return FRCE_OFF & (1u << 13u);
    }

    inline void set_FRCE_OFF_vreg_and_chip_reset() volatile
    {
        FRCE_OFF |= 1u << 13u;
    }

    inline void clear_FRCE_OFF_vreg_and_chip_reset() volatile
    {
        FRCE_OFF &= ~(1u << 13u);
    }

    inline void toggle_FRCE_OFF_vreg_and_chip_reset() volatile
    {
        FRCE_OFF ^= 1u << 13u;
    }

    inline bool get_FRCE_OFF_sio() volatile
    {
        return FRCE_OFF & (1u << 14u);
    }

    inline void set_FRCE_OFF_sio() volatile
    {
        FRCE_OFF |= 1u << 14u;
    }

    inline void clear_FRCE_OFF_sio() volatile
    {
        FRCE_OFF &= ~(1u << 14u);
    }

    inline void toggle_FRCE_OFF_sio() volatile
    {
        FRCE_OFF ^= 1u << 14u;
    }

    inline bool get_FRCE_OFF_proc0() volatile
    {
        return FRCE_OFF & (1u << 15u);
    }

    inline void set_FRCE_OFF_proc0() volatile
    {
        FRCE_OFF |= 1u << 15u;
    }

    inline void clear_FRCE_OFF_proc0() volatile
    {
        FRCE_OFF &= ~(1u << 15u);
    }

    inline void toggle_FRCE_OFF_proc0() volatile
    {
        FRCE_OFF ^= 1u << 15u;
    }

    inline bool get_FRCE_OFF_proc1() volatile
    {
        return FRCE_OFF & (1u << 16u);
    }

    inline void set_FRCE_OFF_proc1() volatile
    {
        FRCE_OFF |= 1u << 16u;
    }

    inline void clear_FRCE_OFF_proc1() volatile
    {
        FRCE_OFF &= ~(1u << 16u);
    }

    inline void toggle_FRCE_OFF_proc1() volatile
    {
        FRCE_OFF ^= 1u << 16u;
    }

    inline void get_FRCE_OFF(bool &rosc, bool &xosc, bool &clocks,
                             bool &resets, bool &busfabric, bool &rom,
                             bool &sram0, bool &sram1, bool &sram2,
                             bool &sram3, bool &sram4, bool &sram5, bool &xip,
                             bool &vreg_and_chip_reset, bool &sio, bool &proc0,
                             bool &proc1) volatile
    {
        uint32_t curr = FRCE_OFF;

        rosc = curr & (1u << 0u);
        xosc = curr & (1u << 1u);
        clocks = curr & (1u << 2u);
        resets = curr & (1u << 3u);
        busfabric = curr & (1u << 4u);
        rom = curr & (1u << 5u);
        sram0 = curr & (1u << 6u);
        sram1 = curr & (1u << 7u);
        sram2 = curr & (1u << 8u);
        sram3 = curr & (1u << 9u);
        sram4 = curr & (1u << 10u);
        sram5 = curr & (1u << 11u);
        xip = curr & (1u << 12u);
        vreg_and_chip_reset = curr & (1u << 13u);
        sio = curr & (1u << 14u);
        proc0 = curr & (1u << 15u);
        proc1 = curr & (1u << 16u);
    }

    inline void set_FRCE_OFF(bool rosc, bool xosc, bool clocks, bool resets,
                             bool busfabric, bool rom, bool sram0, bool sram1,
                             bool sram2, bool sram3, bool sram4, bool sram5,
                             bool xip, bool vreg_and_chip_reset, bool sio,
                             bool proc0, bool proc1) volatile
    {
        uint32_t curr = FRCE_OFF;

        curr &= ~(0b1u << 0u);
        curr |= (rosc & 0b1u) << 0u;
        curr &= ~(0b1u << 1u);
        curr |= (xosc & 0b1u) << 1u;
        curr &= ~(0b1u << 2u);
        curr |= (clocks & 0b1u) << 2u;
        curr &= ~(0b1u << 3u);
        curr |= (resets & 0b1u) << 3u;
        curr &= ~(0b1u << 4u);
        curr |= (busfabric & 0b1u) << 4u;
        curr &= ~(0b1u << 5u);
        curr |= (rom & 0b1u) << 5u;
        curr &= ~(0b1u << 6u);
        curr |= (sram0 & 0b1u) << 6u;
        curr &= ~(0b1u << 7u);
        curr |= (sram1 & 0b1u) << 7u;
        curr &= ~(0b1u << 8u);
        curr |= (sram2 & 0b1u) << 8u;
        curr &= ~(0b1u << 9u);
        curr |= (sram3 & 0b1u) << 9u;
        curr &= ~(0b1u << 10u);
        curr |= (sram4 & 0b1u) << 10u;
        curr &= ~(0b1u << 11u);
        curr |= (sram5 & 0b1u) << 11u;
        curr &= ~(0b1u << 12u);
        curr |= (xip & 0b1u) << 12u;
        curr &= ~(0b1u << 13u);
        curr |= (vreg_and_chip_reset & 0b1u) << 13u;
        curr &= ~(0b1u << 14u);
        curr |= (sio & 0b1u) << 14u;
        curr &= ~(0b1u << 15u);
        curr |= (proc0 & 0b1u) << 15u;
        curr &= ~(0b1u << 16u);
        curr |= (proc1 & 0b1u) << 16u;

        FRCE_OFF = curr;
    }

    inline bool get_WDSEL_rosc() volatile
    {
        return WDSEL & (1u << 0u);
    }

    inline void set_WDSEL_rosc() volatile
    {
        WDSEL |= 1u << 0u;
    }

    inline void clear_WDSEL_rosc() volatile
    {
        WDSEL &= ~(1u << 0u);
    }

    inline void toggle_WDSEL_rosc() volatile
    {
        WDSEL ^= 1u << 0u;
    }

    inline bool get_WDSEL_xosc() volatile
    {
        return WDSEL & (1u << 1u);
    }

    inline void set_WDSEL_xosc() volatile
    {
        WDSEL |= 1u << 1u;
    }

    inline void clear_WDSEL_xosc() volatile
    {
        WDSEL &= ~(1u << 1u);
    }

    inline void toggle_WDSEL_xosc() volatile
    {
        WDSEL ^= 1u << 1u;
    }

    inline bool get_WDSEL_clocks() volatile
    {
        return WDSEL & (1u << 2u);
    }

    inline void set_WDSEL_clocks() volatile
    {
        WDSEL |= 1u << 2u;
    }

    inline void clear_WDSEL_clocks() volatile
    {
        WDSEL &= ~(1u << 2u);
    }

    inline void toggle_WDSEL_clocks() volatile
    {
        WDSEL ^= 1u << 2u;
    }

    inline bool get_WDSEL_resets() volatile
    {
        return WDSEL & (1u << 3u);
    }

    inline void set_WDSEL_resets() volatile
    {
        WDSEL |= 1u << 3u;
    }

    inline void clear_WDSEL_resets() volatile
    {
        WDSEL &= ~(1u << 3u);
    }

    inline void toggle_WDSEL_resets() volatile
    {
        WDSEL ^= 1u << 3u;
    }

    inline bool get_WDSEL_busfabric() volatile
    {
        return WDSEL & (1u << 4u);
    }

    inline void set_WDSEL_busfabric() volatile
    {
        WDSEL |= 1u << 4u;
    }

    inline void clear_WDSEL_busfabric() volatile
    {
        WDSEL &= ~(1u << 4u);
    }

    inline void toggle_WDSEL_busfabric() volatile
    {
        WDSEL ^= 1u << 4u;
    }

    inline bool get_WDSEL_rom() volatile
    {
        return WDSEL & (1u << 5u);
    }

    inline void set_WDSEL_rom() volatile
    {
        WDSEL |= 1u << 5u;
    }

    inline void clear_WDSEL_rom() volatile
    {
        WDSEL &= ~(1u << 5u);
    }

    inline void toggle_WDSEL_rom() volatile
    {
        WDSEL ^= 1u << 5u;
    }

    inline bool get_WDSEL_sram0() volatile
    {
        return WDSEL & (1u << 6u);
    }

    inline void set_WDSEL_sram0() volatile
    {
        WDSEL |= 1u << 6u;
    }

    inline void clear_WDSEL_sram0() volatile
    {
        WDSEL &= ~(1u << 6u);
    }

    inline void toggle_WDSEL_sram0() volatile
    {
        WDSEL ^= 1u << 6u;
    }

    inline bool get_WDSEL_sram1() volatile
    {
        return WDSEL & (1u << 7u);
    }

    inline void set_WDSEL_sram1() volatile
    {
        WDSEL |= 1u << 7u;
    }

    inline void clear_WDSEL_sram1() volatile
    {
        WDSEL &= ~(1u << 7u);
    }

    inline void toggle_WDSEL_sram1() volatile
    {
        WDSEL ^= 1u << 7u;
    }

    inline bool get_WDSEL_sram2() volatile
    {
        return WDSEL & (1u << 8u);
    }

    inline void set_WDSEL_sram2() volatile
    {
        WDSEL |= 1u << 8u;
    }

    inline void clear_WDSEL_sram2() volatile
    {
        WDSEL &= ~(1u << 8u);
    }

    inline void toggle_WDSEL_sram2() volatile
    {
        WDSEL ^= 1u << 8u;
    }

    inline bool get_WDSEL_sram3() volatile
    {
        return WDSEL & (1u << 9u);
    }

    inline void set_WDSEL_sram3() volatile
    {
        WDSEL |= 1u << 9u;
    }

    inline void clear_WDSEL_sram3() volatile
    {
        WDSEL &= ~(1u << 9u);
    }

    inline void toggle_WDSEL_sram3() volatile
    {
        WDSEL ^= 1u << 9u;
    }

    inline bool get_WDSEL_sram4() volatile
    {
        return WDSEL & (1u << 10u);
    }

    inline void set_WDSEL_sram4() volatile
    {
        WDSEL |= 1u << 10u;
    }

    inline void clear_WDSEL_sram4() volatile
    {
        WDSEL &= ~(1u << 10u);
    }

    inline void toggle_WDSEL_sram4() volatile
    {
        WDSEL ^= 1u << 10u;
    }

    inline bool get_WDSEL_sram5() volatile
    {
        return WDSEL & (1u << 11u);
    }

    inline void set_WDSEL_sram5() volatile
    {
        WDSEL |= 1u << 11u;
    }

    inline void clear_WDSEL_sram5() volatile
    {
        WDSEL &= ~(1u << 11u);
    }

    inline void toggle_WDSEL_sram5() volatile
    {
        WDSEL ^= 1u << 11u;
    }

    inline bool get_WDSEL_xip() volatile
    {
        return WDSEL & (1u << 12u);
    }

    inline void set_WDSEL_xip() volatile
    {
        WDSEL |= 1u << 12u;
    }

    inline void clear_WDSEL_xip() volatile
    {
        WDSEL &= ~(1u << 12u);
    }

    inline void toggle_WDSEL_xip() volatile
    {
        WDSEL ^= 1u << 12u;
    }

    inline bool get_WDSEL_vreg_and_chip_reset() volatile
    {
        return WDSEL & (1u << 13u);
    }

    inline void set_WDSEL_vreg_and_chip_reset() volatile
    {
        WDSEL |= 1u << 13u;
    }

    inline void clear_WDSEL_vreg_and_chip_reset() volatile
    {
        WDSEL &= ~(1u << 13u);
    }

    inline void toggle_WDSEL_vreg_and_chip_reset() volatile
    {
        WDSEL ^= 1u << 13u;
    }

    inline bool get_WDSEL_sio() volatile
    {
        return WDSEL & (1u << 14u);
    }

    inline void set_WDSEL_sio() volatile
    {
        WDSEL |= 1u << 14u;
    }

    inline void clear_WDSEL_sio() volatile
    {
        WDSEL &= ~(1u << 14u);
    }

    inline void toggle_WDSEL_sio() volatile
    {
        WDSEL ^= 1u << 14u;
    }

    inline bool get_WDSEL_proc0() volatile
    {
        return WDSEL & (1u << 15u);
    }

    inline void set_WDSEL_proc0() volatile
    {
        WDSEL |= 1u << 15u;
    }

    inline void clear_WDSEL_proc0() volatile
    {
        WDSEL &= ~(1u << 15u);
    }

    inline void toggle_WDSEL_proc0() volatile
    {
        WDSEL ^= 1u << 15u;
    }

    inline bool get_WDSEL_proc1() volatile
    {
        return WDSEL & (1u << 16u);
    }

    inline void set_WDSEL_proc1() volatile
    {
        WDSEL |= 1u << 16u;
    }

    inline void clear_WDSEL_proc1() volatile
    {
        WDSEL &= ~(1u << 16u);
    }

    inline void toggle_WDSEL_proc1() volatile
    {
        WDSEL ^= 1u << 16u;
    }

    inline void get_WDSEL(bool &rosc, bool &xosc, bool &clocks, bool &resets,
                          bool &busfabric, bool &rom, bool &sram0, bool &sram1,
                          bool &sram2, bool &sram3, bool &sram4, bool &sram5,
                          bool &xip, bool &vreg_and_chip_reset, bool &sio,
                          bool &proc0, bool &proc1) volatile
    {
        uint32_t curr = WDSEL;

        rosc = curr & (1u << 0u);
        xosc = curr & (1u << 1u);
        clocks = curr & (1u << 2u);
        resets = curr & (1u << 3u);
        busfabric = curr & (1u << 4u);
        rom = curr & (1u << 5u);
        sram0 = curr & (1u << 6u);
        sram1 = curr & (1u << 7u);
        sram2 = curr & (1u << 8u);
        sram3 = curr & (1u << 9u);
        sram4 = curr & (1u << 10u);
        sram5 = curr & (1u << 11u);
        xip = curr & (1u << 12u);
        vreg_and_chip_reset = curr & (1u << 13u);
        sio = curr & (1u << 14u);
        proc0 = curr & (1u << 15u);
        proc1 = curr & (1u << 16u);
    }

    inline void set_WDSEL(bool rosc, bool xosc, bool clocks, bool resets,
                          bool busfabric, bool rom, bool sram0, bool sram1,
                          bool sram2, bool sram3, bool sram4, bool sram5,
                          bool xip, bool vreg_and_chip_reset, bool sio,
                          bool proc0, bool proc1) volatile
    {
        uint32_t curr = WDSEL;

        curr &= ~(0b1u << 0u);
        curr |= (rosc & 0b1u) << 0u;
        curr &= ~(0b1u << 1u);
        curr |= (xosc & 0b1u) << 1u;
        curr &= ~(0b1u << 2u);
        curr |= (clocks & 0b1u) << 2u;
        curr &= ~(0b1u << 3u);
        curr |= (resets & 0b1u) << 3u;
        curr &= ~(0b1u << 4u);
        curr |= (busfabric & 0b1u) << 4u;
        curr &= ~(0b1u << 5u);
        curr |= (rom & 0b1u) << 5u;
        curr &= ~(0b1u << 6u);
        curr |= (sram0 & 0b1u) << 6u;
        curr &= ~(0b1u << 7u);
        curr |= (sram1 & 0b1u) << 7u;
        curr &= ~(0b1u << 8u);
        curr |= (sram2 & 0b1u) << 8u;
        curr &= ~(0b1u << 9u);
        curr |= (sram3 & 0b1u) << 9u;
        curr &= ~(0b1u << 10u);
        curr |= (sram4 & 0b1u) << 10u;
        curr &= ~(0b1u << 11u);
        curr |= (sram5 & 0b1u) << 11u;
        curr &= ~(0b1u << 12u);
        curr |= (xip & 0b1u) << 12u;
        curr &= ~(0b1u << 13u);
        curr |= (vreg_and_chip_reset & 0b1u) << 13u;
        curr &= ~(0b1u << 14u);
        curr |= (sio & 0b1u) << 14u;
        curr &= ~(0b1u << 15u);
        curr |= (proc0 & 0b1u) << 15u;
        curr &= ~(0b1u << 16u);
        curr |= (proc1 & 0b1u) << 16u;

        WDSEL = curr;
    }

    inline bool get_DONE_rosc() volatile
    {
        return DONE & (1u << 0u);
    }

    inline bool get_DONE_xosc() volatile
    {
        return DONE & (1u << 1u);
    }

    inline bool get_DONE_clocks() volatile
    {
        return DONE & (1u << 2u);
    }

    inline bool get_DONE_resets() volatile
    {
        return DONE & (1u << 3u);
    }

    inline bool get_DONE_busfabric() volatile
    {
        return DONE & (1u << 4u);
    }

    inline bool get_DONE_rom() volatile
    {
        return DONE & (1u << 5u);
    }

    inline bool get_DONE_sram0() volatile
    {
        return DONE & (1u << 6u);
    }

    inline bool get_DONE_sram1() volatile
    {
        return DONE & (1u << 7u);
    }

    inline bool get_DONE_sram2() volatile
    {
        return DONE & (1u << 8u);
    }

    inline bool get_DONE_sram3() volatile
    {
        return DONE & (1u << 9u);
    }

    inline bool get_DONE_sram4() volatile
    {
        return DONE & (1u << 10u);
    }

    inline bool get_DONE_sram5() volatile
    {
        return DONE & (1u << 11u);
    }

    inline bool get_DONE_xip() volatile
    {
        return DONE & (1u << 12u);
    }

    inline bool get_DONE_vreg_and_chip_reset() volatile
    {
        return DONE & (1u << 13u);
    }

    inline bool get_DONE_sio() volatile
    {
        return DONE & (1u << 14u);
    }

    inline bool get_DONE_proc0() volatile
    {
        return DONE & (1u << 15u);
    }

    inline bool get_DONE_proc1() volatile
    {
        return DONE & (1u << 16u);
    }

    inline void get_DONE(bool &rosc, bool &xosc, bool &clocks, bool &resets,
                         bool &busfabric, bool &rom, bool &sram0, bool &sram1,
                         bool &sram2, bool &sram3, bool &sram4, bool &sram5,
                         bool &xip, bool &vreg_and_chip_reset, bool &sio,
                         bool &proc0, bool &proc1) volatile
    {
        uint32_t curr = DONE;

        rosc = curr & (1u << 0u);
        xosc = curr & (1u << 1u);
        clocks = curr & (1u << 2u);
        resets = curr & (1u << 3u);
        busfabric = curr & (1u << 4u);
        rom = curr & (1u << 5u);
        sram0 = curr & (1u << 6u);
        sram1 = curr & (1u << 7u);
        sram2 = curr & (1u << 8u);
        sram3 = curr & (1u << 9u);
        sram4 = curr & (1u << 10u);
        sram5 = curr & (1u << 11u);
        xip = curr & (1u << 12u);
        vreg_and_chip_reset = curr & (1u << 13u);
        sio = curr & (1u << 14u);
        proc0 = curr & (1u << 15u);
        proc1 = curr & (1u << 16u);
    }
};

static_assert(sizeof(psm) == psm::size);

static volatile psm *const PSM = reinterpret_cast<psm *>(0x40010000);

}; // namespace RP2040