Program Listing for File ppb.h#
↰ Return to documentation for file (src/generated/structs/ppb.h)
#pragma once
#include "../ifgen/common.h"
namespace RP2040
{
struct [[gnu::packed]] ppb
{
/* Constant attributes. */
static constexpr std::size_t size = 60836;
/* Fields. */
static constexpr std::size_t reserved_padding0_length = 14340;
const uint32_t reserved_padding0[reserved_padding0_length] = {};
uint32_t SYST_CSR;
uint32_t SYST_RVR;
uint32_t SYST_CVR;
const uint32_t SYST_CALIB =
{};
static constexpr std::size_t reserved_padding1_length = 56;
const uint32_t reserved_padding1[reserved_padding1_length] = {};
uint32_t NVIC_ISER;
static constexpr std::size_t reserved_padding2_length = 31;
const uint32_t reserved_padding2[reserved_padding2_length] = {};
uint32_t NVIC_ICER;
static constexpr std::size_t reserved_padding3_length = 31;
const uint32_t reserved_padding3[reserved_padding3_length] = {};
uint32_t
NVIC_ISPR;
static constexpr std::size_t reserved_padding4_length = 31;
const uint32_t reserved_padding4[reserved_padding4_length] = {};
uint32_t NVIC_ICPR;
static constexpr std::size_t reserved_padding5_length = 95;
const uint32_t reserved_padding5[reserved_padding5_length] = {};
uint32_t NVIC_IPR0;
uint32_t NVIC_IPR1;
uint32_t NVIC_IPR2;
uint32_t NVIC_IPR3;
uint32_t NVIC_IPR4;
uint32_t NVIC_IPR5;
uint32_t NVIC_IPR6;
uint32_t NVIC_IPR7;
static constexpr std::size_t reserved_padding6_length = 568;
const uint32_t reserved_padding6[reserved_padding6_length] = {};
const uint32_t CPUID =
{};
uint32_t ICSR;
uint32_t VTOR;
uint32_t AIRCR;
uint32_t
SCR;
const uint32_t CCR =
{};
const uint32_t reserved_padding7 = {};
uint32_t SHPR2;
uint32_t
SHPR3;
uint32_t SHCSR;
static constexpr std::size_t reserved_padding8_length = 26;
const uint32_t reserved_padding8[reserved_padding8_length] = {};
const uint32_t MPU_TYPE =
{};
uint32_t MPU_CTRL;
uint32_t
MPU_RNR;
uint32_t MPU_RBAR;
uint32_t MPU_RASR;
/* Methods. */
inline bool get_SYST_CSR_ENABLE() volatile
{
return SYST_CSR & (1u << 0u);
}
inline void set_SYST_CSR_ENABLE() volatile
{
SYST_CSR |= 1u << 0u;
}
inline void clear_SYST_CSR_ENABLE() volatile
{
SYST_CSR &= ~(1u << 0u);
}
inline void toggle_SYST_CSR_ENABLE() volatile
{
SYST_CSR ^= 1u << 0u;
}
inline bool get_SYST_CSR_TICKINT() volatile
{
return SYST_CSR & (1u << 1u);
}
inline void set_SYST_CSR_TICKINT() volatile
{
SYST_CSR |= 1u << 1u;
}
inline void clear_SYST_CSR_TICKINT() volatile
{
SYST_CSR &= ~(1u << 1u);
}
inline void toggle_SYST_CSR_TICKINT() volatile
{
SYST_CSR ^= 1u << 1u;
}
inline bool get_SYST_CSR_CLKSOURCE() volatile
{
return SYST_CSR & (1u << 2u);
}
inline void set_SYST_CSR_CLKSOURCE() volatile
{
SYST_CSR |= 1u << 2u;
}
inline void clear_SYST_CSR_CLKSOURCE() volatile
{
SYST_CSR &= ~(1u << 2u);
}
inline void toggle_SYST_CSR_CLKSOURCE() volatile
{
SYST_CSR ^= 1u << 2u;
}
inline bool get_SYST_CSR_COUNTFLAG() volatile
{
return SYST_CSR & (1u << 16u);
}
inline void get_SYST_CSR(bool &ENABLE, bool &TICKINT, bool &CLKSOURCE,
bool &COUNTFLAG) volatile
{
uint32_t curr = SYST_CSR;
ENABLE = curr & (1u << 0u);
TICKINT = curr & (1u << 1u);
CLKSOURCE = curr & (1u << 2u);
COUNTFLAG = curr & (1u << 16u);
}
inline void set_SYST_CSR(bool ENABLE, bool TICKINT,
bool CLKSOURCE) volatile
{
uint32_t curr = SYST_CSR;
curr &= ~(0b1u << 0u);
curr |= (ENABLE & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (TICKINT & 0b1u) << 1u;
curr &= ~(0b1u << 2u);
curr |= (CLKSOURCE & 0b1u) << 2u;
SYST_CSR = curr;
}
inline uint32_t get_SYST_RVR_RELOAD() volatile
{
return (SYST_RVR >> 0u) & 0b111111111111111111111111u;
}
inline void set_SYST_RVR_RELOAD(uint32_t value) volatile
{
uint32_t curr = SYST_RVR;
curr &= ~(0b111111111111111111111111u << 0u);
curr |= (value & 0b111111111111111111111111u) << 0u;
SYST_RVR = curr;
}
inline uint32_t get_SYST_CVR_CURRENT() volatile
{
return (SYST_CVR >> 0u) & 0b111111111111111111111111u;
}
inline void set_SYST_CVR_CURRENT(uint32_t value) volatile
{
uint32_t curr = SYST_CVR;
curr &= ~(0b111111111111111111111111u << 0u);
curr |= (value & 0b111111111111111111111111u) << 0u;
SYST_CVR = curr;
}
inline uint32_t get_SYST_CALIB_TENMS() volatile
{
return (SYST_CALIB >> 0u) & 0b111111111111111111111111u;
}
inline bool get_SYST_CALIB_SKEW() volatile
{
return SYST_CALIB & (1u << 30u);
}
inline bool get_SYST_CALIB_NOREF() volatile
{
return SYST_CALIB & (1u << 31u);
}
inline void get_SYST_CALIB(uint32_t &TENMS, bool &SKEW,
bool &NOREF) volatile
{
uint32_t curr = SYST_CALIB;
TENMS = (curr >> 0u) & 0b111111111111111111111111u;
SKEW = curr & (1u << 30u);
NOREF = curr & (1u << 31u);
}
inline uint32_t get_NVIC_ISER_SETENA() volatile
{
return (NVIC_ISER >> 0u) & 0b11111111111111111111111111111111u;
}
inline void set_NVIC_ISER_SETENA(uint32_t value) volatile
{
uint32_t curr = NVIC_ISER;
curr &= ~(0b11111111111111111111111111111111u << 0u);
curr |= (value & 0b11111111111111111111111111111111u) << 0u;
NVIC_ISER = curr;
}
inline uint32_t get_NVIC_ICER_CLRENA() volatile
{
return (NVIC_ICER >> 0u) & 0b11111111111111111111111111111111u;
}
inline void set_NVIC_ICER_CLRENA(uint32_t value) volatile
{
uint32_t curr = NVIC_ICER;
curr &= ~(0b11111111111111111111111111111111u << 0u);
curr |= (value & 0b11111111111111111111111111111111u) << 0u;
NVIC_ICER = curr;
}
inline uint32_t get_NVIC_ISPR_SETPEND() volatile
{
return (NVIC_ISPR >> 0u) & 0b11111111111111111111111111111111u;
}
inline void set_NVIC_ISPR_SETPEND(uint32_t value) volatile
{
uint32_t curr = NVIC_ISPR;
curr &= ~(0b11111111111111111111111111111111u << 0u);
curr |= (value & 0b11111111111111111111111111111111u) << 0u;
NVIC_ISPR = curr;
}
inline uint32_t get_NVIC_ICPR_CLRPEND() volatile
{
return (NVIC_ICPR >> 0u) & 0b11111111111111111111111111111111u;
}
inline void set_NVIC_ICPR_CLRPEND(uint32_t value) volatile
{
uint32_t curr = NVIC_ICPR;
curr &= ~(0b11111111111111111111111111111111u << 0u);
curr |= (value & 0b11111111111111111111111111111111u) << 0u;
NVIC_ICPR = curr;
}
inline uint8_t get_NVIC_IPR0_IP_0() volatile
{
return (NVIC_IPR0 >> 6u) & 0b11u;
}
inline void set_NVIC_IPR0_IP_0(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR0;
curr &= ~(0b11u << 6u);
curr |= (value & 0b11u) << 6u;
NVIC_IPR0 = curr;
}
inline uint8_t get_NVIC_IPR0_IP_1() volatile
{
return (NVIC_IPR0 >> 14u) & 0b11u;
}
inline void set_NVIC_IPR0_IP_1(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR0;
curr &= ~(0b11u << 14u);
curr |= (value & 0b11u) << 14u;
NVIC_IPR0 = curr;
}
inline uint8_t get_NVIC_IPR0_IP_2() volatile
{
return (NVIC_IPR0 >> 22u) & 0b11u;
}
inline void set_NVIC_IPR0_IP_2(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR0;
curr &= ~(0b11u << 22u);
curr |= (value & 0b11u) << 22u;
NVIC_IPR0 = curr;
}
inline uint8_t get_NVIC_IPR0_IP_3() volatile
{
return (NVIC_IPR0 >> 30u) & 0b11u;
}
inline void set_NVIC_IPR0_IP_3(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR0;
curr &= ~(0b11u << 30u);
curr |= (value & 0b11u) << 30u;
NVIC_IPR0 = curr;
}
inline void get_NVIC_IPR0(uint8_t &IP_0, uint8_t &IP_1, uint8_t &IP_2,
uint8_t &IP_3) volatile
{
uint32_t curr = NVIC_IPR0;
IP_0 = (curr >> 6u) & 0b11u;
IP_1 = (curr >> 14u) & 0b11u;
IP_2 = (curr >> 22u) & 0b11u;
IP_3 = (curr >> 30u) & 0b11u;
}
inline void set_NVIC_IPR0(uint8_t IP_0, uint8_t IP_1, uint8_t IP_2,
uint8_t IP_3) volatile
{
uint32_t curr = NVIC_IPR0;
curr &= ~(0b11u << 6u);
curr |= (IP_0 & 0b11u) << 6u;
curr &= ~(0b11u << 14u);
curr |= (IP_1 & 0b11u) << 14u;
curr &= ~(0b11u << 22u);
curr |= (IP_2 & 0b11u) << 22u;
curr &= ~(0b11u << 30u);
curr |= (IP_3 & 0b11u) << 30u;
NVIC_IPR0 = curr;
}
inline uint8_t get_NVIC_IPR1_IP_4() volatile
{
return (NVIC_IPR1 >> 6u) & 0b11u;
}
inline void set_NVIC_IPR1_IP_4(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR1;
curr &= ~(0b11u << 6u);
curr |= (value & 0b11u) << 6u;
NVIC_IPR1 = curr;
}
inline uint8_t get_NVIC_IPR1_IP_5() volatile
{
return (NVIC_IPR1 >> 14u) & 0b11u;
}
inline void set_NVIC_IPR1_IP_5(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR1;
curr &= ~(0b11u << 14u);
curr |= (value & 0b11u) << 14u;
NVIC_IPR1 = curr;
}
inline uint8_t get_NVIC_IPR1_IP_6() volatile
{
return (NVIC_IPR1 >> 22u) & 0b11u;
}
inline void set_NVIC_IPR1_IP_6(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR1;
curr &= ~(0b11u << 22u);
curr |= (value & 0b11u) << 22u;
NVIC_IPR1 = curr;
}
inline uint8_t get_NVIC_IPR1_IP_7() volatile
{
return (NVIC_IPR1 >> 30u) & 0b11u;
}
inline void set_NVIC_IPR1_IP_7(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR1;
curr &= ~(0b11u << 30u);
curr |= (value & 0b11u) << 30u;
NVIC_IPR1 = curr;
}
inline void get_NVIC_IPR1(uint8_t &IP_4, uint8_t &IP_5, uint8_t &IP_6,
uint8_t &IP_7) volatile
{
uint32_t curr = NVIC_IPR1;
IP_4 = (curr >> 6u) & 0b11u;
IP_5 = (curr >> 14u) & 0b11u;
IP_6 = (curr >> 22u) & 0b11u;
IP_7 = (curr >> 30u) & 0b11u;
}
inline void set_NVIC_IPR1(uint8_t IP_4, uint8_t IP_5, uint8_t IP_6,
uint8_t IP_7) volatile
{
uint32_t curr = NVIC_IPR1;
curr &= ~(0b11u << 6u);
curr |= (IP_4 & 0b11u) << 6u;
curr &= ~(0b11u << 14u);
curr |= (IP_5 & 0b11u) << 14u;
curr &= ~(0b11u << 22u);
curr |= (IP_6 & 0b11u) << 22u;
curr &= ~(0b11u << 30u);
curr |= (IP_7 & 0b11u) << 30u;
NVIC_IPR1 = curr;
}
inline uint8_t get_NVIC_IPR2_IP_8() volatile
{
return (NVIC_IPR2 >> 6u) & 0b11u;
}
inline void set_NVIC_IPR2_IP_8(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR2;
curr &= ~(0b11u << 6u);
curr |= (value & 0b11u) << 6u;
NVIC_IPR2 = curr;
}
inline uint8_t get_NVIC_IPR2_IP_9() volatile
{
return (NVIC_IPR2 >> 14u) & 0b11u;
}
inline void set_NVIC_IPR2_IP_9(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR2;
curr &= ~(0b11u << 14u);
curr |= (value & 0b11u) << 14u;
NVIC_IPR2 = curr;
}
inline uint8_t get_NVIC_IPR2_IP_10() volatile
{
return (NVIC_IPR2 >> 22u) & 0b11u;
}
inline void set_NVIC_IPR2_IP_10(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR2;
curr &= ~(0b11u << 22u);
curr |= (value & 0b11u) << 22u;
NVIC_IPR2 = curr;
}
inline uint8_t get_NVIC_IPR2_IP_11() volatile
{
return (NVIC_IPR2 >> 30u) & 0b11u;
}
inline void set_NVIC_IPR2_IP_11(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR2;
curr &= ~(0b11u << 30u);
curr |= (value & 0b11u) << 30u;
NVIC_IPR2 = curr;
}
inline void get_NVIC_IPR2(uint8_t &IP_8, uint8_t &IP_9, uint8_t &IP_10,
uint8_t &IP_11) volatile
{
uint32_t curr = NVIC_IPR2;
IP_8 = (curr >> 6u) & 0b11u;
IP_9 = (curr >> 14u) & 0b11u;
IP_10 = (curr >> 22u) & 0b11u;
IP_11 = (curr >> 30u) & 0b11u;
}
inline void set_NVIC_IPR2(uint8_t IP_8, uint8_t IP_9, uint8_t IP_10,
uint8_t IP_11) volatile
{
uint32_t curr = NVIC_IPR2;
curr &= ~(0b11u << 6u);
curr |= (IP_8 & 0b11u) << 6u;
curr &= ~(0b11u << 14u);
curr |= (IP_9 & 0b11u) << 14u;
curr &= ~(0b11u << 22u);
curr |= (IP_10 & 0b11u) << 22u;
curr &= ~(0b11u << 30u);
curr |= (IP_11 & 0b11u) << 30u;
NVIC_IPR2 = curr;
}
inline uint8_t get_NVIC_IPR3_IP_12() volatile
{
return (NVIC_IPR3 >> 6u) & 0b11u;
}
inline void set_NVIC_IPR3_IP_12(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR3;
curr &= ~(0b11u << 6u);
curr |= (value & 0b11u) << 6u;
NVIC_IPR3 = curr;
}
inline uint8_t get_NVIC_IPR3_IP_13() volatile
{
return (NVIC_IPR3 >> 14u) & 0b11u;
}
inline void set_NVIC_IPR3_IP_13(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR3;
curr &= ~(0b11u << 14u);
curr |= (value & 0b11u) << 14u;
NVIC_IPR3 = curr;
}
inline uint8_t get_NVIC_IPR3_IP_14() volatile
{
return (NVIC_IPR3 >> 22u) & 0b11u;
}
inline void set_NVIC_IPR3_IP_14(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR3;
curr &= ~(0b11u << 22u);
curr |= (value & 0b11u) << 22u;
NVIC_IPR3 = curr;
}
inline uint8_t get_NVIC_IPR3_IP_15() volatile
{
return (NVIC_IPR3 >> 30u) & 0b11u;
}
inline void set_NVIC_IPR3_IP_15(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR3;
curr &= ~(0b11u << 30u);
curr |= (value & 0b11u) << 30u;
NVIC_IPR3 = curr;
}
inline void get_NVIC_IPR3(uint8_t &IP_12, uint8_t &IP_13, uint8_t &IP_14,
uint8_t &IP_15) volatile
{
uint32_t curr = NVIC_IPR3;
IP_12 = (curr >> 6u) & 0b11u;
IP_13 = (curr >> 14u) & 0b11u;
IP_14 = (curr >> 22u) & 0b11u;
IP_15 = (curr >> 30u) & 0b11u;
}
inline void set_NVIC_IPR3(uint8_t IP_12, uint8_t IP_13, uint8_t IP_14,
uint8_t IP_15) volatile
{
uint32_t curr = NVIC_IPR3;
curr &= ~(0b11u << 6u);
curr |= (IP_12 & 0b11u) << 6u;
curr &= ~(0b11u << 14u);
curr |= (IP_13 & 0b11u) << 14u;
curr &= ~(0b11u << 22u);
curr |= (IP_14 & 0b11u) << 22u;
curr &= ~(0b11u << 30u);
curr |= (IP_15 & 0b11u) << 30u;
NVIC_IPR3 = curr;
}
inline uint8_t get_NVIC_IPR4_IP_16() volatile
{
return (NVIC_IPR4 >> 6u) & 0b11u;
}
inline void set_NVIC_IPR4_IP_16(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR4;
curr &= ~(0b11u << 6u);
curr |= (value & 0b11u) << 6u;
NVIC_IPR4 = curr;
}
inline uint8_t get_NVIC_IPR4_IP_17() volatile
{
return (NVIC_IPR4 >> 14u) & 0b11u;
}
inline void set_NVIC_IPR4_IP_17(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR4;
curr &= ~(0b11u << 14u);
curr |= (value & 0b11u) << 14u;
NVIC_IPR4 = curr;
}
inline uint8_t get_NVIC_IPR4_IP_18() volatile
{
return (NVIC_IPR4 >> 22u) & 0b11u;
}
inline void set_NVIC_IPR4_IP_18(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR4;
curr &= ~(0b11u << 22u);
curr |= (value & 0b11u) << 22u;
NVIC_IPR4 = curr;
}
inline uint8_t get_NVIC_IPR4_IP_19() volatile
{
return (NVIC_IPR4 >> 30u) & 0b11u;
}
inline void set_NVIC_IPR4_IP_19(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR4;
curr &= ~(0b11u << 30u);
curr |= (value & 0b11u) << 30u;
NVIC_IPR4 = curr;
}
inline void get_NVIC_IPR4(uint8_t &IP_16, uint8_t &IP_17, uint8_t &IP_18,
uint8_t &IP_19) volatile
{
uint32_t curr = NVIC_IPR4;
IP_16 = (curr >> 6u) & 0b11u;
IP_17 = (curr >> 14u) & 0b11u;
IP_18 = (curr >> 22u) & 0b11u;
IP_19 = (curr >> 30u) & 0b11u;
}
inline void set_NVIC_IPR4(uint8_t IP_16, uint8_t IP_17, uint8_t IP_18,
uint8_t IP_19) volatile
{
uint32_t curr = NVIC_IPR4;
curr &= ~(0b11u << 6u);
curr |= (IP_16 & 0b11u) << 6u;
curr &= ~(0b11u << 14u);
curr |= (IP_17 & 0b11u) << 14u;
curr &= ~(0b11u << 22u);
curr |= (IP_18 & 0b11u) << 22u;
curr &= ~(0b11u << 30u);
curr |= (IP_19 & 0b11u) << 30u;
NVIC_IPR4 = curr;
}
inline uint8_t get_NVIC_IPR5_IP_20() volatile
{
return (NVIC_IPR5 >> 6u) & 0b11u;
}
inline void set_NVIC_IPR5_IP_20(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR5;
curr &= ~(0b11u << 6u);
curr |= (value & 0b11u) << 6u;
NVIC_IPR5 = curr;
}
inline uint8_t get_NVIC_IPR5_IP_21() volatile
{
return (NVIC_IPR5 >> 14u) & 0b11u;
}
inline void set_NVIC_IPR5_IP_21(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR5;
curr &= ~(0b11u << 14u);
curr |= (value & 0b11u) << 14u;
NVIC_IPR5 = curr;
}
inline uint8_t get_NVIC_IPR5_IP_22() volatile
{
return (NVIC_IPR5 >> 22u) & 0b11u;
}
inline void set_NVIC_IPR5_IP_22(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR5;
curr &= ~(0b11u << 22u);
curr |= (value & 0b11u) << 22u;
NVIC_IPR5 = curr;
}
inline uint8_t get_NVIC_IPR5_IP_23() volatile
{
return (NVIC_IPR5 >> 30u) & 0b11u;
}
inline void set_NVIC_IPR5_IP_23(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR5;
curr &= ~(0b11u << 30u);
curr |= (value & 0b11u) << 30u;
NVIC_IPR5 = curr;
}
inline void get_NVIC_IPR5(uint8_t &IP_20, uint8_t &IP_21, uint8_t &IP_22,
uint8_t &IP_23) volatile
{
uint32_t curr = NVIC_IPR5;
IP_20 = (curr >> 6u) & 0b11u;
IP_21 = (curr >> 14u) & 0b11u;
IP_22 = (curr >> 22u) & 0b11u;
IP_23 = (curr >> 30u) & 0b11u;
}
inline void set_NVIC_IPR5(uint8_t IP_20, uint8_t IP_21, uint8_t IP_22,
uint8_t IP_23) volatile
{
uint32_t curr = NVIC_IPR5;
curr &= ~(0b11u << 6u);
curr |= (IP_20 & 0b11u) << 6u;
curr &= ~(0b11u << 14u);
curr |= (IP_21 & 0b11u) << 14u;
curr &= ~(0b11u << 22u);
curr |= (IP_22 & 0b11u) << 22u;
curr &= ~(0b11u << 30u);
curr |= (IP_23 & 0b11u) << 30u;
NVIC_IPR5 = curr;
}
inline uint8_t get_NVIC_IPR6_IP_24() volatile
{
return (NVIC_IPR6 >> 6u) & 0b11u;
}
inline void set_NVIC_IPR6_IP_24(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR6;
curr &= ~(0b11u << 6u);
curr |= (value & 0b11u) << 6u;
NVIC_IPR6 = curr;
}
inline uint8_t get_NVIC_IPR6_IP_25() volatile
{
return (NVIC_IPR6 >> 14u) & 0b11u;
}
inline void set_NVIC_IPR6_IP_25(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR6;
curr &= ~(0b11u << 14u);
curr |= (value & 0b11u) << 14u;
NVIC_IPR6 = curr;
}
inline uint8_t get_NVIC_IPR6_IP_26() volatile
{
return (NVIC_IPR6 >> 22u) & 0b11u;
}
inline void set_NVIC_IPR6_IP_26(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR6;
curr &= ~(0b11u << 22u);
curr |= (value & 0b11u) << 22u;
NVIC_IPR6 = curr;
}
inline uint8_t get_NVIC_IPR6_IP_27() volatile
{
return (NVIC_IPR6 >> 30u) & 0b11u;
}
inline void set_NVIC_IPR6_IP_27(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR6;
curr &= ~(0b11u << 30u);
curr |= (value & 0b11u) << 30u;
NVIC_IPR6 = curr;
}
inline void get_NVIC_IPR6(uint8_t &IP_24, uint8_t &IP_25, uint8_t &IP_26,
uint8_t &IP_27) volatile
{
uint32_t curr = NVIC_IPR6;
IP_24 = (curr >> 6u) & 0b11u;
IP_25 = (curr >> 14u) & 0b11u;
IP_26 = (curr >> 22u) & 0b11u;
IP_27 = (curr >> 30u) & 0b11u;
}
inline void set_NVIC_IPR6(uint8_t IP_24, uint8_t IP_25, uint8_t IP_26,
uint8_t IP_27) volatile
{
uint32_t curr = NVIC_IPR6;
curr &= ~(0b11u << 6u);
curr |= (IP_24 & 0b11u) << 6u;
curr &= ~(0b11u << 14u);
curr |= (IP_25 & 0b11u) << 14u;
curr &= ~(0b11u << 22u);
curr |= (IP_26 & 0b11u) << 22u;
curr &= ~(0b11u << 30u);
curr |= (IP_27 & 0b11u) << 30u;
NVIC_IPR6 = curr;
}
inline uint8_t get_NVIC_IPR7_IP_28() volatile
{
return (NVIC_IPR7 >> 6u) & 0b11u;
}
inline void set_NVIC_IPR7_IP_28(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR7;
curr &= ~(0b11u << 6u);
curr |= (value & 0b11u) << 6u;
NVIC_IPR7 = curr;
}
inline uint8_t get_NVIC_IPR7_IP_29() volatile
{
return (NVIC_IPR7 >> 14u) & 0b11u;
}
inline void set_NVIC_IPR7_IP_29(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR7;
curr &= ~(0b11u << 14u);
curr |= (value & 0b11u) << 14u;
NVIC_IPR7 = curr;
}
inline uint8_t get_NVIC_IPR7_IP_30() volatile
{
return (NVIC_IPR7 >> 22u) & 0b11u;
}
inline void set_NVIC_IPR7_IP_30(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR7;
curr &= ~(0b11u << 22u);
curr |= (value & 0b11u) << 22u;
NVIC_IPR7 = curr;
}
inline uint8_t get_NVIC_IPR7_IP_31() volatile
{
return (NVIC_IPR7 >> 30u) & 0b11u;
}
inline void set_NVIC_IPR7_IP_31(uint8_t value) volatile
{
uint32_t curr = NVIC_IPR7;
curr &= ~(0b11u << 30u);
curr |= (value & 0b11u) << 30u;
NVIC_IPR7 = curr;
}
inline void get_NVIC_IPR7(uint8_t &IP_28, uint8_t &IP_29, uint8_t &IP_30,
uint8_t &IP_31) volatile
{
uint32_t curr = NVIC_IPR7;
IP_28 = (curr >> 6u) & 0b11u;
IP_29 = (curr >> 14u) & 0b11u;
IP_30 = (curr >> 22u) & 0b11u;
IP_31 = (curr >> 30u) & 0b11u;
}
inline void set_NVIC_IPR7(uint8_t IP_28, uint8_t IP_29, uint8_t IP_30,
uint8_t IP_31) volatile
{
uint32_t curr = NVIC_IPR7;
curr &= ~(0b11u << 6u);
curr |= (IP_28 & 0b11u) << 6u;
curr &= ~(0b11u << 14u);
curr |= (IP_29 & 0b11u) << 14u;
curr &= ~(0b11u << 22u);
curr |= (IP_30 & 0b11u) << 22u;
curr &= ~(0b11u << 30u);
curr |= (IP_31 & 0b11u) << 30u;
NVIC_IPR7 = curr;
}
inline uint8_t get_CPUID_REVISION() volatile
{
return (CPUID >> 0u) & 0b1111u;
}
inline uint16_t get_CPUID_PARTNO() volatile
{
return (CPUID >> 4u) & 0b111111111111u;
}
inline uint8_t get_CPUID_ARCHITECTURE() volatile
{
return (CPUID >> 16u) & 0b1111u;
}
inline uint8_t get_CPUID_VARIANT() volatile
{
return (CPUID >> 20u) & 0b1111u;
}
inline uint8_t get_CPUID_IMPLEMENTER() volatile
{
return (CPUID >> 24u) & 0b11111111u;
}
inline void get_CPUID(uint8_t &REVISION, uint16_t &PARTNO,
uint8_t &ARCHITECTURE, uint8_t &VARIANT,
uint8_t &IMPLEMENTER) volatile
{
uint32_t curr = CPUID;
REVISION = (curr >> 0u) & 0b1111u;
PARTNO = (curr >> 4u) & 0b111111111111u;
ARCHITECTURE = (curr >> 16u) & 0b1111u;
VARIANT = (curr >> 20u) & 0b1111u;
IMPLEMENTER = (curr >> 24u) & 0b11111111u;
}
inline uint16_t get_ICSR_VECTACTIVE() volatile
{
return (ICSR >> 0u) & 0b111111111u;
}
inline uint16_t get_ICSR_VECTPENDING() volatile
{
return (ICSR >> 12u) & 0b111111111u;
}
inline bool get_ICSR_ISRPENDING() volatile
{
return ICSR & (1u << 22u);
}
inline bool get_ICSR_ISRPREEMPT() volatile
{
return ICSR & (1u << 23u);
}
inline bool get_ICSR_PENDSTCLR() volatile
{
return ICSR & (1u << 25u);
}
inline void set_ICSR_PENDSTCLR() volatile
{
ICSR |= 1u << 25u;
}
inline void clear_ICSR_PENDSTCLR() volatile
{
ICSR &= ~(1u << 25u);
}
inline void toggle_ICSR_PENDSTCLR() volatile
{
ICSR ^= 1u << 25u;
}
inline bool get_ICSR_PENDSTSET() volatile
{
return ICSR & (1u << 26u);
}
inline void set_ICSR_PENDSTSET() volatile
{
ICSR |= 1u << 26u;
}
inline void clear_ICSR_PENDSTSET() volatile
{
ICSR &= ~(1u << 26u);
}
inline void toggle_ICSR_PENDSTSET() volatile
{
ICSR ^= 1u << 26u;
}
inline bool get_ICSR_PENDSVCLR() volatile
{
return ICSR & (1u << 27u);
}
inline void set_ICSR_PENDSVCLR() volatile
{
ICSR |= 1u << 27u;
}
inline void clear_ICSR_PENDSVCLR() volatile
{
ICSR &= ~(1u << 27u);
}
inline void toggle_ICSR_PENDSVCLR() volatile
{
ICSR ^= 1u << 27u;
}
inline bool get_ICSR_PENDSVSET() volatile
{
return ICSR & (1u << 28u);
}
inline void set_ICSR_PENDSVSET() volatile
{
ICSR |= 1u << 28u;
}
inline void clear_ICSR_PENDSVSET() volatile
{
ICSR &= ~(1u << 28u);
}
inline void toggle_ICSR_PENDSVSET() volatile
{
ICSR ^= 1u << 28u;
}
inline bool get_ICSR_NMIPENDSET() volatile
{
return ICSR & (1u << 31u);
}
inline void set_ICSR_NMIPENDSET() volatile
{
ICSR |= 1u << 31u;
}
inline void clear_ICSR_NMIPENDSET() volatile
{
ICSR &= ~(1u << 31u);
}
inline void toggle_ICSR_NMIPENDSET() volatile
{
ICSR ^= 1u << 31u;
}
inline void get_ICSR(uint16_t &VECTACTIVE, uint16_t &VECTPENDING,
bool &ISRPENDING, bool &ISRPREEMPT, bool &PENDSTCLR,
bool &PENDSTSET, bool &PENDSVCLR, bool &PENDSVSET,
bool &NMIPENDSET) volatile
{
uint32_t curr = ICSR;
VECTACTIVE = (curr >> 0u) & 0b111111111u;
VECTPENDING = (curr >> 12u) & 0b111111111u;
ISRPENDING = curr & (1u << 22u);
ISRPREEMPT = curr & (1u << 23u);
PENDSTCLR = curr & (1u << 25u);
PENDSTSET = curr & (1u << 26u);
PENDSVCLR = curr & (1u << 27u);
PENDSVSET = curr & (1u << 28u);
NMIPENDSET = curr & (1u << 31u);
}
inline void set_ICSR(bool PENDSTCLR, bool PENDSTSET, bool PENDSVCLR,
bool PENDSVSET, bool NMIPENDSET) volatile
{
uint32_t curr = ICSR;
curr &= ~(0b1u << 25u);
curr |= (PENDSTCLR & 0b1u) << 25u;
curr &= ~(0b1u << 26u);
curr |= (PENDSTSET & 0b1u) << 26u;
curr &= ~(0b1u << 27u);
curr |= (PENDSVCLR & 0b1u) << 27u;
curr &= ~(0b1u << 28u);
curr |= (PENDSVSET & 0b1u) << 28u;
curr &= ~(0b1u << 31u);
curr |= (NMIPENDSET & 0b1u) << 31u;
ICSR = curr;
}
inline uint32_t get_VTOR_TBLOFF() volatile
{
return (VTOR >> 8u) & 0b111111111111111111111111u;
}
inline void set_VTOR_TBLOFF(uint32_t value) volatile
{
uint32_t curr = VTOR;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (value & 0b111111111111111111111111u) << 8u;
VTOR = curr;
}
inline bool get_AIRCR_VECTCLRACTIVE() volatile
{
return AIRCR & (1u << 1u);
}
inline void set_AIRCR_VECTCLRACTIVE() volatile
{
AIRCR |= 1u << 1u;
}
inline void clear_AIRCR_VECTCLRACTIVE() volatile
{
AIRCR &= ~(1u << 1u);
}
inline void toggle_AIRCR_VECTCLRACTIVE() volatile
{
AIRCR ^= 1u << 1u;
}
inline bool get_AIRCR_SYSRESETREQ() volatile
{
return AIRCR & (1u << 2u);
}
inline void set_AIRCR_SYSRESETREQ() volatile
{
AIRCR |= 1u << 2u;
}
inline void clear_AIRCR_SYSRESETREQ() volatile
{
AIRCR &= ~(1u << 2u);
}
inline void toggle_AIRCR_SYSRESETREQ() volatile
{
AIRCR ^= 1u << 2u;
}
inline bool get_AIRCR_ENDIANESS() volatile
{
return AIRCR & (1u << 15u);
}
inline uint16_t get_AIRCR_VECTKEY() volatile
{
return (AIRCR >> 16u) & 0b1111111111111111u;
}
inline void set_AIRCR_VECTKEY(uint16_t value) volatile
{
uint32_t curr = AIRCR;
curr &= ~(0b1111111111111111u << 16u);
curr |= (value & 0b1111111111111111u) << 16u;
AIRCR = curr;
}
inline void get_AIRCR(bool &VECTCLRACTIVE, bool &SYSRESETREQ,
bool &ENDIANESS, uint16_t &VECTKEY) volatile
{
uint32_t curr = AIRCR;
VECTCLRACTIVE = curr & (1u << 1u);
SYSRESETREQ = curr & (1u << 2u);
ENDIANESS = curr & (1u << 15u);
VECTKEY = (curr >> 16u) & 0b1111111111111111u;
}
inline void set_AIRCR(bool VECTCLRACTIVE, bool SYSRESETREQ,
uint16_t VECTKEY) volatile
{
uint32_t curr = AIRCR;
curr &= ~(0b1u << 1u);
curr |= (VECTCLRACTIVE & 0b1u) << 1u;
curr &= ~(0b1u << 2u);
curr |= (SYSRESETREQ & 0b1u) << 2u;
curr &= ~(0b1111111111111111u << 16u);
curr |= (VECTKEY & 0b1111111111111111u) << 16u;
AIRCR = curr;
}
inline bool get_SCR_SLEEPONEXIT() volatile
{
return SCR & (1u << 1u);
}
inline void set_SCR_SLEEPONEXIT() volatile
{
SCR |= 1u << 1u;
}
inline void clear_SCR_SLEEPONEXIT() volatile
{
SCR &= ~(1u << 1u);
}
inline void toggle_SCR_SLEEPONEXIT() volatile
{
SCR ^= 1u << 1u;
}
inline bool get_SCR_SLEEPDEEP() volatile
{
return SCR & (1u << 2u);
}
inline void set_SCR_SLEEPDEEP() volatile
{
SCR |= 1u << 2u;
}
inline void clear_SCR_SLEEPDEEP() volatile
{
SCR &= ~(1u << 2u);
}
inline void toggle_SCR_SLEEPDEEP() volatile
{
SCR ^= 1u << 2u;
}
inline bool get_SCR_SEVONPEND() volatile
{
return SCR & (1u << 4u);
}
inline void set_SCR_SEVONPEND() volatile
{
SCR |= 1u << 4u;
}
inline void clear_SCR_SEVONPEND() volatile
{
SCR &= ~(1u << 4u);
}
inline void toggle_SCR_SEVONPEND() volatile
{
SCR ^= 1u << 4u;
}
inline void get_SCR(bool &SLEEPONEXIT, bool &SLEEPDEEP,
bool &SEVONPEND) volatile
{
uint32_t curr = SCR;
SLEEPONEXIT = curr & (1u << 1u);
SLEEPDEEP = curr & (1u << 2u);
SEVONPEND = curr & (1u << 4u);
}
inline void set_SCR(bool SLEEPONEXIT, bool SLEEPDEEP,
bool SEVONPEND) volatile
{
uint32_t curr = SCR;
curr &= ~(0b1u << 1u);
curr |= (SLEEPONEXIT & 0b1u) << 1u;
curr &= ~(0b1u << 2u);
curr |= (SLEEPDEEP & 0b1u) << 2u;
curr &= ~(0b1u << 4u);
curr |= (SEVONPEND & 0b1u) << 4u;
SCR = curr;
}
inline bool get_CCR_UNALIGN_TRP() volatile
{
return CCR & (1u << 3u);
}
inline bool get_CCR_STKALIGN() volatile
{
return CCR & (1u << 9u);
}
inline void get_CCR(bool &UNALIGN_TRP, bool &STKALIGN) volatile
{
uint32_t curr = CCR;
UNALIGN_TRP = curr & (1u << 3u);
STKALIGN = curr & (1u << 9u);
}
inline uint8_t get_SHPR2_PRI_11() volatile
{
return (SHPR2 >> 30u) & 0b11u;
}
inline void set_SHPR2_PRI_11(uint8_t value) volatile
{
uint32_t curr = SHPR2;
curr &= ~(0b11u << 30u);
curr |= (value & 0b11u) << 30u;
SHPR2 = curr;
}
inline uint8_t get_SHPR3_PRI_14() volatile
{
return (SHPR3 >> 22u) & 0b11u;
}
inline void set_SHPR3_PRI_14(uint8_t value) volatile
{
uint32_t curr = SHPR3;
curr &= ~(0b11u << 22u);
curr |= (value & 0b11u) << 22u;
SHPR3 = curr;
}
inline uint8_t get_SHPR3_PRI_15() volatile
{
return (SHPR3 >> 30u) & 0b11u;
}
inline void set_SHPR3_PRI_15(uint8_t value) volatile
{
uint32_t curr = SHPR3;
curr &= ~(0b11u << 30u);
curr |= (value & 0b11u) << 30u;
SHPR3 = curr;
}
inline void get_SHPR3(uint8_t &PRI_14, uint8_t &PRI_15) volatile
{
uint32_t curr = SHPR3;
PRI_14 = (curr >> 22u) & 0b11u;
PRI_15 = (curr >> 30u) & 0b11u;
}
inline void set_SHPR3(uint8_t PRI_14, uint8_t PRI_15) volatile
{
uint32_t curr = SHPR3;
curr &= ~(0b11u << 22u);
curr |= (PRI_14 & 0b11u) << 22u;
curr &= ~(0b11u << 30u);
curr |= (PRI_15 & 0b11u) << 30u;
SHPR3 = curr;
}
inline bool get_SHCSR_SVCALLPENDED() volatile
{
return SHCSR & (1u << 15u);
}
inline void set_SHCSR_SVCALLPENDED() volatile
{
SHCSR |= 1u << 15u;
}
inline void clear_SHCSR_SVCALLPENDED() volatile
{
SHCSR &= ~(1u << 15u);
}
inline void toggle_SHCSR_SVCALLPENDED() volatile
{
SHCSR ^= 1u << 15u;
}
inline bool get_MPU_TYPE_SEPARATE() volatile
{
return MPU_TYPE & (1u << 0u);
}
inline uint8_t get_MPU_TYPE_DREGION() volatile
{
return (MPU_TYPE >> 8u) & 0b11111111u;
}
inline uint8_t get_MPU_TYPE_IREGION() volatile
{
return (MPU_TYPE >> 16u) & 0b11111111u;
}
inline void get_MPU_TYPE(bool &SEPARATE, uint8_t &DREGION,
uint8_t &IREGION) volatile
{
uint32_t curr = MPU_TYPE;
SEPARATE = curr & (1u << 0u);
DREGION = (curr >> 8u) & 0b11111111u;
IREGION = (curr >> 16u) & 0b11111111u;
}
inline bool get_MPU_CTRL_ENABLE() volatile
{
return MPU_CTRL & (1u << 0u);
}
inline void set_MPU_CTRL_ENABLE() volatile
{
MPU_CTRL |= 1u << 0u;
}
inline void clear_MPU_CTRL_ENABLE() volatile
{
MPU_CTRL &= ~(1u << 0u);
}
inline void toggle_MPU_CTRL_ENABLE() volatile
{
MPU_CTRL ^= 1u << 0u;
}
inline bool get_MPU_CTRL_HFNMIENA() volatile
{
return MPU_CTRL & (1u << 1u);
}
inline void set_MPU_CTRL_HFNMIENA() volatile
{
MPU_CTRL |= 1u << 1u;
}
inline void clear_MPU_CTRL_HFNMIENA() volatile
{
MPU_CTRL &= ~(1u << 1u);
}
inline void toggle_MPU_CTRL_HFNMIENA() volatile
{
MPU_CTRL ^= 1u << 1u;
}
inline bool get_MPU_CTRL_PRIVDEFENA() volatile
{
return MPU_CTRL & (1u << 2u);
}
inline void set_MPU_CTRL_PRIVDEFENA() volatile
{
MPU_CTRL |= 1u << 2u;
}
inline void clear_MPU_CTRL_PRIVDEFENA() volatile
{
MPU_CTRL &= ~(1u << 2u);
}
inline void toggle_MPU_CTRL_PRIVDEFENA() volatile
{
MPU_CTRL ^= 1u << 2u;
}
inline void get_MPU_CTRL(bool &ENABLE, bool &HFNMIENA,
bool &PRIVDEFENA) volatile
{
uint32_t curr = MPU_CTRL;
ENABLE = curr & (1u << 0u);
HFNMIENA = curr & (1u << 1u);
PRIVDEFENA = curr & (1u << 2u);
}
inline void set_MPU_CTRL(bool ENABLE, bool HFNMIENA,
bool PRIVDEFENA) volatile
{
uint32_t curr = MPU_CTRL;
curr &= ~(0b1u << 0u);
curr |= (ENABLE & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (HFNMIENA & 0b1u) << 1u;
curr &= ~(0b1u << 2u);
curr |= (PRIVDEFENA & 0b1u) << 2u;
MPU_CTRL = curr;
}
inline uint8_t get_MPU_RNR_REGION() volatile
{
return (MPU_RNR >> 0u) & 0b1111u;
}
inline void set_MPU_RNR_REGION(uint8_t value) volatile
{
uint32_t curr = MPU_RNR;
curr &= ~(0b1111u << 0u);
curr |= (value & 0b1111u) << 0u;
MPU_RNR = curr;
}
inline uint8_t get_MPU_RBAR_REGION() volatile
{
return (MPU_RBAR >> 0u) & 0b1111u;
}
inline void set_MPU_RBAR_REGION(uint8_t value) volatile
{
uint32_t curr = MPU_RBAR;
curr &= ~(0b1111u << 0u);
curr |= (value & 0b1111u) << 0u;
MPU_RBAR = curr;
}
inline bool get_MPU_RBAR_VALID() volatile
{
return MPU_RBAR & (1u << 4u);
}
inline void set_MPU_RBAR_VALID() volatile
{
MPU_RBAR |= 1u << 4u;
}
inline void clear_MPU_RBAR_VALID() volatile
{
MPU_RBAR &= ~(1u << 4u);
}
inline void toggle_MPU_RBAR_VALID() volatile
{
MPU_RBAR ^= 1u << 4u;
}
inline uint32_t get_MPU_RBAR_ADDR() volatile
{
return (MPU_RBAR >> 8u) & 0b111111111111111111111111u;
}
inline void set_MPU_RBAR_ADDR(uint32_t value) volatile
{
uint32_t curr = MPU_RBAR;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (value & 0b111111111111111111111111u) << 8u;
MPU_RBAR = curr;
}
inline void get_MPU_RBAR(uint8_t ®ION, bool &VALID,
uint32_t &ADDR) volatile
{
uint32_t curr = MPU_RBAR;
REGION = (curr >> 0u) & 0b1111u;
VALID = curr & (1u << 4u);
ADDR = (curr >> 8u) & 0b111111111111111111111111u;
}
inline void set_MPU_RBAR(uint8_t REGION, bool VALID,
uint32_t ADDR) volatile
{
uint32_t curr = MPU_RBAR;
curr &= ~(0b1111u << 0u);
curr |= (REGION & 0b1111u) << 0u;
curr &= ~(0b1u << 4u);
curr |= (VALID & 0b1u) << 4u;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (ADDR & 0b111111111111111111111111u) << 8u;
MPU_RBAR = curr;
}
inline bool get_MPU_RASR_ENABLE() volatile
{
return MPU_RASR & (1u << 0u);
}
inline void set_MPU_RASR_ENABLE() volatile
{
MPU_RASR |= 1u << 0u;
}
inline void clear_MPU_RASR_ENABLE() volatile
{
MPU_RASR &= ~(1u << 0u);
}
inline void toggle_MPU_RASR_ENABLE() volatile
{
MPU_RASR ^= 1u << 0u;
}
inline uint8_t get_MPU_RASR_SIZE() volatile
{
return (MPU_RASR >> 1u) & 0b11111u;
}
inline void set_MPU_RASR_SIZE(uint8_t value) volatile
{
uint32_t curr = MPU_RASR;
curr &= ~(0b11111u << 1u);
curr |= (value & 0b11111u) << 1u;
MPU_RASR = curr;
}
inline uint8_t get_MPU_RASR_SRD() volatile
{
return (MPU_RASR >> 8u) & 0b11111111u;
}
inline void set_MPU_RASR_SRD(uint8_t value) volatile
{
uint32_t curr = MPU_RASR;
curr &= ~(0b11111111u << 8u);
curr |= (value & 0b11111111u) << 8u;
MPU_RASR = curr;
}
inline uint16_t get_MPU_RASR_ATTRS() volatile
{
return (MPU_RASR >> 16u) & 0b1111111111111111u;
}
inline void set_MPU_RASR_ATTRS(uint16_t value) volatile
{
uint32_t curr = MPU_RASR;
curr &= ~(0b1111111111111111u << 16u);
curr |= (value & 0b1111111111111111u) << 16u;
MPU_RASR = curr;
}
inline void get_MPU_RASR(bool &ENABLE, uint8_t &SIZE, uint8_t &SRD,
uint16_t &ATTRS) volatile
{
uint32_t curr = MPU_RASR;
ENABLE = curr & (1u << 0u);
SIZE = (curr >> 1u) & 0b11111u;
SRD = (curr >> 8u) & 0b11111111u;
ATTRS = (curr >> 16u) & 0b1111111111111111u;
}
inline void set_MPU_RASR(bool ENABLE, uint8_t SIZE, uint8_t SRD,
uint16_t ATTRS) volatile
{
uint32_t curr = MPU_RASR;
curr &= ~(0b1u << 0u);
curr |= (ENABLE & 0b1u) << 0u;
curr &= ~(0b11111u << 1u);
curr |= (SIZE & 0b11111u) << 1u;
curr &= ~(0b11111111u << 8u);
curr |= (SRD & 0b11111111u) << 8u;
curr &= ~(0b1111111111111111u << 16u);
curr |= (ATTRS & 0b1111111111111111u) << 16u;
MPU_RASR = curr;
}
};
static_assert(sizeof(ppb) == ppb::size);
static volatile ppb *const PPB = reinterpret_cast<ppb *>(0xe0000000);
}; // namespace RP2040