Program Listing for File io_qspi.h

↰ Return to documentation for file (src/generated/structs/io_qspi.h)

#pragma once

#include "../enums/IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER.h"
#include "../enums/IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER.h"
#include "../ifgen/common.h"

namespace RP2040
{

struct [[gnu::packed]] io_qspi
{
    /* Constant attributes. */
    static constexpr std::size_t size = 88;
    /* Fields. */
    const uint32_t GPIO_QSPI_SCLK_STATUS = {};
    uint32_t GPIO_QSPI_SCLK_CTRL;
    const uint32_t GPIO_QSPI_SS_STATUS = {};
    uint32_t GPIO_QSPI_SS_CTRL;
    const uint32_t GPIO_QSPI_SD0_STATUS = {};
    uint32_t GPIO_QSPI_SD0_CTRL;
    const uint32_t GPIO_QSPI_SD1_STATUS = {};
    uint32_t GPIO_QSPI_SD1_CTRL;
    const uint32_t GPIO_QSPI_SD2_STATUS = {};
    uint32_t GPIO_QSPI_SD2_CTRL;
    const uint32_t GPIO_QSPI_SD3_STATUS = {};
    uint32_t GPIO_QSPI_SD3_CTRL;
    uint32_t INTR;
    uint32_t PROC0_INTE;
    uint32_t PROC0_INTF;
    const uint32_t PROC0_INTS = {};
    uint32_t PROC1_INTE;
    uint32_t PROC1_INTF;
    const uint32_t PROC1_INTS = {};
    uint32_t DORMANT_WAKE_INTE;
    uint32_t DORMANT_WAKE_INTF;
    const uint32_t DORMANT_WAKE_INTS =
        {};
    /* Methods. */

    inline bool get_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI() volatile
    {
        return GPIO_QSPI_SCLK_STATUS & (1u << 8u);
    }

    inline bool get_GPIO_QSPI_SCLK_STATUS_OUTTOPAD() volatile
    {
        return GPIO_QSPI_SCLK_STATUS & (1u << 9u);
    }

    inline bool get_GPIO_QSPI_SCLK_STATUS_OEFROMPERI() volatile
    {
        return GPIO_QSPI_SCLK_STATUS & (1u << 12u);
    }

    inline bool get_GPIO_QSPI_SCLK_STATUS_OETOPAD() volatile
    {
        return GPIO_QSPI_SCLK_STATUS & (1u << 13u);
    }

    inline bool get_GPIO_QSPI_SCLK_STATUS_INFROMPAD() volatile
    {
        return GPIO_QSPI_SCLK_STATUS & (1u << 17u);
    }

    inline bool get_GPIO_QSPI_SCLK_STATUS_INTOPERI() volatile
    {
        return GPIO_QSPI_SCLK_STATUS & (1u << 19u);
    }

    inline bool get_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD() volatile
    {
        return GPIO_QSPI_SCLK_STATUS & (1u << 24u);
    }

    inline bool get_GPIO_QSPI_SCLK_STATUS_IRQTOPROC() volatile
    {
        return GPIO_QSPI_SCLK_STATUS & (1u << 26u);
    }

    inline void get_GPIO_QSPI_SCLK_STATUS(bool &OUTFROMPERI, bool &OUTTOPAD,
                                          bool &OEFROMPERI, bool &OETOPAD,
                                          bool &INFROMPAD, bool &INTOPERI,
                                          bool &IRQFROMPAD,
                                          bool &IRQTOPROC) volatile
    {
        uint32_t curr = GPIO_QSPI_SCLK_STATUS;

        OUTFROMPERI = curr & (1u << 8u);
        OUTTOPAD = curr & (1u << 9u);
        OEFROMPERI = curr & (1u << 12u);
        OETOPAD = curr & (1u << 13u);
        INFROMPAD = curr & (1u << 17u);
        INTOPERI = curr & (1u << 19u);
        IRQFROMPAD = curr & (1u << 24u);
        IRQTOPROC = curr & (1u << 26u);
    }

    inline IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL
    get_GPIO_QSPI_SCLK_CTRL_FUNCSEL() volatile
    {
        return IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL(
            (GPIO_QSPI_SCLK_CTRL >> 0u) & 0b11111u);
    }

    inline void set_GPIO_QSPI_SCLK_CTRL_FUNCSEL(
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL value) volatile
    {
        uint32_t curr = GPIO_QSPI_SCLK_CTRL;

        curr &= ~(0b11111u << 0u);
        curr |= (std::to_underlying(value) & 0b11111u) << 0u;

        GPIO_QSPI_SCLK_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER
    get_GPIO_QSPI_SCLK_CTRL_OUTOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER(
            (GPIO_QSPI_SCLK_CTRL >> 8u) & 0b11u);
    }

    inline void set_GPIO_QSPI_SCLK_CTRL_OUTOVER(
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SCLK_CTRL;

        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(value) & 0b11u) << 8u;

        GPIO_QSPI_SCLK_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER
    get_GPIO_QSPI_SCLK_CTRL_OEOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER(
            (GPIO_QSPI_SCLK_CTRL >> 12u) & 0b11u);
    }

    inline void set_GPIO_QSPI_SCLK_CTRL_OEOVER(
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SCLK_CTRL;

        curr &= ~(0b11u << 12u);
        curr |= (std::to_underlying(value) & 0b11u) << 12u;

        GPIO_QSPI_SCLK_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER
    get_GPIO_QSPI_SCLK_CTRL_INOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER(
            (GPIO_QSPI_SCLK_CTRL >> 16u) & 0b11u);
    }

    inline void set_GPIO_QSPI_SCLK_CTRL_INOVER(
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SCLK_CTRL;

        curr &= ~(0b11u << 16u);
        curr |= (std::to_underlying(value) & 0b11u) << 16u;

        GPIO_QSPI_SCLK_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER
    get_GPIO_QSPI_SCLK_CTRL_IRQOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER(
            (GPIO_QSPI_SCLK_CTRL >> 28u) & 0b11u);
    }

    inline void set_GPIO_QSPI_SCLK_CTRL_IRQOVER(
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SCLK_CTRL;

        curr &= ~(0b11u << 28u);
        curr |= (std::to_underlying(value) & 0b11u) << 28u;

        GPIO_QSPI_SCLK_CTRL = curr;
    }

    inline void get_GPIO_QSPI_SCLK_CTRL(
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL &FUNCSEL,
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER &OUTOVER,
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER &OEOVER,
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER &INOVER,
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER &IRQOVER) volatile
    {
        uint32_t curr = GPIO_QSPI_SCLK_CTRL;

        FUNCSEL = IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL((curr >> 0u) & 0b11111u);
        OUTOVER = IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER((curr >> 8u) & 0b11u);
        OEOVER = IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER((curr >> 12u) & 0b11u);
        INOVER = IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER((curr >> 16u) & 0b11u);
        IRQOVER = IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER((curr >> 28u) & 0b11u);
    }

    inline void set_GPIO_QSPI_SCLK_CTRL(
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL FUNCSEL,
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER OUTOVER,
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER OEOVER,
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER INOVER,
        IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER IRQOVER) volatile
    {
        uint32_t curr = GPIO_QSPI_SCLK_CTRL;

        curr &= ~(0b11111u << 0u);
        curr |= (std::to_underlying(FUNCSEL) & 0b11111u) << 0u;
        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(OUTOVER) & 0b11u) << 8u;
        curr &= ~(0b11u << 12u);
        curr |= (std::to_underlying(OEOVER) & 0b11u) << 12u;
        curr &= ~(0b11u << 16u);
        curr |= (std::to_underlying(INOVER) & 0b11u) << 16u;
        curr &= ~(0b11u << 28u);
        curr |= (std::to_underlying(IRQOVER) & 0b11u) << 28u;

        GPIO_QSPI_SCLK_CTRL = curr;
    }

    inline bool get_GPIO_QSPI_SS_STATUS_OUTFROMPERI() volatile
    {
        return GPIO_QSPI_SS_STATUS & (1u << 8u);
    }

    inline bool get_GPIO_QSPI_SS_STATUS_OUTTOPAD() volatile
    {
        return GPIO_QSPI_SS_STATUS & (1u << 9u);
    }

    inline bool get_GPIO_QSPI_SS_STATUS_OEFROMPERI() volatile
    {
        return GPIO_QSPI_SS_STATUS & (1u << 12u);
    }

    inline bool get_GPIO_QSPI_SS_STATUS_OETOPAD() volatile
    {
        return GPIO_QSPI_SS_STATUS & (1u << 13u);
    }

    inline bool get_GPIO_QSPI_SS_STATUS_INFROMPAD() volatile
    {
        return GPIO_QSPI_SS_STATUS & (1u << 17u);
    }

    inline bool get_GPIO_QSPI_SS_STATUS_INTOPERI() volatile
    {
        return GPIO_QSPI_SS_STATUS & (1u << 19u);
    }

    inline bool get_GPIO_QSPI_SS_STATUS_IRQFROMPAD() volatile
    {
        return GPIO_QSPI_SS_STATUS & (1u << 24u);
    }

    inline bool get_GPIO_QSPI_SS_STATUS_IRQTOPROC() volatile
    {
        return GPIO_QSPI_SS_STATUS & (1u << 26u);
    }

    inline void get_GPIO_QSPI_SS_STATUS(bool &OUTFROMPERI, bool &OUTTOPAD,
                                        bool &OEFROMPERI, bool &OETOPAD,
                                        bool &INFROMPAD, bool &INTOPERI,
                                        bool &IRQFROMPAD,
                                        bool &IRQTOPROC) volatile
    {
        uint32_t curr = GPIO_QSPI_SS_STATUS;

        OUTFROMPERI = curr & (1u << 8u);
        OUTTOPAD = curr & (1u << 9u);
        OEFROMPERI = curr & (1u << 12u);
        OETOPAD = curr & (1u << 13u);
        INFROMPAD = curr & (1u << 17u);
        INTOPERI = curr & (1u << 19u);
        IRQFROMPAD = curr & (1u << 24u);
        IRQTOPROC = curr & (1u << 26u);
    }

    inline IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL
    get_GPIO_QSPI_SS_CTRL_FUNCSEL() volatile
    {
        return IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL((GPIO_QSPI_SS_CTRL >> 0u) &
                                                 0b11111u);
    }

    inline void set_GPIO_QSPI_SS_CTRL_FUNCSEL(
        IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL value) volatile
    {
        uint32_t curr = GPIO_QSPI_SS_CTRL;

        curr &= ~(0b11111u << 0u);
        curr |= (std::to_underlying(value) & 0b11111u) << 0u;

        GPIO_QSPI_SS_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER
    get_GPIO_QSPI_SS_CTRL_OUTOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER((GPIO_QSPI_SS_CTRL >> 8u) &
                                                 0b11u);
    }

    inline void set_GPIO_QSPI_SS_CTRL_OUTOVER(
        IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SS_CTRL;

        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(value) & 0b11u) << 8u;

        GPIO_QSPI_SS_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER
    get_GPIO_QSPI_SS_CTRL_OEOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER((GPIO_QSPI_SS_CTRL >> 12u) &
                                                0b11u);
    }

    inline void set_GPIO_QSPI_SS_CTRL_OEOVER(
        IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SS_CTRL;

        curr &= ~(0b11u << 12u);
        curr |= (std::to_underlying(value) & 0b11u) << 12u;

        GPIO_QSPI_SS_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER
    get_GPIO_QSPI_SS_CTRL_INOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER((GPIO_QSPI_SS_CTRL >> 16u) &
                                                0b11u);
    }

    inline void set_GPIO_QSPI_SS_CTRL_INOVER(
        IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SS_CTRL;

        curr &= ~(0b11u << 16u);
        curr |= (std::to_underlying(value) & 0b11u) << 16u;

        GPIO_QSPI_SS_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER
    get_GPIO_QSPI_SS_CTRL_IRQOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER((GPIO_QSPI_SS_CTRL >> 28u) &
                                                 0b11u);
    }

    inline void set_GPIO_QSPI_SS_CTRL_IRQOVER(
        IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SS_CTRL;

        curr &= ~(0b11u << 28u);
        curr |= (std::to_underlying(value) & 0b11u) << 28u;

        GPIO_QSPI_SS_CTRL = curr;
    }

    inline void get_GPIO_QSPI_SS_CTRL(
        IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL &FUNCSEL,
        IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER &OUTOVER,
        IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER &OEOVER,
        IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER &INOVER,
        IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER &IRQOVER) volatile
    {
        uint32_t curr = GPIO_QSPI_SS_CTRL;

        FUNCSEL = IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL((curr >> 0u) & 0b11111u);
        OUTOVER = IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER((curr >> 8u) & 0b11u);
        OEOVER = IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER((curr >> 12u) & 0b11u);
        INOVER = IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER((curr >> 16u) & 0b11u);
        IRQOVER = IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER((curr >> 28u) & 0b11u);
    }

    inline void set_GPIO_QSPI_SS_CTRL(
        IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL FUNCSEL,
        IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER OUTOVER,
        IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER OEOVER,
        IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER INOVER,
        IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER IRQOVER) volatile
    {
        uint32_t curr = GPIO_QSPI_SS_CTRL;

        curr &= ~(0b11111u << 0u);
        curr |= (std::to_underlying(FUNCSEL) & 0b11111u) << 0u;
        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(OUTOVER) & 0b11u) << 8u;
        curr &= ~(0b11u << 12u);
        curr |= (std::to_underlying(OEOVER) & 0b11u) << 12u;
        curr &= ~(0b11u << 16u);
        curr |= (std::to_underlying(INOVER) & 0b11u) << 16u;
        curr &= ~(0b11u << 28u);
        curr |= (std::to_underlying(IRQOVER) & 0b11u) << 28u;

        GPIO_QSPI_SS_CTRL = curr;
    }

    inline bool get_GPIO_QSPI_SD0_STATUS_OUTFROMPERI() volatile
    {
        return GPIO_QSPI_SD0_STATUS & (1u << 8u);
    }

    inline bool get_GPIO_QSPI_SD0_STATUS_OUTTOPAD() volatile
    {
        return GPIO_QSPI_SD0_STATUS & (1u << 9u);
    }

    inline bool get_GPIO_QSPI_SD0_STATUS_OEFROMPERI() volatile
    {
        return GPIO_QSPI_SD0_STATUS & (1u << 12u);
    }

    inline bool get_GPIO_QSPI_SD0_STATUS_OETOPAD() volatile
    {
        return GPIO_QSPI_SD0_STATUS & (1u << 13u);
    }

    inline bool get_GPIO_QSPI_SD0_STATUS_INFROMPAD() volatile
    {
        return GPIO_QSPI_SD0_STATUS & (1u << 17u);
    }

    inline bool get_GPIO_QSPI_SD0_STATUS_INTOPERI() volatile
    {
        return GPIO_QSPI_SD0_STATUS & (1u << 19u);
    }

    inline bool get_GPIO_QSPI_SD0_STATUS_IRQFROMPAD() volatile
    {
        return GPIO_QSPI_SD0_STATUS & (1u << 24u);
    }

    inline bool get_GPIO_QSPI_SD0_STATUS_IRQTOPROC() volatile
    {
        return GPIO_QSPI_SD0_STATUS & (1u << 26u);
    }

    inline void get_GPIO_QSPI_SD0_STATUS(bool &OUTFROMPERI, bool &OUTTOPAD,
                                         bool &OEFROMPERI, bool &OETOPAD,
                                         bool &INFROMPAD, bool &INTOPERI,
                                         bool &IRQFROMPAD,
                                         bool &IRQTOPROC) volatile
    {
        uint32_t curr = GPIO_QSPI_SD0_STATUS;

        OUTFROMPERI = curr & (1u << 8u);
        OUTTOPAD = curr & (1u << 9u);
        OEFROMPERI = curr & (1u << 12u);
        OETOPAD = curr & (1u << 13u);
        INFROMPAD = curr & (1u << 17u);
        INTOPERI = curr & (1u << 19u);
        IRQFROMPAD = curr & (1u << 24u);
        IRQTOPROC = curr & (1u << 26u);
    }

    inline IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL
    get_GPIO_QSPI_SD0_CTRL_FUNCSEL() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL((GPIO_QSPI_SD0_CTRL >> 0u) &
                                                  0b11111u);
    }

    inline void set_GPIO_QSPI_SD0_CTRL_FUNCSEL(
        IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD0_CTRL;

        curr &= ~(0b11111u << 0u);
        curr |= (std::to_underlying(value) & 0b11111u) << 0u;

        GPIO_QSPI_SD0_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER
    get_GPIO_QSPI_SD0_CTRL_OUTOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER((GPIO_QSPI_SD0_CTRL >> 8u) &
                                                  0b11u);
    }

    inline void set_GPIO_QSPI_SD0_CTRL_OUTOVER(
        IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD0_CTRL;

        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(value) & 0b11u) << 8u;

        GPIO_QSPI_SD0_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER
    get_GPIO_QSPI_SD0_CTRL_OEOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER((GPIO_QSPI_SD0_CTRL >> 12u) &
                                                 0b11u);
    }

    inline void set_GPIO_QSPI_SD0_CTRL_OEOVER(
        IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD0_CTRL;

        curr &= ~(0b11u << 12u);
        curr |= (std::to_underlying(value) & 0b11u) << 12u;

        GPIO_QSPI_SD0_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER
    get_GPIO_QSPI_SD0_CTRL_INOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER((GPIO_QSPI_SD0_CTRL >> 16u) &
                                                 0b11u);
    }

    inline void set_GPIO_QSPI_SD0_CTRL_INOVER(
        IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD0_CTRL;

        curr &= ~(0b11u << 16u);
        curr |= (std::to_underlying(value) & 0b11u) << 16u;

        GPIO_QSPI_SD0_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER
    get_GPIO_QSPI_SD0_CTRL_IRQOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER((GPIO_QSPI_SD0_CTRL >> 28u) &
                                                  0b11u);
    }

    inline void set_GPIO_QSPI_SD0_CTRL_IRQOVER(
        IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD0_CTRL;

        curr &= ~(0b11u << 28u);
        curr |= (std::to_underlying(value) & 0b11u) << 28u;

        GPIO_QSPI_SD0_CTRL = curr;
    }

    inline void get_GPIO_QSPI_SD0_CTRL(
        IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL &FUNCSEL,
        IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER &OUTOVER,
        IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER &OEOVER,
        IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER &INOVER,
        IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER &IRQOVER) volatile
    {
        uint32_t curr = GPIO_QSPI_SD0_CTRL;

        FUNCSEL = IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL((curr >> 0u) & 0b11111u);
        OUTOVER = IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER((curr >> 8u) & 0b11u);
        OEOVER = IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER((curr >> 12u) & 0b11u);
        INOVER = IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER((curr >> 16u) & 0b11u);
        IRQOVER = IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER((curr >> 28u) & 0b11u);
    }

    inline void set_GPIO_QSPI_SD0_CTRL(
        IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL FUNCSEL,
        IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER OUTOVER,
        IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER OEOVER,
        IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER INOVER,
        IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER IRQOVER) volatile
    {
        uint32_t curr = GPIO_QSPI_SD0_CTRL;

        curr &= ~(0b11111u << 0u);
        curr |= (std::to_underlying(FUNCSEL) & 0b11111u) << 0u;
        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(OUTOVER) & 0b11u) << 8u;
        curr &= ~(0b11u << 12u);
        curr |= (std::to_underlying(OEOVER) & 0b11u) << 12u;
        curr &= ~(0b11u << 16u);
        curr |= (std::to_underlying(INOVER) & 0b11u) << 16u;
        curr &= ~(0b11u << 28u);
        curr |= (std::to_underlying(IRQOVER) & 0b11u) << 28u;

        GPIO_QSPI_SD0_CTRL = curr;
    }

    inline bool get_GPIO_QSPI_SD1_STATUS_OUTFROMPERI() volatile
    {
        return GPIO_QSPI_SD1_STATUS & (1u << 8u);
    }

    inline bool get_GPIO_QSPI_SD1_STATUS_OUTTOPAD() volatile
    {
        return GPIO_QSPI_SD1_STATUS & (1u << 9u);
    }

    inline bool get_GPIO_QSPI_SD1_STATUS_OEFROMPERI() volatile
    {
        return GPIO_QSPI_SD1_STATUS & (1u << 12u);
    }

    inline bool get_GPIO_QSPI_SD1_STATUS_OETOPAD() volatile
    {
        return GPIO_QSPI_SD1_STATUS & (1u << 13u);
    }

    inline bool get_GPIO_QSPI_SD1_STATUS_INFROMPAD() volatile
    {
        return GPIO_QSPI_SD1_STATUS & (1u << 17u);
    }

    inline bool get_GPIO_QSPI_SD1_STATUS_INTOPERI() volatile
    {
        return GPIO_QSPI_SD1_STATUS & (1u << 19u);
    }

    inline bool get_GPIO_QSPI_SD1_STATUS_IRQFROMPAD() volatile
    {
        return GPIO_QSPI_SD1_STATUS & (1u << 24u);
    }

    inline bool get_GPIO_QSPI_SD1_STATUS_IRQTOPROC() volatile
    {
        return GPIO_QSPI_SD1_STATUS & (1u << 26u);
    }

    inline void get_GPIO_QSPI_SD1_STATUS(bool &OUTFROMPERI, bool &OUTTOPAD,
                                         bool &OEFROMPERI, bool &OETOPAD,
                                         bool &INFROMPAD, bool &INTOPERI,
                                         bool &IRQFROMPAD,
                                         bool &IRQTOPROC) volatile
    {
        uint32_t curr = GPIO_QSPI_SD1_STATUS;

        OUTFROMPERI = curr & (1u << 8u);
        OUTTOPAD = curr & (1u << 9u);
        OEFROMPERI = curr & (1u << 12u);
        OETOPAD = curr & (1u << 13u);
        INFROMPAD = curr & (1u << 17u);
        INTOPERI = curr & (1u << 19u);
        IRQFROMPAD = curr & (1u << 24u);
        IRQTOPROC = curr & (1u << 26u);
    }

    inline IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL
    get_GPIO_QSPI_SD1_CTRL_FUNCSEL() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL((GPIO_QSPI_SD1_CTRL >> 0u) &
                                                  0b11111u);
    }

    inline void set_GPIO_QSPI_SD1_CTRL_FUNCSEL(
        IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD1_CTRL;

        curr &= ~(0b11111u << 0u);
        curr |= (std::to_underlying(value) & 0b11111u) << 0u;

        GPIO_QSPI_SD1_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER
    get_GPIO_QSPI_SD1_CTRL_OUTOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER((GPIO_QSPI_SD1_CTRL >> 8u) &
                                                  0b11u);
    }

    inline void set_GPIO_QSPI_SD1_CTRL_OUTOVER(
        IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD1_CTRL;

        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(value) & 0b11u) << 8u;

        GPIO_QSPI_SD1_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER
    get_GPIO_QSPI_SD1_CTRL_OEOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER((GPIO_QSPI_SD1_CTRL >> 12u) &
                                                 0b11u);
    }

    inline void set_GPIO_QSPI_SD1_CTRL_OEOVER(
        IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD1_CTRL;

        curr &= ~(0b11u << 12u);
        curr |= (std::to_underlying(value) & 0b11u) << 12u;

        GPIO_QSPI_SD1_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER
    get_GPIO_QSPI_SD1_CTRL_INOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER((GPIO_QSPI_SD1_CTRL >> 16u) &
                                                 0b11u);
    }

    inline void set_GPIO_QSPI_SD1_CTRL_INOVER(
        IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD1_CTRL;

        curr &= ~(0b11u << 16u);
        curr |= (std::to_underlying(value) & 0b11u) << 16u;

        GPIO_QSPI_SD1_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER
    get_GPIO_QSPI_SD1_CTRL_IRQOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER((GPIO_QSPI_SD1_CTRL >> 28u) &
                                                  0b11u);
    }

    inline void set_GPIO_QSPI_SD1_CTRL_IRQOVER(
        IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD1_CTRL;

        curr &= ~(0b11u << 28u);
        curr |= (std::to_underlying(value) & 0b11u) << 28u;

        GPIO_QSPI_SD1_CTRL = curr;
    }

    inline void get_GPIO_QSPI_SD1_CTRL(
        IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL &FUNCSEL,
        IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER &OUTOVER,
        IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER &OEOVER,
        IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER &INOVER,
        IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER &IRQOVER) volatile
    {
        uint32_t curr = GPIO_QSPI_SD1_CTRL;

        FUNCSEL = IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL((curr >> 0u) & 0b11111u);
        OUTOVER = IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER((curr >> 8u) & 0b11u);
        OEOVER = IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER((curr >> 12u) & 0b11u);
        INOVER = IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER((curr >> 16u) & 0b11u);
        IRQOVER = IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER((curr >> 28u) & 0b11u);
    }

    inline void set_GPIO_QSPI_SD1_CTRL(
        IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL FUNCSEL,
        IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER OUTOVER,
        IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER OEOVER,
        IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER INOVER,
        IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER IRQOVER) volatile
    {
        uint32_t curr = GPIO_QSPI_SD1_CTRL;

        curr &= ~(0b11111u << 0u);
        curr |= (std::to_underlying(FUNCSEL) & 0b11111u) << 0u;
        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(OUTOVER) & 0b11u) << 8u;
        curr &= ~(0b11u << 12u);
        curr |= (std::to_underlying(OEOVER) & 0b11u) << 12u;
        curr &= ~(0b11u << 16u);
        curr |= (std::to_underlying(INOVER) & 0b11u) << 16u;
        curr &= ~(0b11u << 28u);
        curr |= (std::to_underlying(IRQOVER) & 0b11u) << 28u;

        GPIO_QSPI_SD1_CTRL = curr;
    }

    inline bool get_GPIO_QSPI_SD2_STATUS_OUTFROMPERI() volatile
    {
        return GPIO_QSPI_SD2_STATUS & (1u << 8u);
    }

    inline bool get_GPIO_QSPI_SD2_STATUS_OUTTOPAD() volatile
    {
        return GPIO_QSPI_SD2_STATUS & (1u << 9u);
    }

    inline bool get_GPIO_QSPI_SD2_STATUS_OEFROMPERI() volatile
    {
        return GPIO_QSPI_SD2_STATUS & (1u << 12u);
    }

    inline bool get_GPIO_QSPI_SD2_STATUS_OETOPAD() volatile
    {
        return GPIO_QSPI_SD2_STATUS & (1u << 13u);
    }

    inline bool get_GPIO_QSPI_SD2_STATUS_INFROMPAD() volatile
    {
        return GPIO_QSPI_SD2_STATUS & (1u << 17u);
    }

    inline bool get_GPIO_QSPI_SD2_STATUS_INTOPERI() volatile
    {
        return GPIO_QSPI_SD2_STATUS & (1u << 19u);
    }

    inline bool get_GPIO_QSPI_SD2_STATUS_IRQFROMPAD() volatile
    {
        return GPIO_QSPI_SD2_STATUS & (1u << 24u);
    }

    inline bool get_GPIO_QSPI_SD2_STATUS_IRQTOPROC() volatile
    {
        return GPIO_QSPI_SD2_STATUS & (1u << 26u);
    }

    inline void get_GPIO_QSPI_SD2_STATUS(bool &OUTFROMPERI, bool &OUTTOPAD,
                                         bool &OEFROMPERI, bool &OETOPAD,
                                         bool &INFROMPAD, bool &INTOPERI,
                                         bool &IRQFROMPAD,
                                         bool &IRQTOPROC) volatile
    {
        uint32_t curr = GPIO_QSPI_SD2_STATUS;

        OUTFROMPERI = curr & (1u << 8u);
        OUTTOPAD = curr & (1u << 9u);
        OEFROMPERI = curr & (1u << 12u);
        OETOPAD = curr & (1u << 13u);
        INFROMPAD = curr & (1u << 17u);
        INTOPERI = curr & (1u << 19u);
        IRQFROMPAD = curr & (1u << 24u);
        IRQTOPROC = curr & (1u << 26u);
    }

    inline IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL
    get_GPIO_QSPI_SD2_CTRL_FUNCSEL() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL((GPIO_QSPI_SD2_CTRL >> 0u) &
                                                  0b11111u);
    }

    inline void set_GPIO_QSPI_SD2_CTRL_FUNCSEL(
        IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD2_CTRL;

        curr &= ~(0b11111u << 0u);
        curr |= (std::to_underlying(value) & 0b11111u) << 0u;

        GPIO_QSPI_SD2_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER
    get_GPIO_QSPI_SD2_CTRL_OUTOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER((GPIO_QSPI_SD2_CTRL >> 8u) &
                                                  0b11u);
    }

    inline void set_GPIO_QSPI_SD2_CTRL_OUTOVER(
        IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD2_CTRL;

        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(value) & 0b11u) << 8u;

        GPIO_QSPI_SD2_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER
    get_GPIO_QSPI_SD2_CTRL_OEOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER((GPIO_QSPI_SD2_CTRL >> 12u) &
                                                 0b11u);
    }

    inline void set_GPIO_QSPI_SD2_CTRL_OEOVER(
        IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD2_CTRL;

        curr &= ~(0b11u << 12u);
        curr |= (std::to_underlying(value) & 0b11u) << 12u;

        GPIO_QSPI_SD2_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER
    get_GPIO_QSPI_SD2_CTRL_INOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER((GPIO_QSPI_SD2_CTRL >> 16u) &
                                                 0b11u);
    }

    inline void set_GPIO_QSPI_SD2_CTRL_INOVER(
        IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD2_CTRL;

        curr &= ~(0b11u << 16u);
        curr |= (std::to_underlying(value) & 0b11u) << 16u;

        GPIO_QSPI_SD2_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER
    get_GPIO_QSPI_SD2_CTRL_IRQOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER((GPIO_QSPI_SD2_CTRL >> 28u) &
                                                  0b11u);
    }

    inline void set_GPIO_QSPI_SD2_CTRL_IRQOVER(
        IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD2_CTRL;

        curr &= ~(0b11u << 28u);
        curr |= (std::to_underlying(value) & 0b11u) << 28u;

        GPIO_QSPI_SD2_CTRL = curr;
    }

    inline void get_GPIO_QSPI_SD2_CTRL(
        IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL &FUNCSEL,
        IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER &OUTOVER,
        IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER &OEOVER,
        IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER &INOVER,
        IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER &IRQOVER) volatile
    {
        uint32_t curr = GPIO_QSPI_SD2_CTRL;

        FUNCSEL = IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL((curr >> 0u) & 0b11111u);
        OUTOVER = IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER((curr >> 8u) & 0b11u);
        OEOVER = IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER((curr >> 12u) & 0b11u);
        INOVER = IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER((curr >> 16u) & 0b11u);
        IRQOVER = IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER((curr >> 28u) & 0b11u);
    }

    inline void set_GPIO_QSPI_SD2_CTRL(
        IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL FUNCSEL,
        IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER OUTOVER,
        IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER OEOVER,
        IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER INOVER,
        IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER IRQOVER) volatile
    {
        uint32_t curr = GPIO_QSPI_SD2_CTRL;

        curr &= ~(0b11111u << 0u);
        curr |= (std::to_underlying(FUNCSEL) & 0b11111u) << 0u;
        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(OUTOVER) & 0b11u) << 8u;
        curr &= ~(0b11u << 12u);
        curr |= (std::to_underlying(OEOVER) & 0b11u) << 12u;
        curr &= ~(0b11u << 16u);
        curr |= (std::to_underlying(INOVER) & 0b11u) << 16u;
        curr &= ~(0b11u << 28u);
        curr |= (std::to_underlying(IRQOVER) & 0b11u) << 28u;

        GPIO_QSPI_SD2_CTRL = curr;
    }

    inline bool get_GPIO_QSPI_SD3_STATUS_OUTFROMPERI() volatile
    {
        return GPIO_QSPI_SD3_STATUS & (1u << 8u);
    }

    inline bool get_GPIO_QSPI_SD3_STATUS_OUTTOPAD() volatile
    {
        return GPIO_QSPI_SD3_STATUS & (1u << 9u);
    }

    inline bool get_GPIO_QSPI_SD3_STATUS_OEFROMPERI() volatile
    {
        return GPIO_QSPI_SD3_STATUS & (1u << 12u);
    }

    inline bool get_GPIO_QSPI_SD3_STATUS_OETOPAD() volatile
    {
        return GPIO_QSPI_SD3_STATUS & (1u << 13u);
    }

    inline bool get_GPIO_QSPI_SD3_STATUS_INFROMPAD() volatile
    {
        return GPIO_QSPI_SD3_STATUS & (1u << 17u);
    }

    inline bool get_GPIO_QSPI_SD3_STATUS_INTOPERI() volatile
    {
        return GPIO_QSPI_SD3_STATUS & (1u << 19u);
    }

    inline bool get_GPIO_QSPI_SD3_STATUS_IRQFROMPAD() volatile
    {
        return GPIO_QSPI_SD3_STATUS & (1u << 24u);
    }

    inline bool get_GPIO_QSPI_SD3_STATUS_IRQTOPROC() volatile
    {
        return GPIO_QSPI_SD3_STATUS & (1u << 26u);
    }

    inline void get_GPIO_QSPI_SD3_STATUS(bool &OUTFROMPERI, bool &OUTTOPAD,
                                         bool &OEFROMPERI, bool &OETOPAD,
                                         bool &INFROMPAD, bool &INTOPERI,
                                         bool &IRQFROMPAD,
                                         bool &IRQTOPROC) volatile
    {
        uint32_t curr = GPIO_QSPI_SD3_STATUS;

        OUTFROMPERI = curr & (1u << 8u);
        OUTTOPAD = curr & (1u << 9u);
        OEFROMPERI = curr & (1u << 12u);
        OETOPAD = curr & (1u << 13u);
        INFROMPAD = curr & (1u << 17u);
        INTOPERI = curr & (1u << 19u);
        IRQFROMPAD = curr & (1u << 24u);
        IRQTOPROC = curr & (1u << 26u);
    }

    inline IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL
    get_GPIO_QSPI_SD3_CTRL_FUNCSEL() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL((GPIO_QSPI_SD3_CTRL >> 0u) &
                                                  0b11111u);
    }

    inline void set_GPIO_QSPI_SD3_CTRL_FUNCSEL(
        IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD3_CTRL;

        curr &= ~(0b11111u << 0u);
        curr |= (std::to_underlying(value) & 0b11111u) << 0u;

        GPIO_QSPI_SD3_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER
    get_GPIO_QSPI_SD3_CTRL_OUTOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER((GPIO_QSPI_SD3_CTRL >> 8u) &
                                                  0b11u);
    }

    inline void set_GPIO_QSPI_SD3_CTRL_OUTOVER(
        IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD3_CTRL;

        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(value) & 0b11u) << 8u;

        GPIO_QSPI_SD3_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER
    get_GPIO_QSPI_SD3_CTRL_OEOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER((GPIO_QSPI_SD3_CTRL >> 12u) &
                                                 0b11u);
    }

    inline void set_GPIO_QSPI_SD3_CTRL_OEOVER(
        IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD3_CTRL;

        curr &= ~(0b11u << 12u);
        curr |= (std::to_underlying(value) & 0b11u) << 12u;

        GPIO_QSPI_SD3_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER
    get_GPIO_QSPI_SD3_CTRL_INOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER((GPIO_QSPI_SD3_CTRL >> 16u) &
                                                 0b11u);
    }

    inline void set_GPIO_QSPI_SD3_CTRL_INOVER(
        IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD3_CTRL;

        curr &= ~(0b11u << 16u);
        curr |= (std::to_underlying(value) & 0b11u) << 16u;

        GPIO_QSPI_SD3_CTRL = curr;
    }

    inline IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER
    get_GPIO_QSPI_SD3_CTRL_IRQOVER() volatile
    {
        return IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER((GPIO_QSPI_SD3_CTRL >> 28u) &
                                                  0b11u);
    }

    inline void set_GPIO_QSPI_SD3_CTRL_IRQOVER(
        IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER value) volatile
    {
        uint32_t curr = GPIO_QSPI_SD3_CTRL;

        curr &= ~(0b11u << 28u);
        curr |= (std::to_underlying(value) & 0b11u) << 28u;

        GPIO_QSPI_SD3_CTRL = curr;
    }

    inline void get_GPIO_QSPI_SD3_CTRL(
        IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL &FUNCSEL,
        IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER &OUTOVER,
        IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER &OEOVER,
        IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER &INOVER,
        IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER &IRQOVER) volatile
    {
        uint32_t curr = GPIO_QSPI_SD3_CTRL;

        FUNCSEL = IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL((curr >> 0u) & 0b11111u);
        OUTOVER = IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER((curr >> 8u) & 0b11u);
        OEOVER = IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER((curr >> 12u) & 0b11u);
        INOVER = IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER((curr >> 16u) & 0b11u);
        IRQOVER = IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER((curr >> 28u) & 0b11u);
    }

    inline void set_GPIO_QSPI_SD3_CTRL(
        IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL FUNCSEL,
        IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER OUTOVER,
        IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER OEOVER,
        IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER INOVER,
        IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER IRQOVER) volatile
    {
        uint32_t curr = GPIO_QSPI_SD3_CTRL;

        curr &= ~(0b11111u << 0u);
        curr |= (std::to_underlying(FUNCSEL) & 0b11111u) << 0u;
        curr &= ~(0b11u << 8u);
        curr |= (std::to_underlying(OUTOVER) & 0b11u) << 8u;
        curr &= ~(0b11u << 12u);
        curr |= (std::to_underlying(OEOVER) & 0b11u) << 12u;
        curr &= ~(0b11u << 16u);
        curr |= (std::to_underlying(INOVER) & 0b11u) << 16u;
        curr &= ~(0b11u << 28u);
        curr |= (std::to_underlying(IRQOVER) & 0b11u) << 28u;

        GPIO_QSPI_SD3_CTRL = curr;
    }

    inline bool get_INTR_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        return INTR & (1u << 0u);
    }

    inline bool get_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        return INTR & (1u << 1u);
    }

    inline bool get_INTR_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        return INTR & (1u << 2u);
    }

    inline void set_INTR_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        INTR |= 1u << 2u;
    }

    inline void clear_INTR_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        INTR &= ~(1u << 2u);
    }

    inline void toggle_INTR_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        INTR ^= 1u << 2u;
    }

    inline bool get_INTR_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        return INTR & (1u << 3u);
    }

    inline void set_INTR_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        INTR |= 1u << 3u;
    }

    inline void clear_INTR_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        INTR &= ~(1u << 3u);
    }

    inline void toggle_INTR_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        INTR ^= 1u << 3u;
    }

    inline bool get_INTR_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        return INTR & (1u << 4u);
    }

    inline bool get_INTR_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        return INTR & (1u << 5u);
    }

    inline bool get_INTR_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        return INTR & (1u << 6u);
    }

    inline void set_INTR_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        INTR |= 1u << 6u;
    }

    inline void clear_INTR_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        INTR &= ~(1u << 6u);
    }

    inline void toggle_INTR_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        INTR ^= 1u << 6u;
    }

    inline bool get_INTR_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        return INTR & (1u << 7u);
    }

    inline void set_INTR_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        INTR |= 1u << 7u;
    }

    inline void clear_INTR_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        INTR &= ~(1u << 7u);
    }

    inline void toggle_INTR_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        INTR ^= 1u << 7u;
    }

    inline bool get_INTR_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        return INTR & (1u << 8u);
    }

    inline bool get_INTR_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        return INTR & (1u << 9u);
    }

    inline bool get_INTR_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        return INTR & (1u << 10u);
    }

    inline void set_INTR_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        INTR |= 1u << 10u;
    }

    inline void clear_INTR_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        INTR &= ~(1u << 10u);
    }

    inline void toggle_INTR_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        INTR ^= 1u << 10u;
    }

    inline bool get_INTR_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        return INTR & (1u << 11u);
    }

    inline void set_INTR_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        INTR |= 1u << 11u;
    }

    inline void clear_INTR_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        INTR &= ~(1u << 11u);
    }

    inline void toggle_INTR_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        INTR ^= 1u << 11u;
    }

    inline bool get_INTR_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        return INTR & (1u << 12u);
    }

    inline bool get_INTR_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        return INTR & (1u << 13u);
    }

    inline bool get_INTR_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        return INTR & (1u << 14u);
    }

    inline void set_INTR_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        INTR |= 1u << 14u;
    }

    inline void clear_INTR_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        INTR &= ~(1u << 14u);
    }

    inline void toggle_INTR_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        INTR ^= 1u << 14u;
    }

    inline bool get_INTR_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        return INTR & (1u << 15u);
    }

    inline void set_INTR_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        INTR |= 1u << 15u;
    }

    inline void clear_INTR_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        INTR &= ~(1u << 15u);
    }

    inline void toggle_INTR_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        INTR ^= 1u << 15u;
    }

    inline bool get_INTR_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        return INTR & (1u << 16u);
    }

    inline bool get_INTR_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        return INTR & (1u << 17u);
    }

    inline bool get_INTR_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        return INTR & (1u << 18u);
    }

    inline void set_INTR_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        INTR |= 1u << 18u;
    }

    inline void clear_INTR_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        INTR &= ~(1u << 18u);
    }

    inline void toggle_INTR_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        INTR ^= 1u << 18u;
    }

    inline bool get_INTR_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        return INTR & (1u << 19u);
    }

    inline void set_INTR_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        INTR |= 1u << 19u;
    }

    inline void clear_INTR_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        INTR &= ~(1u << 19u);
    }

    inline void toggle_INTR_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        INTR ^= 1u << 19u;
    }

    inline bool get_INTR_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        return INTR & (1u << 20u);
    }

    inline bool get_INTR_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        return INTR & (1u << 21u);
    }

    inline bool get_INTR_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        return INTR & (1u << 22u);
    }

    inline void set_INTR_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        INTR |= 1u << 22u;
    }

    inline void clear_INTR_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        INTR &= ~(1u << 22u);
    }

    inline void toggle_INTR_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        INTR ^= 1u << 22u;
    }

    inline bool get_INTR_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        return INTR & (1u << 23u);
    }

    inline void set_INTR_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        INTR |= 1u << 23u;
    }

    inline void clear_INTR_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        INTR &= ~(1u << 23u);
    }

    inline void toggle_INTR_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        INTR ^= 1u << 23u;
    }

    inline void get_INTR(
        bool &GPIO_QSPI_SCLK_LEVEL_LOW, bool &GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool &GPIO_QSPI_SCLK_EDGE_LOW, bool &GPIO_QSPI_SCLK_EDGE_HIGH,
        bool &GPIO_QSPI_SS_LEVEL_LOW, bool &GPIO_QSPI_SS_LEVEL_HIGH,
        bool &GPIO_QSPI_SS_EDGE_LOW, bool &GPIO_QSPI_SS_EDGE_HIGH,
        bool &GPIO_QSPI_SD0_LEVEL_LOW, bool &GPIO_QSPI_SD0_LEVEL_HIGH,
        bool &GPIO_QSPI_SD0_EDGE_LOW, bool &GPIO_QSPI_SD0_EDGE_HIGH,
        bool &GPIO_QSPI_SD1_LEVEL_LOW, bool &GPIO_QSPI_SD1_LEVEL_HIGH,
        bool &GPIO_QSPI_SD1_EDGE_LOW, bool &GPIO_QSPI_SD1_EDGE_HIGH,
        bool &GPIO_QSPI_SD2_LEVEL_LOW, bool &GPIO_QSPI_SD2_LEVEL_HIGH,
        bool &GPIO_QSPI_SD2_EDGE_LOW, bool &GPIO_QSPI_SD2_EDGE_HIGH,
        bool &GPIO_QSPI_SD3_LEVEL_LOW, bool &GPIO_QSPI_SD3_LEVEL_HIGH,
        bool &GPIO_QSPI_SD3_EDGE_LOW, bool &GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = INTR;

        GPIO_QSPI_SCLK_LEVEL_LOW = curr & (1u << 0u);
        GPIO_QSPI_SCLK_LEVEL_HIGH = curr & (1u << 1u);
        GPIO_QSPI_SCLK_EDGE_LOW = curr & (1u << 2u);
        GPIO_QSPI_SCLK_EDGE_HIGH = curr & (1u << 3u);
        GPIO_QSPI_SS_LEVEL_LOW = curr & (1u << 4u);
        GPIO_QSPI_SS_LEVEL_HIGH = curr & (1u << 5u);
        GPIO_QSPI_SS_EDGE_LOW = curr & (1u << 6u);
        GPIO_QSPI_SS_EDGE_HIGH = curr & (1u << 7u);
        GPIO_QSPI_SD0_LEVEL_LOW = curr & (1u << 8u);
        GPIO_QSPI_SD0_LEVEL_HIGH = curr & (1u << 9u);
        GPIO_QSPI_SD0_EDGE_LOW = curr & (1u << 10u);
        GPIO_QSPI_SD0_EDGE_HIGH = curr & (1u << 11u);
        GPIO_QSPI_SD1_LEVEL_LOW = curr & (1u << 12u);
        GPIO_QSPI_SD1_LEVEL_HIGH = curr & (1u << 13u);
        GPIO_QSPI_SD1_EDGE_LOW = curr & (1u << 14u);
        GPIO_QSPI_SD1_EDGE_HIGH = curr & (1u << 15u);
        GPIO_QSPI_SD2_LEVEL_LOW = curr & (1u << 16u);
        GPIO_QSPI_SD2_LEVEL_HIGH = curr & (1u << 17u);
        GPIO_QSPI_SD2_EDGE_LOW = curr & (1u << 18u);
        GPIO_QSPI_SD2_EDGE_HIGH = curr & (1u << 19u);
        GPIO_QSPI_SD3_LEVEL_LOW = curr & (1u << 20u);
        GPIO_QSPI_SD3_LEVEL_HIGH = curr & (1u << 21u);
        GPIO_QSPI_SD3_EDGE_LOW = curr & (1u << 22u);
        GPIO_QSPI_SD3_EDGE_HIGH = curr & (1u << 23u);
    }

    inline void set_INTR(
        bool GPIO_QSPI_SCLK_EDGE_LOW, bool GPIO_QSPI_SCLK_EDGE_HIGH,
        bool GPIO_QSPI_SS_EDGE_LOW, bool GPIO_QSPI_SS_EDGE_HIGH,
        bool GPIO_QSPI_SD0_EDGE_LOW, bool GPIO_QSPI_SD0_EDGE_HIGH,
        bool GPIO_QSPI_SD1_EDGE_LOW, bool GPIO_QSPI_SD1_EDGE_HIGH,
        bool GPIO_QSPI_SD2_EDGE_LOW, bool GPIO_QSPI_SD2_EDGE_HIGH,
        bool GPIO_QSPI_SD3_EDGE_LOW, bool GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = INTR;

        curr &= ~(0b1u << 2u);
        curr |= (GPIO_QSPI_SCLK_EDGE_LOW & 0b1u) << 2u;
        curr &= ~(0b1u << 3u);
        curr |= (GPIO_QSPI_SCLK_EDGE_HIGH & 0b1u) << 3u;
        curr &= ~(0b1u << 6u);
        curr |= (GPIO_QSPI_SS_EDGE_LOW & 0b1u) << 6u;
        curr &= ~(0b1u << 7u);
        curr |= (GPIO_QSPI_SS_EDGE_HIGH & 0b1u) << 7u;
        curr &= ~(0b1u << 10u);
        curr |= (GPIO_QSPI_SD0_EDGE_LOW & 0b1u) << 10u;
        curr &= ~(0b1u << 11u);
        curr |= (GPIO_QSPI_SD0_EDGE_HIGH & 0b1u) << 11u;
        curr &= ~(0b1u << 14u);
        curr |= (GPIO_QSPI_SD1_EDGE_LOW & 0b1u) << 14u;
        curr &= ~(0b1u << 15u);
        curr |= (GPIO_QSPI_SD1_EDGE_HIGH & 0b1u) << 15u;
        curr &= ~(0b1u << 18u);
        curr |= (GPIO_QSPI_SD2_EDGE_LOW & 0b1u) << 18u;
        curr &= ~(0b1u << 19u);
        curr |= (GPIO_QSPI_SD2_EDGE_HIGH & 0b1u) << 19u;
        curr &= ~(0b1u << 22u);
        curr |= (GPIO_QSPI_SD3_EDGE_LOW & 0b1u) << 22u;
        curr &= ~(0b1u << 23u);
        curr |= (GPIO_QSPI_SD3_EDGE_HIGH & 0b1u) << 23u;

        INTR = curr;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        return PROC0_INTE & (1u << 0u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        PROC0_INTE |= 1u << 0u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        PROC0_INTE &= ~(1u << 0u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        PROC0_INTE ^= 1u << 0u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        return PROC0_INTE & (1u << 1u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        PROC0_INTE |= 1u << 1u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        PROC0_INTE &= ~(1u << 1u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        PROC0_INTE ^= 1u << 1u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        return PROC0_INTE & (1u << 2u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        PROC0_INTE |= 1u << 2u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        PROC0_INTE &= ~(1u << 2u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        PROC0_INTE ^= 1u << 2u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        return PROC0_INTE & (1u << 3u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        PROC0_INTE |= 1u << 3u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        PROC0_INTE &= ~(1u << 3u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        PROC0_INTE ^= 1u << 3u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        return PROC0_INTE & (1u << 4u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        PROC0_INTE |= 1u << 4u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        PROC0_INTE &= ~(1u << 4u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        PROC0_INTE ^= 1u << 4u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        return PROC0_INTE & (1u << 5u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        PROC0_INTE |= 1u << 5u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        PROC0_INTE &= ~(1u << 5u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        PROC0_INTE ^= 1u << 5u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        return PROC0_INTE & (1u << 6u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        PROC0_INTE |= 1u << 6u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        PROC0_INTE &= ~(1u << 6u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        PROC0_INTE ^= 1u << 6u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        return PROC0_INTE & (1u << 7u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        PROC0_INTE |= 1u << 7u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        PROC0_INTE &= ~(1u << 7u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        PROC0_INTE ^= 1u << 7u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        return PROC0_INTE & (1u << 8u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        PROC0_INTE |= 1u << 8u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        PROC0_INTE &= ~(1u << 8u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        PROC0_INTE ^= 1u << 8u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        return PROC0_INTE & (1u << 9u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        PROC0_INTE |= 1u << 9u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        PROC0_INTE &= ~(1u << 9u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        PROC0_INTE ^= 1u << 9u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        return PROC0_INTE & (1u << 10u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        PROC0_INTE |= 1u << 10u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        PROC0_INTE &= ~(1u << 10u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        PROC0_INTE ^= 1u << 10u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        return PROC0_INTE & (1u << 11u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        PROC0_INTE |= 1u << 11u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        PROC0_INTE &= ~(1u << 11u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        PROC0_INTE ^= 1u << 11u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        return PROC0_INTE & (1u << 12u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        PROC0_INTE |= 1u << 12u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        PROC0_INTE &= ~(1u << 12u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        PROC0_INTE ^= 1u << 12u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        return PROC0_INTE & (1u << 13u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        PROC0_INTE |= 1u << 13u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        PROC0_INTE &= ~(1u << 13u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        PROC0_INTE ^= 1u << 13u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        return PROC0_INTE & (1u << 14u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        PROC0_INTE |= 1u << 14u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        PROC0_INTE &= ~(1u << 14u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        PROC0_INTE ^= 1u << 14u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        return PROC0_INTE & (1u << 15u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        PROC0_INTE |= 1u << 15u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        PROC0_INTE &= ~(1u << 15u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        PROC0_INTE ^= 1u << 15u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        return PROC0_INTE & (1u << 16u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        PROC0_INTE |= 1u << 16u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        PROC0_INTE &= ~(1u << 16u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        PROC0_INTE ^= 1u << 16u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        return PROC0_INTE & (1u << 17u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        PROC0_INTE |= 1u << 17u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        PROC0_INTE &= ~(1u << 17u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        PROC0_INTE ^= 1u << 17u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        return PROC0_INTE & (1u << 18u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        PROC0_INTE |= 1u << 18u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        PROC0_INTE &= ~(1u << 18u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        PROC0_INTE ^= 1u << 18u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        return PROC0_INTE & (1u << 19u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        PROC0_INTE |= 1u << 19u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        PROC0_INTE &= ~(1u << 19u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        PROC0_INTE ^= 1u << 19u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        return PROC0_INTE & (1u << 20u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        PROC0_INTE |= 1u << 20u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        PROC0_INTE &= ~(1u << 20u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        PROC0_INTE ^= 1u << 20u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        return PROC0_INTE & (1u << 21u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        PROC0_INTE |= 1u << 21u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        PROC0_INTE &= ~(1u << 21u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        PROC0_INTE ^= 1u << 21u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        return PROC0_INTE & (1u << 22u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        PROC0_INTE |= 1u << 22u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        PROC0_INTE &= ~(1u << 22u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        PROC0_INTE ^= 1u << 22u;
    }

    inline bool get_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        return PROC0_INTE & (1u << 23u);
    }

    inline void set_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        PROC0_INTE |= 1u << 23u;
    }

    inline void clear_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        PROC0_INTE &= ~(1u << 23u);
    }

    inline void toggle_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        PROC0_INTE ^= 1u << 23u;
    }

    inline void get_PROC0_INTE(
        bool &GPIO_QSPI_SCLK_LEVEL_LOW, bool &GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool &GPIO_QSPI_SCLK_EDGE_LOW, bool &GPIO_QSPI_SCLK_EDGE_HIGH,
        bool &GPIO_QSPI_SS_LEVEL_LOW, bool &GPIO_QSPI_SS_LEVEL_HIGH,
        bool &GPIO_QSPI_SS_EDGE_LOW, bool &GPIO_QSPI_SS_EDGE_HIGH,
        bool &GPIO_QSPI_SD0_LEVEL_LOW, bool &GPIO_QSPI_SD0_LEVEL_HIGH,
        bool &GPIO_QSPI_SD0_EDGE_LOW, bool &GPIO_QSPI_SD0_EDGE_HIGH,
        bool &GPIO_QSPI_SD1_LEVEL_LOW, bool &GPIO_QSPI_SD1_LEVEL_HIGH,
        bool &GPIO_QSPI_SD1_EDGE_LOW, bool &GPIO_QSPI_SD1_EDGE_HIGH,
        bool &GPIO_QSPI_SD2_LEVEL_LOW, bool &GPIO_QSPI_SD2_LEVEL_HIGH,
        bool &GPIO_QSPI_SD2_EDGE_LOW, bool &GPIO_QSPI_SD2_EDGE_HIGH,
        bool &GPIO_QSPI_SD3_LEVEL_LOW, bool &GPIO_QSPI_SD3_LEVEL_HIGH,
        bool &GPIO_QSPI_SD3_EDGE_LOW, bool &GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = PROC0_INTE;

        GPIO_QSPI_SCLK_LEVEL_LOW = curr & (1u << 0u);
        GPIO_QSPI_SCLK_LEVEL_HIGH = curr & (1u << 1u);
        GPIO_QSPI_SCLK_EDGE_LOW = curr & (1u << 2u);
        GPIO_QSPI_SCLK_EDGE_HIGH = curr & (1u << 3u);
        GPIO_QSPI_SS_LEVEL_LOW = curr & (1u << 4u);
        GPIO_QSPI_SS_LEVEL_HIGH = curr & (1u << 5u);
        GPIO_QSPI_SS_EDGE_LOW = curr & (1u << 6u);
        GPIO_QSPI_SS_EDGE_HIGH = curr & (1u << 7u);
        GPIO_QSPI_SD0_LEVEL_LOW = curr & (1u << 8u);
        GPIO_QSPI_SD0_LEVEL_HIGH = curr & (1u << 9u);
        GPIO_QSPI_SD0_EDGE_LOW = curr & (1u << 10u);
        GPIO_QSPI_SD0_EDGE_HIGH = curr & (1u << 11u);
        GPIO_QSPI_SD1_LEVEL_LOW = curr & (1u << 12u);
        GPIO_QSPI_SD1_LEVEL_HIGH = curr & (1u << 13u);
        GPIO_QSPI_SD1_EDGE_LOW = curr & (1u << 14u);
        GPIO_QSPI_SD1_EDGE_HIGH = curr & (1u << 15u);
        GPIO_QSPI_SD2_LEVEL_LOW = curr & (1u << 16u);
        GPIO_QSPI_SD2_LEVEL_HIGH = curr & (1u << 17u);
        GPIO_QSPI_SD2_EDGE_LOW = curr & (1u << 18u);
        GPIO_QSPI_SD2_EDGE_HIGH = curr & (1u << 19u);
        GPIO_QSPI_SD3_LEVEL_LOW = curr & (1u << 20u);
        GPIO_QSPI_SD3_LEVEL_HIGH = curr & (1u << 21u);
        GPIO_QSPI_SD3_EDGE_LOW = curr & (1u << 22u);
        GPIO_QSPI_SD3_EDGE_HIGH = curr & (1u << 23u);
    }

    inline void set_PROC0_INTE(
        bool GPIO_QSPI_SCLK_LEVEL_LOW, bool GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool GPIO_QSPI_SCLK_EDGE_LOW, bool GPIO_QSPI_SCLK_EDGE_HIGH,
        bool GPIO_QSPI_SS_LEVEL_LOW, bool GPIO_QSPI_SS_LEVEL_HIGH,
        bool GPIO_QSPI_SS_EDGE_LOW, bool GPIO_QSPI_SS_EDGE_HIGH,
        bool GPIO_QSPI_SD0_LEVEL_LOW, bool GPIO_QSPI_SD0_LEVEL_HIGH,
        bool GPIO_QSPI_SD0_EDGE_LOW, bool GPIO_QSPI_SD0_EDGE_HIGH,
        bool GPIO_QSPI_SD1_LEVEL_LOW, bool GPIO_QSPI_SD1_LEVEL_HIGH,
        bool GPIO_QSPI_SD1_EDGE_LOW, bool GPIO_QSPI_SD1_EDGE_HIGH,
        bool GPIO_QSPI_SD2_LEVEL_LOW, bool GPIO_QSPI_SD2_LEVEL_HIGH,
        bool GPIO_QSPI_SD2_EDGE_LOW, bool GPIO_QSPI_SD2_EDGE_HIGH,
        bool GPIO_QSPI_SD3_LEVEL_LOW, bool GPIO_QSPI_SD3_LEVEL_HIGH,
        bool GPIO_QSPI_SD3_EDGE_LOW, bool GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = PROC0_INTE;

        curr &= ~(0b1u << 0u);
        curr |= (GPIO_QSPI_SCLK_LEVEL_LOW & 0b1u) << 0u;
        curr &= ~(0b1u << 1u);
        curr |= (GPIO_QSPI_SCLK_LEVEL_HIGH & 0b1u) << 1u;
        curr &= ~(0b1u << 2u);
        curr |= (GPIO_QSPI_SCLK_EDGE_LOW & 0b1u) << 2u;
        curr &= ~(0b1u << 3u);
        curr |= (GPIO_QSPI_SCLK_EDGE_HIGH & 0b1u) << 3u;
        curr &= ~(0b1u << 4u);
        curr |= (GPIO_QSPI_SS_LEVEL_LOW & 0b1u) << 4u;
        curr &= ~(0b1u << 5u);
        curr |= (GPIO_QSPI_SS_LEVEL_HIGH & 0b1u) << 5u;
        curr &= ~(0b1u << 6u);
        curr |= (GPIO_QSPI_SS_EDGE_LOW & 0b1u) << 6u;
        curr &= ~(0b1u << 7u);
        curr |= (GPIO_QSPI_SS_EDGE_HIGH & 0b1u) << 7u;
        curr &= ~(0b1u << 8u);
        curr |= (GPIO_QSPI_SD0_LEVEL_LOW & 0b1u) << 8u;
        curr &= ~(0b1u << 9u);
        curr |= (GPIO_QSPI_SD0_LEVEL_HIGH & 0b1u) << 9u;
        curr &= ~(0b1u << 10u);
        curr |= (GPIO_QSPI_SD0_EDGE_LOW & 0b1u) << 10u;
        curr &= ~(0b1u << 11u);
        curr |= (GPIO_QSPI_SD0_EDGE_HIGH & 0b1u) << 11u;
        curr &= ~(0b1u << 12u);
        curr |= (GPIO_QSPI_SD1_LEVEL_LOW & 0b1u) << 12u;
        curr &= ~(0b1u << 13u);
        curr |= (GPIO_QSPI_SD1_LEVEL_HIGH & 0b1u) << 13u;
        curr &= ~(0b1u << 14u);
        curr |= (GPIO_QSPI_SD1_EDGE_LOW & 0b1u) << 14u;
        curr &= ~(0b1u << 15u);
        curr |= (GPIO_QSPI_SD1_EDGE_HIGH & 0b1u) << 15u;
        curr &= ~(0b1u << 16u);
        curr |= (GPIO_QSPI_SD2_LEVEL_LOW & 0b1u) << 16u;
        curr &= ~(0b1u << 17u);
        curr |= (GPIO_QSPI_SD2_LEVEL_HIGH & 0b1u) << 17u;
        curr &= ~(0b1u << 18u);
        curr |= (GPIO_QSPI_SD2_EDGE_LOW & 0b1u) << 18u;
        curr &= ~(0b1u << 19u);
        curr |= (GPIO_QSPI_SD2_EDGE_HIGH & 0b1u) << 19u;
        curr &= ~(0b1u << 20u);
        curr |= (GPIO_QSPI_SD3_LEVEL_LOW & 0b1u) << 20u;
        curr &= ~(0b1u << 21u);
        curr |= (GPIO_QSPI_SD3_LEVEL_HIGH & 0b1u) << 21u;
        curr &= ~(0b1u << 22u);
        curr |= (GPIO_QSPI_SD3_EDGE_LOW & 0b1u) << 22u;
        curr &= ~(0b1u << 23u);
        curr |= (GPIO_QSPI_SD3_EDGE_HIGH & 0b1u) << 23u;

        PROC0_INTE = curr;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        return PROC0_INTF & (1u << 0u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        PROC0_INTF |= 1u << 0u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        PROC0_INTF &= ~(1u << 0u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        PROC0_INTF ^= 1u << 0u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        return PROC0_INTF & (1u << 1u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        PROC0_INTF |= 1u << 1u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        PROC0_INTF &= ~(1u << 1u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        PROC0_INTF ^= 1u << 1u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        return PROC0_INTF & (1u << 2u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        PROC0_INTF |= 1u << 2u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        PROC0_INTF &= ~(1u << 2u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        PROC0_INTF ^= 1u << 2u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        return PROC0_INTF & (1u << 3u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        PROC0_INTF |= 1u << 3u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        PROC0_INTF &= ~(1u << 3u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        PROC0_INTF ^= 1u << 3u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        return PROC0_INTF & (1u << 4u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        PROC0_INTF |= 1u << 4u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        PROC0_INTF &= ~(1u << 4u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        PROC0_INTF ^= 1u << 4u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        return PROC0_INTF & (1u << 5u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        PROC0_INTF |= 1u << 5u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        PROC0_INTF &= ~(1u << 5u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        PROC0_INTF ^= 1u << 5u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        return PROC0_INTF & (1u << 6u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        PROC0_INTF |= 1u << 6u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        PROC0_INTF &= ~(1u << 6u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        PROC0_INTF ^= 1u << 6u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        return PROC0_INTF & (1u << 7u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        PROC0_INTF |= 1u << 7u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        PROC0_INTF &= ~(1u << 7u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        PROC0_INTF ^= 1u << 7u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        return PROC0_INTF & (1u << 8u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        PROC0_INTF |= 1u << 8u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        PROC0_INTF &= ~(1u << 8u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        PROC0_INTF ^= 1u << 8u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        return PROC0_INTF & (1u << 9u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        PROC0_INTF |= 1u << 9u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        PROC0_INTF &= ~(1u << 9u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        PROC0_INTF ^= 1u << 9u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        return PROC0_INTF & (1u << 10u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        PROC0_INTF |= 1u << 10u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        PROC0_INTF &= ~(1u << 10u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        PROC0_INTF ^= 1u << 10u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        return PROC0_INTF & (1u << 11u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        PROC0_INTF |= 1u << 11u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        PROC0_INTF &= ~(1u << 11u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        PROC0_INTF ^= 1u << 11u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        return PROC0_INTF & (1u << 12u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        PROC0_INTF |= 1u << 12u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        PROC0_INTF &= ~(1u << 12u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        PROC0_INTF ^= 1u << 12u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        return PROC0_INTF & (1u << 13u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        PROC0_INTF |= 1u << 13u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        PROC0_INTF &= ~(1u << 13u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        PROC0_INTF ^= 1u << 13u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        return PROC0_INTF & (1u << 14u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        PROC0_INTF |= 1u << 14u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        PROC0_INTF &= ~(1u << 14u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        PROC0_INTF ^= 1u << 14u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        return PROC0_INTF & (1u << 15u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        PROC0_INTF |= 1u << 15u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        PROC0_INTF &= ~(1u << 15u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        PROC0_INTF ^= 1u << 15u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        return PROC0_INTF & (1u << 16u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        PROC0_INTF |= 1u << 16u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        PROC0_INTF &= ~(1u << 16u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        PROC0_INTF ^= 1u << 16u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        return PROC0_INTF & (1u << 17u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        PROC0_INTF |= 1u << 17u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        PROC0_INTF &= ~(1u << 17u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        PROC0_INTF ^= 1u << 17u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        return PROC0_INTF & (1u << 18u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        PROC0_INTF |= 1u << 18u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        PROC0_INTF &= ~(1u << 18u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        PROC0_INTF ^= 1u << 18u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        return PROC0_INTF & (1u << 19u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        PROC0_INTF |= 1u << 19u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        PROC0_INTF &= ~(1u << 19u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        PROC0_INTF ^= 1u << 19u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        return PROC0_INTF & (1u << 20u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        PROC0_INTF |= 1u << 20u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        PROC0_INTF &= ~(1u << 20u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        PROC0_INTF ^= 1u << 20u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        return PROC0_INTF & (1u << 21u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        PROC0_INTF |= 1u << 21u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        PROC0_INTF &= ~(1u << 21u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        PROC0_INTF ^= 1u << 21u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        return PROC0_INTF & (1u << 22u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        PROC0_INTF |= 1u << 22u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        PROC0_INTF &= ~(1u << 22u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        PROC0_INTF ^= 1u << 22u;
    }

    inline bool get_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        return PROC0_INTF & (1u << 23u);
    }

    inline void set_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        PROC0_INTF |= 1u << 23u;
    }

    inline void clear_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        PROC0_INTF &= ~(1u << 23u);
    }

    inline void toggle_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        PROC0_INTF ^= 1u << 23u;
    }

    inline void get_PROC0_INTF(
        bool &GPIO_QSPI_SCLK_LEVEL_LOW, bool &GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool &GPIO_QSPI_SCLK_EDGE_LOW, bool &GPIO_QSPI_SCLK_EDGE_HIGH,
        bool &GPIO_QSPI_SS_LEVEL_LOW, bool &GPIO_QSPI_SS_LEVEL_HIGH,
        bool &GPIO_QSPI_SS_EDGE_LOW, bool &GPIO_QSPI_SS_EDGE_HIGH,
        bool &GPIO_QSPI_SD0_LEVEL_LOW, bool &GPIO_QSPI_SD0_LEVEL_HIGH,
        bool &GPIO_QSPI_SD0_EDGE_LOW, bool &GPIO_QSPI_SD0_EDGE_HIGH,
        bool &GPIO_QSPI_SD1_LEVEL_LOW, bool &GPIO_QSPI_SD1_LEVEL_HIGH,
        bool &GPIO_QSPI_SD1_EDGE_LOW, bool &GPIO_QSPI_SD1_EDGE_HIGH,
        bool &GPIO_QSPI_SD2_LEVEL_LOW, bool &GPIO_QSPI_SD2_LEVEL_HIGH,
        bool &GPIO_QSPI_SD2_EDGE_LOW, bool &GPIO_QSPI_SD2_EDGE_HIGH,
        bool &GPIO_QSPI_SD3_LEVEL_LOW, bool &GPIO_QSPI_SD3_LEVEL_HIGH,
        bool &GPIO_QSPI_SD3_EDGE_LOW, bool &GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = PROC0_INTF;

        GPIO_QSPI_SCLK_LEVEL_LOW = curr & (1u << 0u);
        GPIO_QSPI_SCLK_LEVEL_HIGH = curr & (1u << 1u);
        GPIO_QSPI_SCLK_EDGE_LOW = curr & (1u << 2u);
        GPIO_QSPI_SCLK_EDGE_HIGH = curr & (1u << 3u);
        GPIO_QSPI_SS_LEVEL_LOW = curr & (1u << 4u);
        GPIO_QSPI_SS_LEVEL_HIGH = curr & (1u << 5u);
        GPIO_QSPI_SS_EDGE_LOW = curr & (1u << 6u);
        GPIO_QSPI_SS_EDGE_HIGH = curr & (1u << 7u);
        GPIO_QSPI_SD0_LEVEL_LOW = curr & (1u << 8u);
        GPIO_QSPI_SD0_LEVEL_HIGH = curr & (1u << 9u);
        GPIO_QSPI_SD0_EDGE_LOW = curr & (1u << 10u);
        GPIO_QSPI_SD0_EDGE_HIGH = curr & (1u << 11u);
        GPIO_QSPI_SD1_LEVEL_LOW = curr & (1u << 12u);
        GPIO_QSPI_SD1_LEVEL_HIGH = curr & (1u << 13u);
        GPIO_QSPI_SD1_EDGE_LOW = curr & (1u << 14u);
        GPIO_QSPI_SD1_EDGE_HIGH = curr & (1u << 15u);
        GPIO_QSPI_SD2_LEVEL_LOW = curr & (1u << 16u);
        GPIO_QSPI_SD2_LEVEL_HIGH = curr & (1u << 17u);
        GPIO_QSPI_SD2_EDGE_LOW = curr & (1u << 18u);
        GPIO_QSPI_SD2_EDGE_HIGH = curr & (1u << 19u);
        GPIO_QSPI_SD3_LEVEL_LOW = curr & (1u << 20u);
        GPIO_QSPI_SD3_LEVEL_HIGH = curr & (1u << 21u);
        GPIO_QSPI_SD3_EDGE_LOW = curr & (1u << 22u);
        GPIO_QSPI_SD3_EDGE_HIGH = curr & (1u << 23u);
    }

    inline void set_PROC0_INTF(
        bool GPIO_QSPI_SCLK_LEVEL_LOW, bool GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool GPIO_QSPI_SCLK_EDGE_LOW, bool GPIO_QSPI_SCLK_EDGE_HIGH,
        bool GPIO_QSPI_SS_LEVEL_LOW, bool GPIO_QSPI_SS_LEVEL_HIGH,
        bool GPIO_QSPI_SS_EDGE_LOW, bool GPIO_QSPI_SS_EDGE_HIGH,
        bool GPIO_QSPI_SD0_LEVEL_LOW, bool GPIO_QSPI_SD0_LEVEL_HIGH,
        bool GPIO_QSPI_SD0_EDGE_LOW, bool GPIO_QSPI_SD0_EDGE_HIGH,
        bool GPIO_QSPI_SD1_LEVEL_LOW, bool GPIO_QSPI_SD1_LEVEL_HIGH,
        bool GPIO_QSPI_SD1_EDGE_LOW, bool GPIO_QSPI_SD1_EDGE_HIGH,
        bool GPIO_QSPI_SD2_LEVEL_LOW, bool GPIO_QSPI_SD2_LEVEL_HIGH,
        bool GPIO_QSPI_SD2_EDGE_LOW, bool GPIO_QSPI_SD2_EDGE_HIGH,
        bool GPIO_QSPI_SD3_LEVEL_LOW, bool GPIO_QSPI_SD3_LEVEL_HIGH,
        bool GPIO_QSPI_SD3_EDGE_LOW, bool GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = PROC0_INTF;

        curr &= ~(0b1u << 0u);
        curr |= (GPIO_QSPI_SCLK_LEVEL_LOW & 0b1u) << 0u;
        curr &= ~(0b1u << 1u);
        curr |= (GPIO_QSPI_SCLK_LEVEL_HIGH & 0b1u) << 1u;
        curr &= ~(0b1u << 2u);
        curr |= (GPIO_QSPI_SCLK_EDGE_LOW & 0b1u) << 2u;
        curr &= ~(0b1u << 3u);
        curr |= (GPIO_QSPI_SCLK_EDGE_HIGH & 0b1u) << 3u;
        curr &= ~(0b1u << 4u);
        curr |= (GPIO_QSPI_SS_LEVEL_LOW & 0b1u) << 4u;
        curr &= ~(0b1u << 5u);
        curr |= (GPIO_QSPI_SS_LEVEL_HIGH & 0b1u) << 5u;
        curr &= ~(0b1u << 6u);
        curr |= (GPIO_QSPI_SS_EDGE_LOW & 0b1u) << 6u;
        curr &= ~(0b1u << 7u);
        curr |= (GPIO_QSPI_SS_EDGE_HIGH & 0b1u) << 7u;
        curr &= ~(0b1u << 8u);
        curr |= (GPIO_QSPI_SD0_LEVEL_LOW & 0b1u) << 8u;
        curr &= ~(0b1u << 9u);
        curr |= (GPIO_QSPI_SD0_LEVEL_HIGH & 0b1u) << 9u;
        curr &= ~(0b1u << 10u);
        curr |= (GPIO_QSPI_SD0_EDGE_LOW & 0b1u) << 10u;
        curr &= ~(0b1u << 11u);
        curr |= (GPIO_QSPI_SD0_EDGE_HIGH & 0b1u) << 11u;
        curr &= ~(0b1u << 12u);
        curr |= (GPIO_QSPI_SD1_LEVEL_LOW & 0b1u) << 12u;
        curr &= ~(0b1u << 13u);
        curr |= (GPIO_QSPI_SD1_LEVEL_HIGH & 0b1u) << 13u;
        curr &= ~(0b1u << 14u);
        curr |= (GPIO_QSPI_SD1_EDGE_LOW & 0b1u) << 14u;
        curr &= ~(0b1u << 15u);
        curr |= (GPIO_QSPI_SD1_EDGE_HIGH & 0b1u) << 15u;
        curr &= ~(0b1u << 16u);
        curr |= (GPIO_QSPI_SD2_LEVEL_LOW & 0b1u) << 16u;
        curr &= ~(0b1u << 17u);
        curr |= (GPIO_QSPI_SD2_LEVEL_HIGH & 0b1u) << 17u;
        curr &= ~(0b1u << 18u);
        curr |= (GPIO_QSPI_SD2_EDGE_LOW & 0b1u) << 18u;
        curr &= ~(0b1u << 19u);
        curr |= (GPIO_QSPI_SD2_EDGE_HIGH & 0b1u) << 19u;
        curr &= ~(0b1u << 20u);
        curr |= (GPIO_QSPI_SD3_LEVEL_LOW & 0b1u) << 20u;
        curr &= ~(0b1u << 21u);
        curr |= (GPIO_QSPI_SD3_LEVEL_HIGH & 0b1u) << 21u;
        curr &= ~(0b1u << 22u);
        curr |= (GPIO_QSPI_SD3_EDGE_LOW & 0b1u) << 22u;
        curr &= ~(0b1u << 23u);
        curr |= (GPIO_QSPI_SD3_EDGE_HIGH & 0b1u) << 23u;

        PROC0_INTF = curr;
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        return PROC0_INTS & (1u << 0u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        return PROC0_INTS & (1u << 1u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        return PROC0_INTS & (1u << 2u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        return PROC0_INTS & (1u << 3u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        return PROC0_INTS & (1u << 4u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        return PROC0_INTS & (1u << 5u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        return PROC0_INTS & (1u << 6u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        return PROC0_INTS & (1u << 7u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        return PROC0_INTS & (1u << 8u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        return PROC0_INTS & (1u << 9u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        return PROC0_INTS & (1u << 10u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        return PROC0_INTS & (1u << 11u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        return PROC0_INTS & (1u << 12u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        return PROC0_INTS & (1u << 13u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        return PROC0_INTS & (1u << 14u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        return PROC0_INTS & (1u << 15u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        return PROC0_INTS & (1u << 16u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        return PROC0_INTS & (1u << 17u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        return PROC0_INTS & (1u << 18u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        return PROC0_INTS & (1u << 19u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        return PROC0_INTS & (1u << 20u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        return PROC0_INTS & (1u << 21u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        return PROC0_INTS & (1u << 22u);
    }

    inline bool get_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        return PROC0_INTS & (1u << 23u);
    }

    inline void get_PROC0_INTS(
        bool &GPIO_QSPI_SCLK_LEVEL_LOW, bool &GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool &GPIO_QSPI_SCLK_EDGE_LOW, bool &GPIO_QSPI_SCLK_EDGE_HIGH,
        bool &GPIO_QSPI_SS_LEVEL_LOW, bool &GPIO_QSPI_SS_LEVEL_HIGH,
        bool &GPIO_QSPI_SS_EDGE_LOW, bool &GPIO_QSPI_SS_EDGE_HIGH,
        bool &GPIO_QSPI_SD0_LEVEL_LOW, bool &GPIO_QSPI_SD0_LEVEL_HIGH,
        bool &GPIO_QSPI_SD0_EDGE_LOW, bool &GPIO_QSPI_SD0_EDGE_HIGH,
        bool &GPIO_QSPI_SD1_LEVEL_LOW, bool &GPIO_QSPI_SD1_LEVEL_HIGH,
        bool &GPIO_QSPI_SD1_EDGE_LOW, bool &GPIO_QSPI_SD1_EDGE_HIGH,
        bool &GPIO_QSPI_SD2_LEVEL_LOW, bool &GPIO_QSPI_SD2_LEVEL_HIGH,
        bool &GPIO_QSPI_SD2_EDGE_LOW, bool &GPIO_QSPI_SD2_EDGE_HIGH,
        bool &GPIO_QSPI_SD3_LEVEL_LOW, bool &GPIO_QSPI_SD3_LEVEL_HIGH,
        bool &GPIO_QSPI_SD3_EDGE_LOW, bool &GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = PROC0_INTS;

        GPIO_QSPI_SCLK_LEVEL_LOW = curr & (1u << 0u);
        GPIO_QSPI_SCLK_LEVEL_HIGH = curr & (1u << 1u);
        GPIO_QSPI_SCLK_EDGE_LOW = curr & (1u << 2u);
        GPIO_QSPI_SCLK_EDGE_HIGH = curr & (1u << 3u);
        GPIO_QSPI_SS_LEVEL_LOW = curr & (1u << 4u);
        GPIO_QSPI_SS_LEVEL_HIGH = curr & (1u << 5u);
        GPIO_QSPI_SS_EDGE_LOW = curr & (1u << 6u);
        GPIO_QSPI_SS_EDGE_HIGH = curr & (1u << 7u);
        GPIO_QSPI_SD0_LEVEL_LOW = curr & (1u << 8u);
        GPIO_QSPI_SD0_LEVEL_HIGH = curr & (1u << 9u);
        GPIO_QSPI_SD0_EDGE_LOW = curr & (1u << 10u);
        GPIO_QSPI_SD0_EDGE_HIGH = curr & (1u << 11u);
        GPIO_QSPI_SD1_LEVEL_LOW = curr & (1u << 12u);
        GPIO_QSPI_SD1_LEVEL_HIGH = curr & (1u << 13u);
        GPIO_QSPI_SD1_EDGE_LOW = curr & (1u << 14u);
        GPIO_QSPI_SD1_EDGE_HIGH = curr & (1u << 15u);
        GPIO_QSPI_SD2_LEVEL_LOW = curr & (1u << 16u);
        GPIO_QSPI_SD2_LEVEL_HIGH = curr & (1u << 17u);
        GPIO_QSPI_SD2_EDGE_LOW = curr & (1u << 18u);
        GPIO_QSPI_SD2_EDGE_HIGH = curr & (1u << 19u);
        GPIO_QSPI_SD3_LEVEL_LOW = curr & (1u << 20u);
        GPIO_QSPI_SD3_LEVEL_HIGH = curr & (1u << 21u);
        GPIO_QSPI_SD3_EDGE_LOW = curr & (1u << 22u);
        GPIO_QSPI_SD3_EDGE_HIGH = curr & (1u << 23u);
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        return PROC1_INTE & (1u << 0u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        PROC1_INTE |= 1u << 0u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        PROC1_INTE &= ~(1u << 0u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        PROC1_INTE ^= 1u << 0u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        return PROC1_INTE & (1u << 1u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        PROC1_INTE |= 1u << 1u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        PROC1_INTE &= ~(1u << 1u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        PROC1_INTE ^= 1u << 1u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        return PROC1_INTE & (1u << 2u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        PROC1_INTE |= 1u << 2u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        PROC1_INTE &= ~(1u << 2u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        PROC1_INTE ^= 1u << 2u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        return PROC1_INTE & (1u << 3u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        PROC1_INTE |= 1u << 3u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        PROC1_INTE &= ~(1u << 3u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        PROC1_INTE ^= 1u << 3u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        return PROC1_INTE & (1u << 4u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        PROC1_INTE |= 1u << 4u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        PROC1_INTE &= ~(1u << 4u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        PROC1_INTE ^= 1u << 4u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        return PROC1_INTE & (1u << 5u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        PROC1_INTE |= 1u << 5u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        PROC1_INTE &= ~(1u << 5u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        PROC1_INTE ^= 1u << 5u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        return PROC1_INTE & (1u << 6u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        PROC1_INTE |= 1u << 6u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        PROC1_INTE &= ~(1u << 6u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        PROC1_INTE ^= 1u << 6u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        return PROC1_INTE & (1u << 7u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        PROC1_INTE |= 1u << 7u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        PROC1_INTE &= ~(1u << 7u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        PROC1_INTE ^= 1u << 7u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        return PROC1_INTE & (1u << 8u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        PROC1_INTE |= 1u << 8u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        PROC1_INTE &= ~(1u << 8u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        PROC1_INTE ^= 1u << 8u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        return PROC1_INTE & (1u << 9u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        PROC1_INTE |= 1u << 9u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        PROC1_INTE &= ~(1u << 9u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        PROC1_INTE ^= 1u << 9u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        return PROC1_INTE & (1u << 10u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        PROC1_INTE |= 1u << 10u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        PROC1_INTE &= ~(1u << 10u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        PROC1_INTE ^= 1u << 10u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        return PROC1_INTE & (1u << 11u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        PROC1_INTE |= 1u << 11u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        PROC1_INTE &= ~(1u << 11u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        PROC1_INTE ^= 1u << 11u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        return PROC1_INTE & (1u << 12u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        PROC1_INTE |= 1u << 12u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        PROC1_INTE &= ~(1u << 12u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        PROC1_INTE ^= 1u << 12u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        return PROC1_INTE & (1u << 13u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        PROC1_INTE |= 1u << 13u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        PROC1_INTE &= ~(1u << 13u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        PROC1_INTE ^= 1u << 13u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        return PROC1_INTE & (1u << 14u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        PROC1_INTE |= 1u << 14u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        PROC1_INTE &= ~(1u << 14u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        PROC1_INTE ^= 1u << 14u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        return PROC1_INTE & (1u << 15u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        PROC1_INTE |= 1u << 15u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        PROC1_INTE &= ~(1u << 15u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        PROC1_INTE ^= 1u << 15u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        return PROC1_INTE & (1u << 16u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        PROC1_INTE |= 1u << 16u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        PROC1_INTE &= ~(1u << 16u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        PROC1_INTE ^= 1u << 16u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        return PROC1_INTE & (1u << 17u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        PROC1_INTE |= 1u << 17u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        PROC1_INTE &= ~(1u << 17u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        PROC1_INTE ^= 1u << 17u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        return PROC1_INTE & (1u << 18u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        PROC1_INTE |= 1u << 18u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        PROC1_INTE &= ~(1u << 18u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        PROC1_INTE ^= 1u << 18u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        return PROC1_INTE & (1u << 19u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        PROC1_INTE |= 1u << 19u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        PROC1_INTE &= ~(1u << 19u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        PROC1_INTE ^= 1u << 19u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        return PROC1_INTE & (1u << 20u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        PROC1_INTE |= 1u << 20u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        PROC1_INTE &= ~(1u << 20u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        PROC1_INTE ^= 1u << 20u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        return PROC1_INTE & (1u << 21u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        PROC1_INTE |= 1u << 21u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        PROC1_INTE &= ~(1u << 21u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        PROC1_INTE ^= 1u << 21u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        return PROC1_INTE & (1u << 22u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        PROC1_INTE |= 1u << 22u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        PROC1_INTE &= ~(1u << 22u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        PROC1_INTE ^= 1u << 22u;
    }

    inline bool get_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        return PROC1_INTE & (1u << 23u);
    }

    inline void set_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        PROC1_INTE |= 1u << 23u;
    }

    inline void clear_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        PROC1_INTE &= ~(1u << 23u);
    }

    inline void toggle_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        PROC1_INTE ^= 1u << 23u;
    }

    inline void get_PROC1_INTE(
        bool &GPIO_QSPI_SCLK_LEVEL_LOW, bool &GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool &GPIO_QSPI_SCLK_EDGE_LOW, bool &GPIO_QSPI_SCLK_EDGE_HIGH,
        bool &GPIO_QSPI_SS_LEVEL_LOW, bool &GPIO_QSPI_SS_LEVEL_HIGH,
        bool &GPIO_QSPI_SS_EDGE_LOW, bool &GPIO_QSPI_SS_EDGE_HIGH,
        bool &GPIO_QSPI_SD0_LEVEL_LOW, bool &GPIO_QSPI_SD0_LEVEL_HIGH,
        bool &GPIO_QSPI_SD0_EDGE_LOW, bool &GPIO_QSPI_SD0_EDGE_HIGH,
        bool &GPIO_QSPI_SD1_LEVEL_LOW, bool &GPIO_QSPI_SD1_LEVEL_HIGH,
        bool &GPIO_QSPI_SD1_EDGE_LOW, bool &GPIO_QSPI_SD1_EDGE_HIGH,
        bool &GPIO_QSPI_SD2_LEVEL_LOW, bool &GPIO_QSPI_SD2_LEVEL_HIGH,
        bool &GPIO_QSPI_SD2_EDGE_LOW, bool &GPIO_QSPI_SD2_EDGE_HIGH,
        bool &GPIO_QSPI_SD3_LEVEL_LOW, bool &GPIO_QSPI_SD3_LEVEL_HIGH,
        bool &GPIO_QSPI_SD3_EDGE_LOW, bool &GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = PROC1_INTE;

        GPIO_QSPI_SCLK_LEVEL_LOW = curr & (1u << 0u);
        GPIO_QSPI_SCLK_LEVEL_HIGH = curr & (1u << 1u);
        GPIO_QSPI_SCLK_EDGE_LOW = curr & (1u << 2u);
        GPIO_QSPI_SCLK_EDGE_HIGH = curr & (1u << 3u);
        GPIO_QSPI_SS_LEVEL_LOW = curr & (1u << 4u);
        GPIO_QSPI_SS_LEVEL_HIGH = curr & (1u << 5u);
        GPIO_QSPI_SS_EDGE_LOW = curr & (1u << 6u);
        GPIO_QSPI_SS_EDGE_HIGH = curr & (1u << 7u);
        GPIO_QSPI_SD0_LEVEL_LOW = curr & (1u << 8u);
        GPIO_QSPI_SD0_LEVEL_HIGH = curr & (1u << 9u);
        GPIO_QSPI_SD0_EDGE_LOW = curr & (1u << 10u);
        GPIO_QSPI_SD0_EDGE_HIGH = curr & (1u << 11u);
        GPIO_QSPI_SD1_LEVEL_LOW = curr & (1u << 12u);
        GPIO_QSPI_SD1_LEVEL_HIGH = curr & (1u << 13u);
        GPIO_QSPI_SD1_EDGE_LOW = curr & (1u << 14u);
        GPIO_QSPI_SD1_EDGE_HIGH = curr & (1u << 15u);
        GPIO_QSPI_SD2_LEVEL_LOW = curr & (1u << 16u);
        GPIO_QSPI_SD2_LEVEL_HIGH = curr & (1u << 17u);
        GPIO_QSPI_SD2_EDGE_LOW = curr & (1u << 18u);
        GPIO_QSPI_SD2_EDGE_HIGH = curr & (1u << 19u);
        GPIO_QSPI_SD3_LEVEL_LOW = curr & (1u << 20u);
        GPIO_QSPI_SD3_LEVEL_HIGH = curr & (1u << 21u);
        GPIO_QSPI_SD3_EDGE_LOW = curr & (1u << 22u);
        GPIO_QSPI_SD3_EDGE_HIGH = curr & (1u << 23u);
    }

    inline void set_PROC1_INTE(
        bool GPIO_QSPI_SCLK_LEVEL_LOW, bool GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool GPIO_QSPI_SCLK_EDGE_LOW, bool GPIO_QSPI_SCLK_EDGE_HIGH,
        bool GPIO_QSPI_SS_LEVEL_LOW, bool GPIO_QSPI_SS_LEVEL_HIGH,
        bool GPIO_QSPI_SS_EDGE_LOW, bool GPIO_QSPI_SS_EDGE_HIGH,
        bool GPIO_QSPI_SD0_LEVEL_LOW, bool GPIO_QSPI_SD0_LEVEL_HIGH,
        bool GPIO_QSPI_SD0_EDGE_LOW, bool GPIO_QSPI_SD0_EDGE_HIGH,
        bool GPIO_QSPI_SD1_LEVEL_LOW, bool GPIO_QSPI_SD1_LEVEL_HIGH,
        bool GPIO_QSPI_SD1_EDGE_LOW, bool GPIO_QSPI_SD1_EDGE_HIGH,
        bool GPIO_QSPI_SD2_LEVEL_LOW, bool GPIO_QSPI_SD2_LEVEL_HIGH,
        bool GPIO_QSPI_SD2_EDGE_LOW, bool GPIO_QSPI_SD2_EDGE_HIGH,
        bool GPIO_QSPI_SD3_LEVEL_LOW, bool GPIO_QSPI_SD3_LEVEL_HIGH,
        bool GPIO_QSPI_SD3_EDGE_LOW, bool GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = PROC1_INTE;

        curr &= ~(0b1u << 0u);
        curr |= (GPIO_QSPI_SCLK_LEVEL_LOW & 0b1u) << 0u;
        curr &= ~(0b1u << 1u);
        curr |= (GPIO_QSPI_SCLK_LEVEL_HIGH & 0b1u) << 1u;
        curr &= ~(0b1u << 2u);
        curr |= (GPIO_QSPI_SCLK_EDGE_LOW & 0b1u) << 2u;
        curr &= ~(0b1u << 3u);
        curr |= (GPIO_QSPI_SCLK_EDGE_HIGH & 0b1u) << 3u;
        curr &= ~(0b1u << 4u);
        curr |= (GPIO_QSPI_SS_LEVEL_LOW & 0b1u) << 4u;
        curr &= ~(0b1u << 5u);
        curr |= (GPIO_QSPI_SS_LEVEL_HIGH & 0b1u) << 5u;
        curr &= ~(0b1u << 6u);
        curr |= (GPIO_QSPI_SS_EDGE_LOW & 0b1u) << 6u;
        curr &= ~(0b1u << 7u);
        curr |= (GPIO_QSPI_SS_EDGE_HIGH & 0b1u) << 7u;
        curr &= ~(0b1u << 8u);
        curr |= (GPIO_QSPI_SD0_LEVEL_LOW & 0b1u) << 8u;
        curr &= ~(0b1u << 9u);
        curr |= (GPIO_QSPI_SD0_LEVEL_HIGH & 0b1u) << 9u;
        curr &= ~(0b1u << 10u);
        curr |= (GPIO_QSPI_SD0_EDGE_LOW & 0b1u) << 10u;
        curr &= ~(0b1u << 11u);
        curr |= (GPIO_QSPI_SD0_EDGE_HIGH & 0b1u) << 11u;
        curr &= ~(0b1u << 12u);
        curr |= (GPIO_QSPI_SD1_LEVEL_LOW & 0b1u) << 12u;
        curr &= ~(0b1u << 13u);
        curr |= (GPIO_QSPI_SD1_LEVEL_HIGH & 0b1u) << 13u;
        curr &= ~(0b1u << 14u);
        curr |= (GPIO_QSPI_SD1_EDGE_LOW & 0b1u) << 14u;
        curr &= ~(0b1u << 15u);
        curr |= (GPIO_QSPI_SD1_EDGE_HIGH & 0b1u) << 15u;
        curr &= ~(0b1u << 16u);
        curr |= (GPIO_QSPI_SD2_LEVEL_LOW & 0b1u) << 16u;
        curr &= ~(0b1u << 17u);
        curr |= (GPIO_QSPI_SD2_LEVEL_HIGH & 0b1u) << 17u;
        curr &= ~(0b1u << 18u);
        curr |= (GPIO_QSPI_SD2_EDGE_LOW & 0b1u) << 18u;
        curr &= ~(0b1u << 19u);
        curr |= (GPIO_QSPI_SD2_EDGE_HIGH & 0b1u) << 19u;
        curr &= ~(0b1u << 20u);
        curr |= (GPIO_QSPI_SD3_LEVEL_LOW & 0b1u) << 20u;
        curr &= ~(0b1u << 21u);
        curr |= (GPIO_QSPI_SD3_LEVEL_HIGH & 0b1u) << 21u;
        curr &= ~(0b1u << 22u);
        curr |= (GPIO_QSPI_SD3_EDGE_LOW & 0b1u) << 22u;
        curr &= ~(0b1u << 23u);
        curr |= (GPIO_QSPI_SD3_EDGE_HIGH & 0b1u) << 23u;

        PROC1_INTE = curr;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        return PROC1_INTF & (1u << 0u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        PROC1_INTF |= 1u << 0u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        PROC1_INTF &= ~(1u << 0u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        PROC1_INTF ^= 1u << 0u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        return PROC1_INTF & (1u << 1u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        PROC1_INTF |= 1u << 1u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        PROC1_INTF &= ~(1u << 1u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        PROC1_INTF ^= 1u << 1u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        return PROC1_INTF & (1u << 2u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        PROC1_INTF |= 1u << 2u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        PROC1_INTF &= ~(1u << 2u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        PROC1_INTF ^= 1u << 2u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        return PROC1_INTF & (1u << 3u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        PROC1_INTF |= 1u << 3u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        PROC1_INTF &= ~(1u << 3u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        PROC1_INTF ^= 1u << 3u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        return PROC1_INTF & (1u << 4u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        PROC1_INTF |= 1u << 4u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        PROC1_INTF &= ~(1u << 4u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        PROC1_INTF ^= 1u << 4u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        return PROC1_INTF & (1u << 5u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        PROC1_INTF |= 1u << 5u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        PROC1_INTF &= ~(1u << 5u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        PROC1_INTF ^= 1u << 5u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        return PROC1_INTF & (1u << 6u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        PROC1_INTF |= 1u << 6u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        PROC1_INTF &= ~(1u << 6u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        PROC1_INTF ^= 1u << 6u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        return PROC1_INTF & (1u << 7u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        PROC1_INTF |= 1u << 7u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        PROC1_INTF &= ~(1u << 7u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        PROC1_INTF ^= 1u << 7u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        return PROC1_INTF & (1u << 8u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        PROC1_INTF |= 1u << 8u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        PROC1_INTF &= ~(1u << 8u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        PROC1_INTF ^= 1u << 8u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        return PROC1_INTF & (1u << 9u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        PROC1_INTF |= 1u << 9u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        PROC1_INTF &= ~(1u << 9u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        PROC1_INTF ^= 1u << 9u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        return PROC1_INTF & (1u << 10u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        PROC1_INTF |= 1u << 10u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        PROC1_INTF &= ~(1u << 10u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        PROC1_INTF ^= 1u << 10u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        return PROC1_INTF & (1u << 11u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        PROC1_INTF |= 1u << 11u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        PROC1_INTF &= ~(1u << 11u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        PROC1_INTF ^= 1u << 11u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        return PROC1_INTF & (1u << 12u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        PROC1_INTF |= 1u << 12u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        PROC1_INTF &= ~(1u << 12u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        PROC1_INTF ^= 1u << 12u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        return PROC1_INTF & (1u << 13u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        PROC1_INTF |= 1u << 13u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        PROC1_INTF &= ~(1u << 13u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        PROC1_INTF ^= 1u << 13u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        return PROC1_INTF & (1u << 14u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        PROC1_INTF |= 1u << 14u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        PROC1_INTF &= ~(1u << 14u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        PROC1_INTF ^= 1u << 14u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        return PROC1_INTF & (1u << 15u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        PROC1_INTF |= 1u << 15u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        PROC1_INTF &= ~(1u << 15u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        PROC1_INTF ^= 1u << 15u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        return PROC1_INTF & (1u << 16u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        PROC1_INTF |= 1u << 16u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        PROC1_INTF &= ~(1u << 16u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        PROC1_INTF ^= 1u << 16u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        return PROC1_INTF & (1u << 17u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        PROC1_INTF |= 1u << 17u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        PROC1_INTF &= ~(1u << 17u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        PROC1_INTF ^= 1u << 17u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        return PROC1_INTF & (1u << 18u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        PROC1_INTF |= 1u << 18u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        PROC1_INTF &= ~(1u << 18u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        PROC1_INTF ^= 1u << 18u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        return PROC1_INTF & (1u << 19u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        PROC1_INTF |= 1u << 19u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        PROC1_INTF &= ~(1u << 19u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        PROC1_INTF ^= 1u << 19u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        return PROC1_INTF & (1u << 20u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        PROC1_INTF |= 1u << 20u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        PROC1_INTF &= ~(1u << 20u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        PROC1_INTF ^= 1u << 20u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        return PROC1_INTF & (1u << 21u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        PROC1_INTF |= 1u << 21u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        PROC1_INTF &= ~(1u << 21u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        PROC1_INTF ^= 1u << 21u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        return PROC1_INTF & (1u << 22u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        PROC1_INTF |= 1u << 22u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        PROC1_INTF &= ~(1u << 22u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        PROC1_INTF ^= 1u << 22u;
    }

    inline bool get_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        return PROC1_INTF & (1u << 23u);
    }

    inline void set_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        PROC1_INTF |= 1u << 23u;
    }

    inline void clear_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        PROC1_INTF &= ~(1u << 23u);
    }

    inline void toggle_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        PROC1_INTF ^= 1u << 23u;
    }

    inline void get_PROC1_INTF(
        bool &GPIO_QSPI_SCLK_LEVEL_LOW, bool &GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool &GPIO_QSPI_SCLK_EDGE_LOW, bool &GPIO_QSPI_SCLK_EDGE_HIGH,
        bool &GPIO_QSPI_SS_LEVEL_LOW, bool &GPIO_QSPI_SS_LEVEL_HIGH,
        bool &GPIO_QSPI_SS_EDGE_LOW, bool &GPIO_QSPI_SS_EDGE_HIGH,
        bool &GPIO_QSPI_SD0_LEVEL_LOW, bool &GPIO_QSPI_SD0_LEVEL_HIGH,
        bool &GPIO_QSPI_SD0_EDGE_LOW, bool &GPIO_QSPI_SD0_EDGE_HIGH,
        bool &GPIO_QSPI_SD1_LEVEL_LOW, bool &GPIO_QSPI_SD1_LEVEL_HIGH,
        bool &GPIO_QSPI_SD1_EDGE_LOW, bool &GPIO_QSPI_SD1_EDGE_HIGH,
        bool &GPIO_QSPI_SD2_LEVEL_LOW, bool &GPIO_QSPI_SD2_LEVEL_HIGH,
        bool &GPIO_QSPI_SD2_EDGE_LOW, bool &GPIO_QSPI_SD2_EDGE_HIGH,
        bool &GPIO_QSPI_SD3_LEVEL_LOW, bool &GPIO_QSPI_SD3_LEVEL_HIGH,
        bool &GPIO_QSPI_SD3_EDGE_LOW, bool &GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = PROC1_INTF;

        GPIO_QSPI_SCLK_LEVEL_LOW = curr & (1u << 0u);
        GPIO_QSPI_SCLK_LEVEL_HIGH = curr & (1u << 1u);
        GPIO_QSPI_SCLK_EDGE_LOW = curr & (1u << 2u);
        GPIO_QSPI_SCLK_EDGE_HIGH = curr & (1u << 3u);
        GPIO_QSPI_SS_LEVEL_LOW = curr & (1u << 4u);
        GPIO_QSPI_SS_LEVEL_HIGH = curr & (1u << 5u);
        GPIO_QSPI_SS_EDGE_LOW = curr & (1u << 6u);
        GPIO_QSPI_SS_EDGE_HIGH = curr & (1u << 7u);
        GPIO_QSPI_SD0_LEVEL_LOW = curr & (1u << 8u);
        GPIO_QSPI_SD0_LEVEL_HIGH = curr & (1u << 9u);
        GPIO_QSPI_SD0_EDGE_LOW = curr & (1u << 10u);
        GPIO_QSPI_SD0_EDGE_HIGH = curr & (1u << 11u);
        GPIO_QSPI_SD1_LEVEL_LOW = curr & (1u << 12u);
        GPIO_QSPI_SD1_LEVEL_HIGH = curr & (1u << 13u);
        GPIO_QSPI_SD1_EDGE_LOW = curr & (1u << 14u);
        GPIO_QSPI_SD1_EDGE_HIGH = curr & (1u << 15u);
        GPIO_QSPI_SD2_LEVEL_LOW = curr & (1u << 16u);
        GPIO_QSPI_SD2_LEVEL_HIGH = curr & (1u << 17u);
        GPIO_QSPI_SD2_EDGE_LOW = curr & (1u << 18u);
        GPIO_QSPI_SD2_EDGE_HIGH = curr & (1u << 19u);
        GPIO_QSPI_SD3_LEVEL_LOW = curr & (1u << 20u);
        GPIO_QSPI_SD3_LEVEL_HIGH = curr & (1u << 21u);
        GPIO_QSPI_SD3_EDGE_LOW = curr & (1u << 22u);
        GPIO_QSPI_SD3_EDGE_HIGH = curr & (1u << 23u);
    }

    inline void set_PROC1_INTF(
        bool GPIO_QSPI_SCLK_LEVEL_LOW, bool GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool GPIO_QSPI_SCLK_EDGE_LOW, bool GPIO_QSPI_SCLK_EDGE_HIGH,
        bool GPIO_QSPI_SS_LEVEL_LOW, bool GPIO_QSPI_SS_LEVEL_HIGH,
        bool GPIO_QSPI_SS_EDGE_LOW, bool GPIO_QSPI_SS_EDGE_HIGH,
        bool GPIO_QSPI_SD0_LEVEL_LOW, bool GPIO_QSPI_SD0_LEVEL_HIGH,
        bool GPIO_QSPI_SD0_EDGE_LOW, bool GPIO_QSPI_SD0_EDGE_HIGH,
        bool GPIO_QSPI_SD1_LEVEL_LOW, bool GPIO_QSPI_SD1_LEVEL_HIGH,
        bool GPIO_QSPI_SD1_EDGE_LOW, bool GPIO_QSPI_SD1_EDGE_HIGH,
        bool GPIO_QSPI_SD2_LEVEL_LOW, bool GPIO_QSPI_SD2_LEVEL_HIGH,
        bool GPIO_QSPI_SD2_EDGE_LOW, bool GPIO_QSPI_SD2_EDGE_HIGH,
        bool GPIO_QSPI_SD3_LEVEL_LOW, bool GPIO_QSPI_SD3_LEVEL_HIGH,
        bool GPIO_QSPI_SD3_EDGE_LOW, bool GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = PROC1_INTF;

        curr &= ~(0b1u << 0u);
        curr |= (GPIO_QSPI_SCLK_LEVEL_LOW & 0b1u) << 0u;
        curr &= ~(0b1u << 1u);
        curr |= (GPIO_QSPI_SCLK_LEVEL_HIGH & 0b1u) << 1u;
        curr &= ~(0b1u << 2u);
        curr |= (GPIO_QSPI_SCLK_EDGE_LOW & 0b1u) << 2u;
        curr &= ~(0b1u << 3u);
        curr |= (GPIO_QSPI_SCLK_EDGE_HIGH & 0b1u) << 3u;
        curr &= ~(0b1u << 4u);
        curr |= (GPIO_QSPI_SS_LEVEL_LOW & 0b1u) << 4u;
        curr &= ~(0b1u << 5u);
        curr |= (GPIO_QSPI_SS_LEVEL_HIGH & 0b1u) << 5u;
        curr &= ~(0b1u << 6u);
        curr |= (GPIO_QSPI_SS_EDGE_LOW & 0b1u) << 6u;
        curr &= ~(0b1u << 7u);
        curr |= (GPIO_QSPI_SS_EDGE_HIGH & 0b1u) << 7u;
        curr &= ~(0b1u << 8u);
        curr |= (GPIO_QSPI_SD0_LEVEL_LOW & 0b1u) << 8u;
        curr &= ~(0b1u << 9u);
        curr |= (GPIO_QSPI_SD0_LEVEL_HIGH & 0b1u) << 9u;
        curr &= ~(0b1u << 10u);
        curr |= (GPIO_QSPI_SD0_EDGE_LOW & 0b1u) << 10u;
        curr &= ~(0b1u << 11u);
        curr |= (GPIO_QSPI_SD0_EDGE_HIGH & 0b1u) << 11u;
        curr &= ~(0b1u << 12u);
        curr |= (GPIO_QSPI_SD1_LEVEL_LOW & 0b1u) << 12u;
        curr &= ~(0b1u << 13u);
        curr |= (GPIO_QSPI_SD1_LEVEL_HIGH & 0b1u) << 13u;
        curr &= ~(0b1u << 14u);
        curr |= (GPIO_QSPI_SD1_EDGE_LOW & 0b1u) << 14u;
        curr &= ~(0b1u << 15u);
        curr |= (GPIO_QSPI_SD1_EDGE_HIGH & 0b1u) << 15u;
        curr &= ~(0b1u << 16u);
        curr |= (GPIO_QSPI_SD2_LEVEL_LOW & 0b1u) << 16u;
        curr &= ~(0b1u << 17u);
        curr |= (GPIO_QSPI_SD2_LEVEL_HIGH & 0b1u) << 17u;
        curr &= ~(0b1u << 18u);
        curr |= (GPIO_QSPI_SD2_EDGE_LOW & 0b1u) << 18u;
        curr &= ~(0b1u << 19u);
        curr |= (GPIO_QSPI_SD2_EDGE_HIGH & 0b1u) << 19u;
        curr &= ~(0b1u << 20u);
        curr |= (GPIO_QSPI_SD3_LEVEL_LOW & 0b1u) << 20u;
        curr &= ~(0b1u << 21u);
        curr |= (GPIO_QSPI_SD3_LEVEL_HIGH & 0b1u) << 21u;
        curr &= ~(0b1u << 22u);
        curr |= (GPIO_QSPI_SD3_EDGE_LOW & 0b1u) << 22u;
        curr &= ~(0b1u << 23u);
        curr |= (GPIO_QSPI_SD3_EDGE_HIGH & 0b1u) << 23u;

        PROC1_INTF = curr;
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        return PROC1_INTS & (1u << 0u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        return PROC1_INTS & (1u << 1u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        return PROC1_INTS & (1u << 2u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        return PROC1_INTS & (1u << 3u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        return PROC1_INTS & (1u << 4u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        return PROC1_INTS & (1u << 5u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        return PROC1_INTS & (1u << 6u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        return PROC1_INTS & (1u << 7u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        return PROC1_INTS & (1u << 8u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        return PROC1_INTS & (1u << 9u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        return PROC1_INTS & (1u << 10u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        return PROC1_INTS & (1u << 11u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        return PROC1_INTS & (1u << 12u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        return PROC1_INTS & (1u << 13u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        return PROC1_INTS & (1u << 14u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        return PROC1_INTS & (1u << 15u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        return PROC1_INTS & (1u << 16u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        return PROC1_INTS & (1u << 17u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        return PROC1_INTS & (1u << 18u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        return PROC1_INTS & (1u << 19u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        return PROC1_INTS & (1u << 20u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        return PROC1_INTS & (1u << 21u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        return PROC1_INTS & (1u << 22u);
    }

    inline bool get_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        return PROC1_INTS & (1u << 23u);
    }

    inline void get_PROC1_INTS(
        bool &GPIO_QSPI_SCLK_LEVEL_LOW, bool &GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool &GPIO_QSPI_SCLK_EDGE_LOW, bool &GPIO_QSPI_SCLK_EDGE_HIGH,
        bool &GPIO_QSPI_SS_LEVEL_LOW, bool &GPIO_QSPI_SS_LEVEL_HIGH,
        bool &GPIO_QSPI_SS_EDGE_LOW, bool &GPIO_QSPI_SS_EDGE_HIGH,
        bool &GPIO_QSPI_SD0_LEVEL_LOW, bool &GPIO_QSPI_SD0_LEVEL_HIGH,
        bool &GPIO_QSPI_SD0_EDGE_LOW, bool &GPIO_QSPI_SD0_EDGE_HIGH,
        bool &GPIO_QSPI_SD1_LEVEL_LOW, bool &GPIO_QSPI_SD1_LEVEL_HIGH,
        bool &GPIO_QSPI_SD1_EDGE_LOW, bool &GPIO_QSPI_SD1_EDGE_HIGH,
        bool &GPIO_QSPI_SD2_LEVEL_LOW, bool &GPIO_QSPI_SD2_LEVEL_HIGH,
        bool &GPIO_QSPI_SD2_EDGE_LOW, bool &GPIO_QSPI_SD2_EDGE_HIGH,
        bool &GPIO_QSPI_SD3_LEVEL_LOW, bool &GPIO_QSPI_SD3_LEVEL_HIGH,
        bool &GPIO_QSPI_SD3_EDGE_LOW, bool &GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = PROC1_INTS;

        GPIO_QSPI_SCLK_LEVEL_LOW = curr & (1u << 0u);
        GPIO_QSPI_SCLK_LEVEL_HIGH = curr & (1u << 1u);
        GPIO_QSPI_SCLK_EDGE_LOW = curr & (1u << 2u);
        GPIO_QSPI_SCLK_EDGE_HIGH = curr & (1u << 3u);
        GPIO_QSPI_SS_LEVEL_LOW = curr & (1u << 4u);
        GPIO_QSPI_SS_LEVEL_HIGH = curr & (1u << 5u);
        GPIO_QSPI_SS_EDGE_LOW = curr & (1u << 6u);
        GPIO_QSPI_SS_EDGE_HIGH = curr & (1u << 7u);
        GPIO_QSPI_SD0_LEVEL_LOW = curr & (1u << 8u);
        GPIO_QSPI_SD0_LEVEL_HIGH = curr & (1u << 9u);
        GPIO_QSPI_SD0_EDGE_LOW = curr & (1u << 10u);
        GPIO_QSPI_SD0_EDGE_HIGH = curr & (1u << 11u);
        GPIO_QSPI_SD1_LEVEL_LOW = curr & (1u << 12u);
        GPIO_QSPI_SD1_LEVEL_HIGH = curr & (1u << 13u);
        GPIO_QSPI_SD1_EDGE_LOW = curr & (1u << 14u);
        GPIO_QSPI_SD1_EDGE_HIGH = curr & (1u << 15u);
        GPIO_QSPI_SD2_LEVEL_LOW = curr & (1u << 16u);
        GPIO_QSPI_SD2_LEVEL_HIGH = curr & (1u << 17u);
        GPIO_QSPI_SD2_EDGE_LOW = curr & (1u << 18u);
        GPIO_QSPI_SD2_EDGE_HIGH = curr & (1u << 19u);
        GPIO_QSPI_SD3_LEVEL_LOW = curr & (1u << 20u);
        GPIO_QSPI_SD3_LEVEL_HIGH = curr & (1u << 21u);
        GPIO_QSPI_SD3_EDGE_LOW = curr & (1u << 22u);
        GPIO_QSPI_SD3_EDGE_HIGH = curr & (1u << 23u);
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 0u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 0u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 0u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 0u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 1u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 1u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 1u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 1u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 2u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 2u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 2u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 2u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 3u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 3u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 3u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 3u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 4u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 4u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 4u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 4u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 5u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 5u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 5u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 5u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 6u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 6u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 6u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 6u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 7u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 7u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 7u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 7u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 8u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 8u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 8u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 8u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 9u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 9u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 9u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 9u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 10u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 10u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 10u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 10u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 11u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 11u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 11u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 11u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 12u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 12u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 12u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 12u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 13u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 13u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 13u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 13u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 14u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 14u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 14u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 14u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 15u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 15u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 15u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 15u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 16u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 16u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 16u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 16u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 17u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 17u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 17u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 17u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 18u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 18u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 18u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 18u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 19u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 19u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 19u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 19u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 20u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 20u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 20u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 20u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 21u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 21u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 21u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 21u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 22u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 22u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 22u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 22u;
    }

    inline bool get_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTE & (1u << 23u);
    }

    inline void set_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE |= 1u << 23u;
    }

    inline void clear_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE &= ~(1u << 23u);
    }

    inline void toggle_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTE ^= 1u << 23u;
    }

    inline void get_DORMANT_WAKE_INTE(
        bool &GPIO_QSPI_SCLK_LEVEL_LOW, bool &GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool &GPIO_QSPI_SCLK_EDGE_LOW, bool &GPIO_QSPI_SCLK_EDGE_HIGH,
        bool &GPIO_QSPI_SS_LEVEL_LOW, bool &GPIO_QSPI_SS_LEVEL_HIGH,
        bool &GPIO_QSPI_SS_EDGE_LOW, bool &GPIO_QSPI_SS_EDGE_HIGH,
        bool &GPIO_QSPI_SD0_LEVEL_LOW, bool &GPIO_QSPI_SD0_LEVEL_HIGH,
        bool &GPIO_QSPI_SD0_EDGE_LOW, bool &GPIO_QSPI_SD0_EDGE_HIGH,
        bool &GPIO_QSPI_SD1_LEVEL_LOW, bool &GPIO_QSPI_SD1_LEVEL_HIGH,
        bool &GPIO_QSPI_SD1_EDGE_LOW, bool &GPIO_QSPI_SD1_EDGE_HIGH,
        bool &GPIO_QSPI_SD2_LEVEL_LOW, bool &GPIO_QSPI_SD2_LEVEL_HIGH,
        bool &GPIO_QSPI_SD2_EDGE_LOW, bool &GPIO_QSPI_SD2_EDGE_HIGH,
        bool &GPIO_QSPI_SD3_LEVEL_LOW, bool &GPIO_QSPI_SD3_LEVEL_HIGH,
        bool &GPIO_QSPI_SD3_EDGE_LOW, bool &GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = DORMANT_WAKE_INTE;

        GPIO_QSPI_SCLK_LEVEL_LOW = curr & (1u << 0u);
        GPIO_QSPI_SCLK_LEVEL_HIGH = curr & (1u << 1u);
        GPIO_QSPI_SCLK_EDGE_LOW = curr & (1u << 2u);
        GPIO_QSPI_SCLK_EDGE_HIGH = curr & (1u << 3u);
        GPIO_QSPI_SS_LEVEL_LOW = curr & (1u << 4u);
        GPIO_QSPI_SS_LEVEL_HIGH = curr & (1u << 5u);
        GPIO_QSPI_SS_EDGE_LOW = curr & (1u << 6u);
        GPIO_QSPI_SS_EDGE_HIGH = curr & (1u << 7u);
        GPIO_QSPI_SD0_LEVEL_LOW = curr & (1u << 8u);
        GPIO_QSPI_SD0_LEVEL_HIGH = curr & (1u << 9u);
        GPIO_QSPI_SD0_EDGE_LOW = curr & (1u << 10u);
        GPIO_QSPI_SD0_EDGE_HIGH = curr & (1u << 11u);
        GPIO_QSPI_SD1_LEVEL_LOW = curr & (1u << 12u);
        GPIO_QSPI_SD1_LEVEL_HIGH = curr & (1u << 13u);
        GPIO_QSPI_SD1_EDGE_LOW = curr & (1u << 14u);
        GPIO_QSPI_SD1_EDGE_HIGH = curr & (1u << 15u);
        GPIO_QSPI_SD2_LEVEL_LOW = curr & (1u << 16u);
        GPIO_QSPI_SD2_LEVEL_HIGH = curr & (1u << 17u);
        GPIO_QSPI_SD2_EDGE_LOW = curr & (1u << 18u);
        GPIO_QSPI_SD2_EDGE_HIGH = curr & (1u << 19u);
        GPIO_QSPI_SD3_LEVEL_LOW = curr & (1u << 20u);
        GPIO_QSPI_SD3_LEVEL_HIGH = curr & (1u << 21u);
        GPIO_QSPI_SD3_EDGE_LOW = curr & (1u << 22u);
        GPIO_QSPI_SD3_EDGE_HIGH = curr & (1u << 23u);
    }

    inline void set_DORMANT_WAKE_INTE(
        bool GPIO_QSPI_SCLK_LEVEL_LOW, bool GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool GPIO_QSPI_SCLK_EDGE_LOW, bool GPIO_QSPI_SCLK_EDGE_HIGH,
        bool GPIO_QSPI_SS_LEVEL_LOW, bool GPIO_QSPI_SS_LEVEL_HIGH,
        bool GPIO_QSPI_SS_EDGE_LOW, bool GPIO_QSPI_SS_EDGE_HIGH,
        bool GPIO_QSPI_SD0_LEVEL_LOW, bool GPIO_QSPI_SD0_LEVEL_HIGH,
        bool GPIO_QSPI_SD0_EDGE_LOW, bool GPIO_QSPI_SD0_EDGE_HIGH,
        bool GPIO_QSPI_SD1_LEVEL_LOW, bool GPIO_QSPI_SD1_LEVEL_HIGH,
        bool GPIO_QSPI_SD1_EDGE_LOW, bool GPIO_QSPI_SD1_EDGE_HIGH,
        bool GPIO_QSPI_SD2_LEVEL_LOW, bool GPIO_QSPI_SD2_LEVEL_HIGH,
        bool GPIO_QSPI_SD2_EDGE_LOW, bool GPIO_QSPI_SD2_EDGE_HIGH,
        bool GPIO_QSPI_SD3_LEVEL_LOW, bool GPIO_QSPI_SD3_LEVEL_HIGH,
        bool GPIO_QSPI_SD3_EDGE_LOW, bool GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = DORMANT_WAKE_INTE;

        curr &= ~(0b1u << 0u);
        curr |= (GPIO_QSPI_SCLK_LEVEL_LOW & 0b1u) << 0u;
        curr &= ~(0b1u << 1u);
        curr |= (GPIO_QSPI_SCLK_LEVEL_HIGH & 0b1u) << 1u;
        curr &= ~(0b1u << 2u);
        curr |= (GPIO_QSPI_SCLK_EDGE_LOW & 0b1u) << 2u;
        curr &= ~(0b1u << 3u);
        curr |= (GPIO_QSPI_SCLK_EDGE_HIGH & 0b1u) << 3u;
        curr &= ~(0b1u << 4u);
        curr |= (GPIO_QSPI_SS_LEVEL_LOW & 0b1u) << 4u;
        curr &= ~(0b1u << 5u);
        curr |= (GPIO_QSPI_SS_LEVEL_HIGH & 0b1u) << 5u;
        curr &= ~(0b1u << 6u);
        curr |= (GPIO_QSPI_SS_EDGE_LOW & 0b1u) << 6u;
        curr &= ~(0b1u << 7u);
        curr |= (GPIO_QSPI_SS_EDGE_HIGH & 0b1u) << 7u;
        curr &= ~(0b1u << 8u);
        curr |= (GPIO_QSPI_SD0_LEVEL_LOW & 0b1u) << 8u;
        curr &= ~(0b1u << 9u);
        curr |= (GPIO_QSPI_SD0_LEVEL_HIGH & 0b1u) << 9u;
        curr &= ~(0b1u << 10u);
        curr |= (GPIO_QSPI_SD0_EDGE_LOW & 0b1u) << 10u;
        curr &= ~(0b1u << 11u);
        curr |= (GPIO_QSPI_SD0_EDGE_HIGH & 0b1u) << 11u;
        curr &= ~(0b1u << 12u);
        curr |= (GPIO_QSPI_SD1_LEVEL_LOW & 0b1u) << 12u;
        curr &= ~(0b1u << 13u);
        curr |= (GPIO_QSPI_SD1_LEVEL_HIGH & 0b1u) << 13u;
        curr &= ~(0b1u << 14u);
        curr |= (GPIO_QSPI_SD1_EDGE_LOW & 0b1u) << 14u;
        curr &= ~(0b1u << 15u);
        curr |= (GPIO_QSPI_SD1_EDGE_HIGH & 0b1u) << 15u;
        curr &= ~(0b1u << 16u);
        curr |= (GPIO_QSPI_SD2_LEVEL_LOW & 0b1u) << 16u;
        curr &= ~(0b1u << 17u);
        curr |= (GPIO_QSPI_SD2_LEVEL_HIGH & 0b1u) << 17u;
        curr &= ~(0b1u << 18u);
        curr |= (GPIO_QSPI_SD2_EDGE_LOW & 0b1u) << 18u;
        curr &= ~(0b1u << 19u);
        curr |= (GPIO_QSPI_SD2_EDGE_HIGH & 0b1u) << 19u;
        curr &= ~(0b1u << 20u);
        curr |= (GPIO_QSPI_SD3_LEVEL_LOW & 0b1u) << 20u;
        curr &= ~(0b1u << 21u);
        curr |= (GPIO_QSPI_SD3_LEVEL_HIGH & 0b1u) << 21u;
        curr &= ~(0b1u << 22u);
        curr |= (GPIO_QSPI_SD3_EDGE_LOW & 0b1u) << 22u;
        curr &= ~(0b1u << 23u);
        curr |= (GPIO_QSPI_SD3_EDGE_HIGH & 0b1u) << 23u;

        DORMANT_WAKE_INTE = curr;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 0u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 0u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 0u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 0u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 1u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 1u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 1u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 1u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 2u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 2u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 2u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 2u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 3u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 3u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 3u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 3u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 4u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 4u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 4u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 4u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 5u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 5u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 5u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 5u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 6u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 6u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 6u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 6u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 7u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 7u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 7u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 7u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 8u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 8u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 8u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 8u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 9u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 9u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 9u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 9u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 10u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 10u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 10u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 10u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 11u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 11u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 11u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 11u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 12u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 12u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 12u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 12u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 13u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 13u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 13u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 13u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 14u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 14u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 14u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 14u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 15u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 15u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 15u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 15u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 16u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 16u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 16u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 16u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 17u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 17u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 17u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 17u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 18u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 18u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 18u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 18u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 19u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 19u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 19u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 19u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 20u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 20u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 20u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 20u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 21u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 21u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 21u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 21u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 22u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 22u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 22u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 22u;
    }

    inline bool get_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTF & (1u << 23u);
    }

    inline void set_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF |= 1u << 23u;
    }

    inline void clear_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF &= ~(1u << 23u);
    }

    inline void toggle_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        DORMANT_WAKE_INTF ^= 1u << 23u;
    }

    inline void get_DORMANT_WAKE_INTF(
        bool &GPIO_QSPI_SCLK_LEVEL_LOW, bool &GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool &GPIO_QSPI_SCLK_EDGE_LOW, bool &GPIO_QSPI_SCLK_EDGE_HIGH,
        bool &GPIO_QSPI_SS_LEVEL_LOW, bool &GPIO_QSPI_SS_LEVEL_HIGH,
        bool &GPIO_QSPI_SS_EDGE_LOW, bool &GPIO_QSPI_SS_EDGE_HIGH,
        bool &GPIO_QSPI_SD0_LEVEL_LOW, bool &GPIO_QSPI_SD0_LEVEL_HIGH,
        bool &GPIO_QSPI_SD0_EDGE_LOW, bool &GPIO_QSPI_SD0_EDGE_HIGH,
        bool &GPIO_QSPI_SD1_LEVEL_LOW, bool &GPIO_QSPI_SD1_LEVEL_HIGH,
        bool &GPIO_QSPI_SD1_EDGE_LOW, bool &GPIO_QSPI_SD1_EDGE_HIGH,
        bool &GPIO_QSPI_SD2_LEVEL_LOW, bool &GPIO_QSPI_SD2_LEVEL_HIGH,
        bool &GPIO_QSPI_SD2_EDGE_LOW, bool &GPIO_QSPI_SD2_EDGE_HIGH,
        bool &GPIO_QSPI_SD3_LEVEL_LOW, bool &GPIO_QSPI_SD3_LEVEL_HIGH,
        bool &GPIO_QSPI_SD3_EDGE_LOW, bool &GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = DORMANT_WAKE_INTF;

        GPIO_QSPI_SCLK_LEVEL_LOW = curr & (1u << 0u);
        GPIO_QSPI_SCLK_LEVEL_HIGH = curr & (1u << 1u);
        GPIO_QSPI_SCLK_EDGE_LOW = curr & (1u << 2u);
        GPIO_QSPI_SCLK_EDGE_HIGH = curr & (1u << 3u);
        GPIO_QSPI_SS_LEVEL_LOW = curr & (1u << 4u);
        GPIO_QSPI_SS_LEVEL_HIGH = curr & (1u << 5u);
        GPIO_QSPI_SS_EDGE_LOW = curr & (1u << 6u);
        GPIO_QSPI_SS_EDGE_HIGH = curr & (1u << 7u);
        GPIO_QSPI_SD0_LEVEL_LOW = curr & (1u << 8u);
        GPIO_QSPI_SD0_LEVEL_HIGH = curr & (1u << 9u);
        GPIO_QSPI_SD0_EDGE_LOW = curr & (1u << 10u);
        GPIO_QSPI_SD0_EDGE_HIGH = curr & (1u << 11u);
        GPIO_QSPI_SD1_LEVEL_LOW = curr & (1u << 12u);
        GPIO_QSPI_SD1_LEVEL_HIGH = curr & (1u << 13u);
        GPIO_QSPI_SD1_EDGE_LOW = curr & (1u << 14u);
        GPIO_QSPI_SD1_EDGE_HIGH = curr & (1u << 15u);
        GPIO_QSPI_SD2_LEVEL_LOW = curr & (1u << 16u);
        GPIO_QSPI_SD2_LEVEL_HIGH = curr & (1u << 17u);
        GPIO_QSPI_SD2_EDGE_LOW = curr & (1u << 18u);
        GPIO_QSPI_SD2_EDGE_HIGH = curr & (1u << 19u);
        GPIO_QSPI_SD3_LEVEL_LOW = curr & (1u << 20u);
        GPIO_QSPI_SD3_LEVEL_HIGH = curr & (1u << 21u);
        GPIO_QSPI_SD3_EDGE_LOW = curr & (1u << 22u);
        GPIO_QSPI_SD3_EDGE_HIGH = curr & (1u << 23u);
    }

    inline void set_DORMANT_WAKE_INTF(
        bool GPIO_QSPI_SCLK_LEVEL_LOW, bool GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool GPIO_QSPI_SCLK_EDGE_LOW, bool GPIO_QSPI_SCLK_EDGE_HIGH,
        bool GPIO_QSPI_SS_LEVEL_LOW, bool GPIO_QSPI_SS_LEVEL_HIGH,
        bool GPIO_QSPI_SS_EDGE_LOW, bool GPIO_QSPI_SS_EDGE_HIGH,
        bool GPIO_QSPI_SD0_LEVEL_LOW, bool GPIO_QSPI_SD0_LEVEL_HIGH,
        bool GPIO_QSPI_SD0_EDGE_LOW, bool GPIO_QSPI_SD0_EDGE_HIGH,
        bool GPIO_QSPI_SD1_LEVEL_LOW, bool GPIO_QSPI_SD1_LEVEL_HIGH,
        bool GPIO_QSPI_SD1_EDGE_LOW, bool GPIO_QSPI_SD1_EDGE_HIGH,
        bool GPIO_QSPI_SD2_LEVEL_LOW, bool GPIO_QSPI_SD2_LEVEL_HIGH,
        bool GPIO_QSPI_SD2_EDGE_LOW, bool GPIO_QSPI_SD2_EDGE_HIGH,
        bool GPIO_QSPI_SD3_LEVEL_LOW, bool GPIO_QSPI_SD3_LEVEL_HIGH,
        bool GPIO_QSPI_SD3_EDGE_LOW, bool GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = DORMANT_WAKE_INTF;

        curr &= ~(0b1u << 0u);
        curr |= (GPIO_QSPI_SCLK_LEVEL_LOW & 0b1u) << 0u;
        curr &= ~(0b1u << 1u);
        curr |= (GPIO_QSPI_SCLK_LEVEL_HIGH & 0b1u) << 1u;
        curr &= ~(0b1u << 2u);
        curr |= (GPIO_QSPI_SCLK_EDGE_LOW & 0b1u) << 2u;
        curr &= ~(0b1u << 3u);
        curr |= (GPIO_QSPI_SCLK_EDGE_HIGH & 0b1u) << 3u;
        curr &= ~(0b1u << 4u);
        curr |= (GPIO_QSPI_SS_LEVEL_LOW & 0b1u) << 4u;
        curr &= ~(0b1u << 5u);
        curr |= (GPIO_QSPI_SS_LEVEL_HIGH & 0b1u) << 5u;
        curr &= ~(0b1u << 6u);
        curr |= (GPIO_QSPI_SS_EDGE_LOW & 0b1u) << 6u;
        curr &= ~(0b1u << 7u);
        curr |= (GPIO_QSPI_SS_EDGE_HIGH & 0b1u) << 7u;
        curr &= ~(0b1u << 8u);
        curr |= (GPIO_QSPI_SD0_LEVEL_LOW & 0b1u) << 8u;
        curr &= ~(0b1u << 9u);
        curr |= (GPIO_QSPI_SD0_LEVEL_HIGH & 0b1u) << 9u;
        curr &= ~(0b1u << 10u);
        curr |= (GPIO_QSPI_SD0_EDGE_LOW & 0b1u) << 10u;
        curr &= ~(0b1u << 11u);
        curr |= (GPIO_QSPI_SD0_EDGE_HIGH & 0b1u) << 11u;
        curr &= ~(0b1u << 12u);
        curr |= (GPIO_QSPI_SD1_LEVEL_LOW & 0b1u) << 12u;
        curr &= ~(0b1u << 13u);
        curr |= (GPIO_QSPI_SD1_LEVEL_HIGH & 0b1u) << 13u;
        curr &= ~(0b1u << 14u);
        curr |= (GPIO_QSPI_SD1_EDGE_LOW & 0b1u) << 14u;
        curr &= ~(0b1u << 15u);
        curr |= (GPIO_QSPI_SD1_EDGE_HIGH & 0b1u) << 15u;
        curr &= ~(0b1u << 16u);
        curr |= (GPIO_QSPI_SD2_LEVEL_LOW & 0b1u) << 16u;
        curr &= ~(0b1u << 17u);
        curr |= (GPIO_QSPI_SD2_LEVEL_HIGH & 0b1u) << 17u;
        curr &= ~(0b1u << 18u);
        curr |= (GPIO_QSPI_SD2_EDGE_LOW & 0b1u) << 18u;
        curr &= ~(0b1u << 19u);
        curr |= (GPIO_QSPI_SD2_EDGE_HIGH & 0b1u) << 19u;
        curr &= ~(0b1u << 20u);
        curr |= (GPIO_QSPI_SD3_LEVEL_LOW & 0b1u) << 20u;
        curr &= ~(0b1u << 21u);
        curr |= (GPIO_QSPI_SD3_LEVEL_HIGH & 0b1u) << 21u;
        curr &= ~(0b1u << 22u);
        curr |= (GPIO_QSPI_SD3_EDGE_LOW & 0b1u) << 22u;
        curr &= ~(0b1u << 23u);
        curr |= (GPIO_QSPI_SD3_EDGE_HIGH & 0b1u) << 23u;

        DORMANT_WAKE_INTF = curr;
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 0u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 1u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 2u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 3u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 4u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 5u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 6u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 7u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 8u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 9u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 10u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 11u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 12u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 13u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 14u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 15u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 16u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 17u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 18u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 19u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 20u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 21u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 22u);
    }

    inline bool get_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH() volatile
    {
        return DORMANT_WAKE_INTS & (1u << 23u);
    }

    inline void get_DORMANT_WAKE_INTS(
        bool &GPIO_QSPI_SCLK_LEVEL_LOW, bool &GPIO_QSPI_SCLK_LEVEL_HIGH,
        bool &GPIO_QSPI_SCLK_EDGE_LOW, bool &GPIO_QSPI_SCLK_EDGE_HIGH,
        bool &GPIO_QSPI_SS_LEVEL_LOW, bool &GPIO_QSPI_SS_LEVEL_HIGH,
        bool &GPIO_QSPI_SS_EDGE_LOW, bool &GPIO_QSPI_SS_EDGE_HIGH,
        bool &GPIO_QSPI_SD0_LEVEL_LOW, bool &GPIO_QSPI_SD0_LEVEL_HIGH,
        bool &GPIO_QSPI_SD0_EDGE_LOW, bool &GPIO_QSPI_SD0_EDGE_HIGH,
        bool &GPIO_QSPI_SD1_LEVEL_LOW, bool &GPIO_QSPI_SD1_LEVEL_HIGH,
        bool &GPIO_QSPI_SD1_EDGE_LOW, bool &GPIO_QSPI_SD1_EDGE_HIGH,
        bool &GPIO_QSPI_SD2_LEVEL_LOW, bool &GPIO_QSPI_SD2_LEVEL_HIGH,
        bool &GPIO_QSPI_SD2_EDGE_LOW, bool &GPIO_QSPI_SD2_EDGE_HIGH,
        bool &GPIO_QSPI_SD3_LEVEL_LOW, bool &GPIO_QSPI_SD3_LEVEL_HIGH,
        bool &GPIO_QSPI_SD3_EDGE_LOW, bool &GPIO_QSPI_SD3_EDGE_HIGH) volatile
    {
        uint32_t curr = DORMANT_WAKE_INTS;

        GPIO_QSPI_SCLK_LEVEL_LOW = curr & (1u << 0u);
        GPIO_QSPI_SCLK_LEVEL_HIGH = curr & (1u << 1u);
        GPIO_QSPI_SCLK_EDGE_LOW = curr & (1u << 2u);
        GPIO_QSPI_SCLK_EDGE_HIGH = curr & (1u << 3u);
        GPIO_QSPI_SS_LEVEL_LOW = curr & (1u << 4u);
        GPIO_QSPI_SS_LEVEL_HIGH = curr & (1u << 5u);
        GPIO_QSPI_SS_EDGE_LOW = curr & (1u << 6u);
        GPIO_QSPI_SS_EDGE_HIGH = curr & (1u << 7u);
        GPIO_QSPI_SD0_LEVEL_LOW = curr & (1u << 8u);
        GPIO_QSPI_SD0_LEVEL_HIGH = curr & (1u << 9u);
        GPIO_QSPI_SD0_EDGE_LOW = curr & (1u << 10u);
        GPIO_QSPI_SD0_EDGE_HIGH = curr & (1u << 11u);
        GPIO_QSPI_SD1_LEVEL_LOW = curr & (1u << 12u);
        GPIO_QSPI_SD1_LEVEL_HIGH = curr & (1u << 13u);
        GPIO_QSPI_SD1_EDGE_LOW = curr & (1u << 14u);
        GPIO_QSPI_SD1_EDGE_HIGH = curr & (1u << 15u);
        GPIO_QSPI_SD2_LEVEL_LOW = curr & (1u << 16u);
        GPIO_QSPI_SD2_LEVEL_HIGH = curr & (1u << 17u);
        GPIO_QSPI_SD2_EDGE_LOW = curr & (1u << 18u);
        GPIO_QSPI_SD2_EDGE_HIGH = curr & (1u << 19u);
        GPIO_QSPI_SD3_LEVEL_LOW = curr & (1u << 20u);
        GPIO_QSPI_SD3_LEVEL_HIGH = curr & (1u << 21u);
        GPIO_QSPI_SD3_EDGE_LOW = curr & (1u << 22u);
        GPIO_QSPI_SD3_EDGE_HIGH = curr & (1u << 23u);
    }
};

static_assert(sizeof(io_qspi) == io_qspi::size);

static volatile io_qspi *const IO_QSPI =
    reinterpret_cast<io_qspi *>(0x40018000);

}; // namespace RP2040