Program Listing for File i2c0.h#
↰ Return to documentation for file (src/generated/structs/i2c0.h)
#pragma once
#include "../enums/I2C0_IC_CON_SPEED.h"
#include "../ifgen/common.h"
namespace RP2040
{
struct [[gnu::packed]] i2c0
{
/* Constant attributes. */
static constexpr std::size_t size = 256;
/* Fields. */
uint32_t IC_CON;
uint32_t IC_TAR;
uint32_t IC_SAR;
const uint32_t reserved_padding0 = {};
uint32_t IC_DATA_CMD;
uint32_t IC_SS_SCL_HCNT;
uint32_t IC_SS_SCL_LCNT;
uint32_t IC_FS_SCL_HCNT;
uint32_t IC_FS_SCL_LCNT;
static constexpr std::size_t reserved_padding1_length = 2;
const uint32_t reserved_padding1[reserved_padding1_length] = {};
const uint32_t IC_INTR_STAT = {};
uint32_t IC_INTR_MASK;
const uint32_t IC_RAW_INTR_STAT = {};
uint32_t IC_RX_TL;
uint32_t
IC_TX_TL;
const uint32_t IC_CLR_INTR = {};
const uint32_t IC_CLR_RX_UNDER =
{};
const uint32_t IC_CLR_RX_OVER =
{};
const uint32_t IC_CLR_TX_OVER =
{};
const uint32_t IC_CLR_RD_REQ =
{};
const uint32_t IC_CLR_TX_ABRT =
{};
const uint32_t IC_CLR_RX_DONE =
{};
const uint32_t IC_CLR_ACTIVITY =
{};
const uint32_t IC_CLR_STOP_DET =
{};
const uint32_t IC_CLR_START_DET =
{};
const uint32_t IC_CLR_GEN_CALL =
{};
uint32_t IC_ENABLE;
const uint32_t IC_STATUS = {};
const uint32_t IC_TXFLR =
{};
const uint32_t IC_RXFLR =
{};
uint32_t IC_SDA_HOLD;
const uint32_t IC_TX_ABRT_SOURCE =
{};
uint32_t IC_SLV_DATA_NACK_ONLY;
uint32_t IC_DMA_CR;
uint32_t IC_DMA_TDLR;
uint32_t IC_DMA_RDLR;
uint32_t IC_SDA_SETUP;
uint32_t IC_ACK_GENERAL_CALL;
const uint32_t IC_ENABLE_STATUS = {};
uint32_t IC_FS_SPKLEN;
const uint32_t reserved_padding2 = {};
const uint32_t IC_CLR_RESTART_DET =
{};
static constexpr std::size_t reserved_padding3_length = 18;
const uint32_t reserved_padding3[reserved_padding3_length] = {};
const uint32_t IC_COMP_PARAM_1 = {};
const uint32_t IC_COMP_VERSION =
{};
const uint32_t IC_COMP_TYPE =
{};
/* Methods. */
inline bool get_IC_CON_MASTER_MODE() volatile
{
return IC_CON & (1u << 0u);
}
inline void set_IC_CON_MASTER_MODE() volatile
{
IC_CON |= 1u << 0u;
}
inline void clear_IC_CON_MASTER_MODE() volatile
{
IC_CON &= ~(1u << 0u);
}
inline void toggle_IC_CON_MASTER_MODE() volatile
{
IC_CON ^= 1u << 0u;
}
inline I2C0_IC_CON_SPEED get_IC_CON_SPEED() volatile
{
return I2C0_IC_CON_SPEED((IC_CON >> 1u) & 0b11u);
}
inline void set_IC_CON_SPEED(I2C0_IC_CON_SPEED value) volatile
{
uint32_t curr = IC_CON;
curr &= ~(0b11u << 1u);
curr |= (std::to_underlying(value) & 0b11u) << 1u;
IC_CON = curr;
}
inline bool get_IC_CON_IC_10BITADDR_SLAVE() volatile
{
return IC_CON & (1u << 3u);
}
inline void set_IC_CON_IC_10BITADDR_SLAVE() volatile
{
IC_CON |= 1u << 3u;
}
inline void clear_IC_CON_IC_10BITADDR_SLAVE() volatile
{
IC_CON &= ~(1u << 3u);
}
inline void toggle_IC_CON_IC_10BITADDR_SLAVE() volatile
{
IC_CON ^= 1u << 3u;
}
inline bool get_IC_CON_IC_10BITADDR_MASTER() volatile
{
return IC_CON & (1u << 4u);
}
inline void set_IC_CON_IC_10BITADDR_MASTER() volatile
{
IC_CON |= 1u << 4u;
}
inline void clear_IC_CON_IC_10BITADDR_MASTER() volatile
{
IC_CON &= ~(1u << 4u);
}
inline void toggle_IC_CON_IC_10BITADDR_MASTER() volatile
{
IC_CON ^= 1u << 4u;
}
inline bool get_IC_CON_IC_RESTART_EN() volatile
{
return IC_CON & (1u << 5u);
}
inline void set_IC_CON_IC_RESTART_EN() volatile
{
IC_CON |= 1u << 5u;
}
inline void clear_IC_CON_IC_RESTART_EN() volatile
{
IC_CON &= ~(1u << 5u);
}
inline void toggle_IC_CON_IC_RESTART_EN() volatile
{
IC_CON ^= 1u << 5u;
}
inline bool get_IC_CON_IC_SLAVE_DISABLE() volatile
{
return IC_CON & (1u << 6u);
}
inline void set_IC_CON_IC_SLAVE_DISABLE() volatile
{
IC_CON |= 1u << 6u;
}
inline void clear_IC_CON_IC_SLAVE_DISABLE() volatile
{
IC_CON &= ~(1u << 6u);
}
inline void toggle_IC_CON_IC_SLAVE_DISABLE() volatile
{
IC_CON ^= 1u << 6u;
}
inline bool get_IC_CON_STOP_DET_IFADDRESSED() volatile
{
return IC_CON & (1u << 7u);
}
inline void set_IC_CON_STOP_DET_IFADDRESSED() volatile
{
IC_CON |= 1u << 7u;
}
inline void clear_IC_CON_STOP_DET_IFADDRESSED() volatile
{
IC_CON &= ~(1u << 7u);
}
inline void toggle_IC_CON_STOP_DET_IFADDRESSED() volatile
{
IC_CON ^= 1u << 7u;
}
inline bool get_IC_CON_TX_EMPTY_CTRL() volatile
{
return IC_CON & (1u << 8u);
}
inline void set_IC_CON_TX_EMPTY_CTRL() volatile
{
IC_CON |= 1u << 8u;
}
inline void clear_IC_CON_TX_EMPTY_CTRL() volatile
{
IC_CON &= ~(1u << 8u);
}
inline void toggle_IC_CON_TX_EMPTY_CTRL() volatile
{
IC_CON ^= 1u << 8u;
}
inline bool get_IC_CON_RX_FIFO_FULL_HLD_CTRL() volatile
{
return IC_CON & (1u << 9u);
}
inline void set_IC_CON_RX_FIFO_FULL_HLD_CTRL() volatile
{
IC_CON |= 1u << 9u;
}
inline void clear_IC_CON_RX_FIFO_FULL_HLD_CTRL() volatile
{
IC_CON &= ~(1u << 9u);
}
inline void toggle_IC_CON_RX_FIFO_FULL_HLD_CTRL() volatile
{
IC_CON ^= 1u << 9u;
}
inline bool get_IC_CON_STOP_DET_IF_MASTER_ACTIVE() volatile
{
return IC_CON & (1u << 10u);
}
inline void get_IC_CON(bool &MASTER_MODE, I2C0_IC_CON_SPEED &SPEED,
bool &IC_10BITADDR_SLAVE, bool &IC_10BITADDR_MASTER,
bool &IC_RESTART_EN, bool &IC_SLAVE_DISABLE,
bool &STOP_DET_IFADDRESSED, bool &TX_EMPTY_CTRL,
bool &RX_FIFO_FULL_HLD_CTRL,
bool &STOP_DET_IF_MASTER_ACTIVE) volatile
{
uint32_t curr = IC_CON;
MASTER_MODE = curr & (1u << 0u);
SPEED = I2C0_IC_CON_SPEED((curr >> 1u) & 0b11u);
IC_10BITADDR_SLAVE = curr & (1u << 3u);
IC_10BITADDR_MASTER = curr & (1u << 4u);
IC_RESTART_EN = curr & (1u << 5u);
IC_SLAVE_DISABLE = curr & (1u << 6u);
STOP_DET_IFADDRESSED = curr & (1u << 7u);
TX_EMPTY_CTRL = curr & (1u << 8u);
RX_FIFO_FULL_HLD_CTRL = curr & (1u << 9u);
STOP_DET_IF_MASTER_ACTIVE = curr & (1u << 10u);
}
inline void set_IC_CON(bool MASTER_MODE, I2C0_IC_CON_SPEED SPEED,
bool IC_10BITADDR_SLAVE, bool IC_10BITADDR_MASTER,
bool IC_RESTART_EN, bool IC_SLAVE_DISABLE,
bool STOP_DET_IFADDRESSED, bool TX_EMPTY_CTRL,
bool RX_FIFO_FULL_HLD_CTRL) volatile
{
uint32_t curr = IC_CON;
curr &= ~(0b1u << 0u);
curr |= (MASTER_MODE & 0b1u) << 0u;
curr &= ~(0b11u << 1u);
curr |= (std::to_underlying(SPEED) & 0b11u) << 1u;
curr &= ~(0b1u << 3u);
curr |= (IC_10BITADDR_SLAVE & 0b1u) << 3u;
curr &= ~(0b1u << 4u);
curr |= (IC_10BITADDR_MASTER & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (IC_RESTART_EN & 0b1u) << 5u;
curr &= ~(0b1u << 6u);
curr |= (IC_SLAVE_DISABLE & 0b1u) << 6u;
curr &= ~(0b1u << 7u);
curr |= (STOP_DET_IFADDRESSED & 0b1u) << 7u;
curr &= ~(0b1u << 8u);
curr |= (TX_EMPTY_CTRL & 0b1u) << 8u;
curr &= ~(0b1u << 9u);
curr |= (RX_FIFO_FULL_HLD_CTRL & 0b1u) << 9u;
IC_CON = curr;
}
inline uint16_t get_IC_TAR_IC_TAR() volatile
{
return (IC_TAR >> 0u) & 0b1111111111u;
}
inline void set_IC_TAR_IC_TAR(uint16_t value) volatile
{
uint32_t curr = IC_TAR;
curr &= ~(0b1111111111u << 0u);
curr |= (value & 0b1111111111u) << 0u;
IC_TAR = curr;
}
inline bool get_IC_TAR_GC_OR_START() volatile
{
return IC_TAR & (1u << 10u);
}
inline void set_IC_TAR_GC_OR_START() volatile
{
IC_TAR |= 1u << 10u;
}
inline void clear_IC_TAR_GC_OR_START() volatile
{
IC_TAR &= ~(1u << 10u);
}
inline void toggle_IC_TAR_GC_OR_START() volatile
{
IC_TAR ^= 1u << 10u;
}
inline bool get_IC_TAR_SPECIAL() volatile
{
return IC_TAR & (1u << 11u);
}
inline void set_IC_TAR_SPECIAL() volatile
{
IC_TAR |= 1u << 11u;
}
inline void clear_IC_TAR_SPECIAL() volatile
{
IC_TAR &= ~(1u << 11u);
}
inline void toggle_IC_TAR_SPECIAL() volatile
{
IC_TAR ^= 1u << 11u;
}
inline void get_IC_TAR(uint16_t &IC_TAR, bool &GC_OR_START,
bool &SPECIAL) volatile
{
uint32_t curr = IC_TAR;
IC_TAR = (curr >> 0u) & 0b1111111111u;
GC_OR_START = curr & (1u << 10u);
SPECIAL = curr & (1u << 11u);
}
inline void set_IC_TAR(uint16_t IC_TAR, bool GC_OR_START,
bool SPECIAL) volatile
{
uint32_t curr = IC_TAR;
curr &= ~(0b1111111111u << 0u);
curr |= (IC_TAR & 0b1111111111u) << 0u;
curr &= ~(0b1u << 10u);
curr |= (GC_OR_START & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (SPECIAL & 0b1u) << 11u;
IC_TAR = curr;
}
inline uint16_t get_IC_SAR_IC_SAR() volatile
{
return (IC_SAR >> 0u) & 0b1111111111u;
}
inline void set_IC_SAR_IC_SAR(uint16_t value) volatile
{
uint32_t curr = IC_SAR;
curr &= ~(0b1111111111u << 0u);
curr |= (value & 0b1111111111u) << 0u;
IC_SAR = curr;
}
inline uint8_t get_IC_DATA_CMD_DAT() volatile
{
return (IC_DATA_CMD >> 0u) & 0b11111111u;
}
inline void set_IC_DATA_CMD_DAT(uint8_t value) volatile
{
uint32_t curr = IC_DATA_CMD;
curr &= ~(0b11111111u << 0u);
curr |= (value & 0b11111111u) << 0u;
IC_DATA_CMD = curr;
}
inline bool get_IC_DATA_CMD_CMD() volatile
{
return IC_DATA_CMD & (1u << 8u);
}
inline void set_IC_DATA_CMD_CMD() volatile
{
IC_DATA_CMD |= 1u << 8u;
}
inline void clear_IC_DATA_CMD_CMD() volatile
{
IC_DATA_CMD &= ~(1u << 8u);
}
inline void toggle_IC_DATA_CMD_CMD() volatile
{
IC_DATA_CMD ^= 1u << 8u;
}
inline bool get_IC_DATA_CMD_STOP() volatile
{
return IC_DATA_CMD & (1u << 9u);
}
inline void set_IC_DATA_CMD_STOP() volatile
{
IC_DATA_CMD |= 1u << 9u;
}
inline void clear_IC_DATA_CMD_STOP() volatile
{
IC_DATA_CMD &= ~(1u << 9u);
}
inline void toggle_IC_DATA_CMD_STOP() volatile
{
IC_DATA_CMD ^= 1u << 9u;
}
inline bool get_IC_DATA_CMD_RESTART() volatile
{
return IC_DATA_CMD & (1u << 10u);
}
inline void set_IC_DATA_CMD_RESTART() volatile
{
IC_DATA_CMD |= 1u << 10u;
}
inline void clear_IC_DATA_CMD_RESTART() volatile
{
IC_DATA_CMD &= ~(1u << 10u);
}
inline void toggle_IC_DATA_CMD_RESTART() volatile
{
IC_DATA_CMD ^= 1u << 10u;
}
inline bool get_IC_DATA_CMD_FIRST_DATA_BYTE() volatile
{
return IC_DATA_CMD & (1u << 11u);
}
inline void get_IC_DATA_CMD(uint8_t &DAT, bool &CMD, bool &STOP,
bool &RESTART, bool &FIRST_DATA_BYTE) volatile
{
uint32_t curr = IC_DATA_CMD;
DAT = (curr >> 0u) & 0b11111111u;
CMD = curr & (1u << 8u);
STOP = curr & (1u << 9u);
RESTART = curr & (1u << 10u);
FIRST_DATA_BYTE = curr & (1u << 11u);
}
inline void set_IC_DATA_CMD(uint8_t DAT, bool CMD, bool STOP,
bool RESTART) volatile
{
uint32_t curr = IC_DATA_CMD;
curr &= ~(0b11111111u << 0u);
curr |= (DAT & 0b11111111u) << 0u;
curr &= ~(0b1u << 8u);
curr |= (CMD & 0b1u) << 8u;
curr &= ~(0b1u << 9u);
curr |= (STOP & 0b1u) << 9u;
curr &= ~(0b1u << 10u);
curr |= (RESTART & 0b1u) << 10u;
IC_DATA_CMD = curr;
}
inline uint16_t get_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT() volatile
{
return (IC_SS_SCL_HCNT >> 0u) & 0b1111111111111111u;
}
inline void set_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT(uint16_t value) volatile
{
uint32_t curr = IC_SS_SCL_HCNT;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
IC_SS_SCL_HCNT = curr;
}
inline uint16_t get_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT() volatile
{
return (IC_SS_SCL_LCNT >> 0u) & 0b1111111111111111u;
}
inline void set_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT(uint16_t value) volatile
{
uint32_t curr = IC_SS_SCL_LCNT;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
IC_SS_SCL_LCNT = curr;
}
inline uint16_t get_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT() volatile
{
return (IC_FS_SCL_HCNT >> 0u) & 0b1111111111111111u;
}
inline void set_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT(uint16_t value) volatile
{
uint32_t curr = IC_FS_SCL_HCNT;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
IC_FS_SCL_HCNT = curr;
}
inline uint16_t get_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT() volatile
{
return (IC_FS_SCL_LCNT >> 0u) & 0b1111111111111111u;
}
inline void set_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT(uint16_t value) volatile
{
uint32_t curr = IC_FS_SCL_LCNT;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
IC_FS_SCL_LCNT = curr;
}
inline bool get_IC_INTR_STAT_R_RX_UNDER() volatile
{
return IC_INTR_STAT & (1u << 0u);
}
inline bool get_IC_INTR_STAT_R_RX_OVER() volatile
{
return IC_INTR_STAT & (1u << 1u);
}
inline bool get_IC_INTR_STAT_R_RX_FULL() volatile
{
return IC_INTR_STAT & (1u << 2u);
}
inline bool get_IC_INTR_STAT_R_TX_OVER() volatile
{
return IC_INTR_STAT & (1u << 3u);
}
inline bool get_IC_INTR_STAT_R_TX_EMPTY() volatile
{
return IC_INTR_STAT & (1u << 4u);
}
inline bool get_IC_INTR_STAT_R_RD_REQ() volatile
{
return IC_INTR_STAT & (1u << 5u);
}
inline bool get_IC_INTR_STAT_R_TX_ABRT() volatile
{
return IC_INTR_STAT & (1u << 6u);
}
inline bool get_IC_INTR_STAT_R_RX_DONE() volatile
{
return IC_INTR_STAT & (1u << 7u);
}
inline bool get_IC_INTR_STAT_R_ACTIVITY() volatile
{
return IC_INTR_STAT & (1u << 8u);
}
inline bool get_IC_INTR_STAT_R_STOP_DET() volatile
{
return IC_INTR_STAT & (1u << 9u);
}
inline bool get_IC_INTR_STAT_R_START_DET() volatile
{
return IC_INTR_STAT & (1u << 10u);
}
inline bool get_IC_INTR_STAT_R_GEN_CALL() volatile
{
return IC_INTR_STAT & (1u << 11u);
}
inline bool get_IC_INTR_STAT_R_RESTART_DET() volatile
{
return IC_INTR_STAT & (1u << 12u);
}
inline void get_IC_INTR_STAT(bool &R_RX_UNDER, bool &R_RX_OVER,
bool &R_RX_FULL, bool &R_TX_OVER,
bool &R_TX_EMPTY, bool &R_RD_REQ,
bool &R_TX_ABRT, bool &R_RX_DONE,
bool &R_ACTIVITY, bool &R_STOP_DET,
bool &R_START_DET, bool &R_GEN_CALL,
bool &R_RESTART_DET) volatile
{
uint32_t curr = IC_INTR_STAT;
R_RX_UNDER = curr & (1u << 0u);
R_RX_OVER = curr & (1u << 1u);
R_RX_FULL = curr & (1u << 2u);
R_TX_OVER = curr & (1u << 3u);
R_TX_EMPTY = curr & (1u << 4u);
R_RD_REQ = curr & (1u << 5u);
R_TX_ABRT = curr & (1u << 6u);
R_RX_DONE = curr & (1u << 7u);
R_ACTIVITY = curr & (1u << 8u);
R_STOP_DET = curr & (1u << 9u);
R_START_DET = curr & (1u << 10u);
R_GEN_CALL = curr & (1u << 11u);
R_RESTART_DET = curr & (1u << 12u);
}
inline bool get_IC_INTR_MASK_M_RX_UNDER() volatile
{
return IC_INTR_MASK & (1u << 0u);
}
inline void set_IC_INTR_MASK_M_RX_UNDER() volatile
{
IC_INTR_MASK |= 1u << 0u;
}
inline void clear_IC_INTR_MASK_M_RX_UNDER() volatile
{
IC_INTR_MASK &= ~(1u << 0u);
}
inline void toggle_IC_INTR_MASK_M_RX_UNDER() volatile
{
IC_INTR_MASK ^= 1u << 0u;
}
inline bool get_IC_INTR_MASK_M_RX_OVER() volatile
{
return IC_INTR_MASK & (1u << 1u);
}
inline void set_IC_INTR_MASK_M_RX_OVER() volatile
{
IC_INTR_MASK |= 1u << 1u;
}
inline void clear_IC_INTR_MASK_M_RX_OVER() volatile
{
IC_INTR_MASK &= ~(1u << 1u);
}
inline void toggle_IC_INTR_MASK_M_RX_OVER() volatile
{
IC_INTR_MASK ^= 1u << 1u;
}
inline bool get_IC_INTR_MASK_M_RX_FULL() volatile
{
return IC_INTR_MASK & (1u << 2u);
}
inline void set_IC_INTR_MASK_M_RX_FULL() volatile
{
IC_INTR_MASK |= 1u << 2u;
}
inline void clear_IC_INTR_MASK_M_RX_FULL() volatile
{
IC_INTR_MASK &= ~(1u << 2u);
}
inline void toggle_IC_INTR_MASK_M_RX_FULL() volatile
{
IC_INTR_MASK ^= 1u << 2u;
}
inline bool get_IC_INTR_MASK_M_TX_OVER() volatile
{
return IC_INTR_MASK & (1u << 3u);
}
inline void set_IC_INTR_MASK_M_TX_OVER() volatile
{
IC_INTR_MASK |= 1u << 3u;
}
inline void clear_IC_INTR_MASK_M_TX_OVER() volatile
{
IC_INTR_MASK &= ~(1u << 3u);
}
inline void toggle_IC_INTR_MASK_M_TX_OVER() volatile
{
IC_INTR_MASK ^= 1u << 3u;
}
inline bool get_IC_INTR_MASK_M_TX_EMPTY() volatile
{
return IC_INTR_MASK & (1u << 4u);
}
inline void set_IC_INTR_MASK_M_TX_EMPTY() volatile
{
IC_INTR_MASK |= 1u << 4u;
}
inline void clear_IC_INTR_MASK_M_TX_EMPTY() volatile
{
IC_INTR_MASK &= ~(1u << 4u);
}
inline void toggle_IC_INTR_MASK_M_TX_EMPTY() volatile
{
IC_INTR_MASK ^= 1u << 4u;
}
inline bool get_IC_INTR_MASK_M_RD_REQ() volatile
{
return IC_INTR_MASK & (1u << 5u);
}
inline void set_IC_INTR_MASK_M_RD_REQ() volatile
{
IC_INTR_MASK |= 1u << 5u;
}
inline void clear_IC_INTR_MASK_M_RD_REQ() volatile
{
IC_INTR_MASK &= ~(1u << 5u);
}
inline void toggle_IC_INTR_MASK_M_RD_REQ() volatile
{
IC_INTR_MASK ^= 1u << 5u;
}
inline bool get_IC_INTR_MASK_M_TX_ABRT() volatile
{
return IC_INTR_MASK & (1u << 6u);
}
inline void set_IC_INTR_MASK_M_TX_ABRT() volatile
{
IC_INTR_MASK |= 1u << 6u;
}
inline void clear_IC_INTR_MASK_M_TX_ABRT() volatile
{
IC_INTR_MASK &= ~(1u << 6u);
}
inline void toggle_IC_INTR_MASK_M_TX_ABRT() volatile
{
IC_INTR_MASK ^= 1u << 6u;
}
inline bool get_IC_INTR_MASK_M_RX_DONE() volatile
{
return IC_INTR_MASK & (1u << 7u);
}
inline void set_IC_INTR_MASK_M_RX_DONE() volatile
{
IC_INTR_MASK |= 1u << 7u;
}
inline void clear_IC_INTR_MASK_M_RX_DONE() volatile
{
IC_INTR_MASK &= ~(1u << 7u);
}
inline void toggle_IC_INTR_MASK_M_RX_DONE() volatile
{
IC_INTR_MASK ^= 1u << 7u;
}
inline bool get_IC_INTR_MASK_M_ACTIVITY() volatile
{
return IC_INTR_MASK & (1u << 8u);
}
inline void set_IC_INTR_MASK_M_ACTIVITY() volatile
{
IC_INTR_MASK |= 1u << 8u;
}
inline void clear_IC_INTR_MASK_M_ACTIVITY() volatile
{
IC_INTR_MASK &= ~(1u << 8u);
}
inline void toggle_IC_INTR_MASK_M_ACTIVITY() volatile
{
IC_INTR_MASK ^= 1u << 8u;
}
inline bool get_IC_INTR_MASK_M_STOP_DET() volatile
{
return IC_INTR_MASK & (1u << 9u);
}
inline void set_IC_INTR_MASK_M_STOP_DET() volatile
{
IC_INTR_MASK |= 1u << 9u;
}
inline void clear_IC_INTR_MASK_M_STOP_DET() volatile
{
IC_INTR_MASK &= ~(1u << 9u);
}
inline void toggle_IC_INTR_MASK_M_STOP_DET() volatile
{
IC_INTR_MASK ^= 1u << 9u;
}
inline bool get_IC_INTR_MASK_M_START_DET() volatile
{
return IC_INTR_MASK & (1u << 10u);
}
inline void set_IC_INTR_MASK_M_START_DET() volatile
{
IC_INTR_MASK |= 1u << 10u;
}
inline void clear_IC_INTR_MASK_M_START_DET() volatile
{
IC_INTR_MASK &= ~(1u << 10u);
}
inline void toggle_IC_INTR_MASK_M_START_DET() volatile
{
IC_INTR_MASK ^= 1u << 10u;
}
inline bool get_IC_INTR_MASK_M_GEN_CALL() volatile
{
return IC_INTR_MASK & (1u << 11u);
}
inline void set_IC_INTR_MASK_M_GEN_CALL() volatile
{
IC_INTR_MASK |= 1u << 11u;
}
inline void clear_IC_INTR_MASK_M_GEN_CALL() volatile
{
IC_INTR_MASK &= ~(1u << 11u);
}
inline void toggle_IC_INTR_MASK_M_GEN_CALL() volatile
{
IC_INTR_MASK ^= 1u << 11u;
}
inline bool get_IC_INTR_MASK_M_RESTART_DET() volatile
{
return IC_INTR_MASK & (1u << 12u);
}
inline void set_IC_INTR_MASK_M_RESTART_DET() volatile
{
IC_INTR_MASK |= 1u << 12u;
}
inline void clear_IC_INTR_MASK_M_RESTART_DET() volatile
{
IC_INTR_MASK &= ~(1u << 12u);
}
inline void toggle_IC_INTR_MASK_M_RESTART_DET() volatile
{
IC_INTR_MASK ^= 1u << 12u;
}
inline void get_IC_INTR_MASK(bool &M_RX_UNDER, bool &M_RX_OVER,
bool &M_RX_FULL, bool &M_TX_OVER,
bool &M_TX_EMPTY, bool &M_RD_REQ,
bool &M_TX_ABRT, bool &M_RX_DONE,
bool &M_ACTIVITY, bool &M_STOP_DET,
bool &M_START_DET, bool &M_GEN_CALL,
bool &M_RESTART_DET) volatile
{
uint32_t curr = IC_INTR_MASK;
M_RX_UNDER = curr & (1u << 0u);
M_RX_OVER = curr & (1u << 1u);
M_RX_FULL = curr & (1u << 2u);
M_TX_OVER = curr & (1u << 3u);
M_TX_EMPTY = curr & (1u << 4u);
M_RD_REQ = curr & (1u << 5u);
M_TX_ABRT = curr & (1u << 6u);
M_RX_DONE = curr & (1u << 7u);
M_ACTIVITY = curr & (1u << 8u);
M_STOP_DET = curr & (1u << 9u);
M_START_DET = curr & (1u << 10u);
M_GEN_CALL = curr & (1u << 11u);
M_RESTART_DET = curr & (1u << 12u);
}
inline void set_IC_INTR_MASK(bool M_RX_UNDER, bool M_RX_OVER,
bool M_RX_FULL, bool M_TX_OVER,
bool M_TX_EMPTY, bool M_RD_REQ,
bool M_TX_ABRT, bool M_RX_DONE,
bool M_ACTIVITY, bool M_STOP_DET,
bool M_START_DET, bool M_GEN_CALL,
bool M_RESTART_DET) volatile
{
uint32_t curr = IC_INTR_MASK;
curr &= ~(0b1u << 0u);
curr |= (M_RX_UNDER & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (M_RX_OVER & 0b1u) << 1u;
curr &= ~(0b1u << 2u);
curr |= (M_RX_FULL & 0b1u) << 2u;
curr &= ~(0b1u << 3u);
curr |= (M_TX_OVER & 0b1u) << 3u;
curr &= ~(0b1u << 4u);
curr |= (M_TX_EMPTY & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (M_RD_REQ & 0b1u) << 5u;
curr &= ~(0b1u << 6u);
curr |= (M_TX_ABRT & 0b1u) << 6u;
curr &= ~(0b1u << 7u);
curr |= (M_RX_DONE & 0b1u) << 7u;
curr &= ~(0b1u << 8u);
curr |= (M_ACTIVITY & 0b1u) << 8u;
curr &= ~(0b1u << 9u);
curr |= (M_STOP_DET & 0b1u) << 9u;
curr &= ~(0b1u << 10u);
curr |= (M_START_DET & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (M_GEN_CALL & 0b1u) << 11u;
curr &= ~(0b1u << 12u);
curr |= (M_RESTART_DET & 0b1u) << 12u;
IC_INTR_MASK = curr;
}
inline bool get_IC_RAW_INTR_STAT_RX_UNDER() volatile
{
return IC_RAW_INTR_STAT & (1u << 0u);
}
inline bool get_IC_RAW_INTR_STAT_RX_OVER() volatile
{
return IC_RAW_INTR_STAT & (1u << 1u);
}
inline bool get_IC_RAW_INTR_STAT_RX_FULL() volatile
{
return IC_RAW_INTR_STAT & (1u << 2u);
}
inline bool get_IC_RAW_INTR_STAT_TX_OVER() volatile
{
return IC_RAW_INTR_STAT & (1u << 3u);
}
inline bool get_IC_RAW_INTR_STAT_TX_EMPTY() volatile
{
return IC_RAW_INTR_STAT & (1u << 4u);
}
inline bool get_IC_RAW_INTR_STAT_RD_REQ() volatile
{
return IC_RAW_INTR_STAT & (1u << 5u);
}
inline bool get_IC_RAW_INTR_STAT_TX_ABRT() volatile
{
return IC_RAW_INTR_STAT & (1u << 6u);
}
inline bool get_IC_RAW_INTR_STAT_RX_DONE() volatile
{
return IC_RAW_INTR_STAT & (1u << 7u);
}
inline bool get_IC_RAW_INTR_STAT_ACTIVITY() volatile
{
return IC_RAW_INTR_STAT & (1u << 8u);
}
inline bool get_IC_RAW_INTR_STAT_STOP_DET() volatile
{
return IC_RAW_INTR_STAT & (1u << 9u);
}
inline bool get_IC_RAW_INTR_STAT_START_DET() volatile
{
return IC_RAW_INTR_STAT & (1u << 10u);
}
inline bool get_IC_RAW_INTR_STAT_GEN_CALL() volatile
{
return IC_RAW_INTR_STAT & (1u << 11u);
}
inline bool get_IC_RAW_INTR_STAT_RESTART_DET() volatile
{
return IC_RAW_INTR_STAT & (1u << 12u);
}
inline void get_IC_RAW_INTR_STAT(bool &RX_UNDER, bool &RX_OVER,
bool &RX_FULL, bool &TX_OVER,
bool &TX_EMPTY, bool &RD_REQ,
bool &TX_ABRT, bool &RX_DONE,
bool &ACTIVITY, bool &STOP_DET,
bool &START_DET, bool &GEN_CALL,
bool &RESTART_DET) volatile
{
uint32_t curr = IC_RAW_INTR_STAT;
RX_UNDER = curr & (1u << 0u);
RX_OVER = curr & (1u << 1u);
RX_FULL = curr & (1u << 2u);
TX_OVER = curr & (1u << 3u);
TX_EMPTY = curr & (1u << 4u);
RD_REQ = curr & (1u << 5u);
TX_ABRT = curr & (1u << 6u);
RX_DONE = curr & (1u << 7u);
ACTIVITY = curr & (1u << 8u);
STOP_DET = curr & (1u << 9u);
START_DET = curr & (1u << 10u);
GEN_CALL = curr & (1u << 11u);
RESTART_DET = curr & (1u << 12u);
}
inline uint8_t get_IC_RX_TL_RX_TL() volatile
{
return (IC_RX_TL >> 0u) & 0b11111111u;
}
inline void set_IC_RX_TL_RX_TL(uint8_t value) volatile
{
uint32_t curr = IC_RX_TL;
curr &= ~(0b11111111u << 0u);
curr |= (value & 0b11111111u) << 0u;
IC_RX_TL = curr;
}
inline uint8_t get_IC_TX_TL_TX_TL() volatile
{
return (IC_TX_TL >> 0u) & 0b11111111u;
}
inline void set_IC_TX_TL_TX_TL(uint8_t value) volatile
{
uint32_t curr = IC_TX_TL;
curr &= ~(0b11111111u << 0u);
curr |= (value & 0b11111111u) << 0u;
IC_TX_TL = curr;
}
inline bool get_IC_CLR_INTR_CLR_INTR() volatile
{
return IC_CLR_INTR & (1u << 0u);
}
inline bool get_IC_CLR_RX_UNDER_CLR_RX_UNDER() volatile
{
return IC_CLR_RX_UNDER & (1u << 0u);
}
inline bool get_IC_CLR_RX_OVER_CLR_RX_OVER() volatile
{
return IC_CLR_RX_OVER & (1u << 0u);
}
inline bool get_IC_CLR_TX_OVER_CLR_TX_OVER() volatile
{
return IC_CLR_TX_OVER & (1u << 0u);
}
inline bool get_IC_CLR_RD_REQ_CLR_RD_REQ() volatile
{
return IC_CLR_RD_REQ & (1u << 0u);
}
inline bool get_IC_CLR_TX_ABRT_CLR_TX_ABRT() volatile
{
return IC_CLR_TX_ABRT & (1u << 0u);
}
inline bool get_IC_CLR_RX_DONE_CLR_RX_DONE() volatile
{
return IC_CLR_RX_DONE & (1u << 0u);
}
inline bool get_IC_CLR_ACTIVITY_CLR_ACTIVITY() volatile
{
return IC_CLR_ACTIVITY & (1u << 0u);
}
inline bool get_IC_CLR_STOP_DET_CLR_STOP_DET() volatile
{
return IC_CLR_STOP_DET & (1u << 0u);
}
inline bool get_IC_CLR_START_DET_CLR_START_DET() volatile
{
return IC_CLR_START_DET & (1u << 0u);
}
inline bool get_IC_CLR_GEN_CALL_CLR_GEN_CALL() volatile
{
return IC_CLR_GEN_CALL & (1u << 0u);
}
inline bool get_IC_ENABLE_ENABLE() volatile
{
return IC_ENABLE & (1u << 0u);
}
inline void set_IC_ENABLE_ENABLE() volatile
{
IC_ENABLE |= 1u << 0u;
}
inline void clear_IC_ENABLE_ENABLE() volatile
{
IC_ENABLE &= ~(1u << 0u);
}
inline void toggle_IC_ENABLE_ENABLE() volatile
{
IC_ENABLE ^= 1u << 0u;
}
inline bool get_IC_ENABLE_ABORT() volatile
{
return IC_ENABLE & (1u << 1u);
}
inline void set_IC_ENABLE_ABORT() volatile
{
IC_ENABLE |= 1u << 1u;
}
inline void clear_IC_ENABLE_ABORT() volatile
{
IC_ENABLE &= ~(1u << 1u);
}
inline void toggle_IC_ENABLE_ABORT() volatile
{
IC_ENABLE ^= 1u << 1u;
}
inline bool get_IC_ENABLE_TX_CMD_BLOCK() volatile
{
return IC_ENABLE & (1u << 2u);
}
inline void set_IC_ENABLE_TX_CMD_BLOCK() volatile
{
IC_ENABLE |= 1u << 2u;
}
inline void clear_IC_ENABLE_TX_CMD_BLOCK() volatile
{
IC_ENABLE &= ~(1u << 2u);
}
inline void toggle_IC_ENABLE_TX_CMD_BLOCK() volatile
{
IC_ENABLE ^= 1u << 2u;
}
inline void get_IC_ENABLE(bool &ENABLE, bool &ABORT,
bool &TX_CMD_BLOCK) volatile
{
uint32_t curr = IC_ENABLE;
ENABLE = curr & (1u << 0u);
ABORT = curr & (1u << 1u);
TX_CMD_BLOCK = curr & (1u << 2u);
}
inline void set_IC_ENABLE(bool ENABLE, bool ABORT,
bool TX_CMD_BLOCK) volatile
{
uint32_t curr = IC_ENABLE;
curr &= ~(0b1u << 0u);
curr |= (ENABLE & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (ABORT & 0b1u) << 1u;
curr &= ~(0b1u << 2u);
curr |= (TX_CMD_BLOCK & 0b1u) << 2u;
IC_ENABLE = curr;
}
inline bool get_IC_STATUS_ACTIVITY() volatile
{
return IC_STATUS & (1u << 0u);
}
inline bool get_IC_STATUS_TFNF() volatile
{
return IC_STATUS & (1u << 1u);
}
inline bool get_IC_STATUS_TFE() volatile
{
return IC_STATUS & (1u << 2u);
}
inline bool get_IC_STATUS_RFNE() volatile
{
return IC_STATUS & (1u << 3u);
}
inline bool get_IC_STATUS_RFF() volatile
{
return IC_STATUS & (1u << 4u);
}
inline bool get_IC_STATUS_MST_ACTIVITY() volatile
{
return IC_STATUS & (1u << 5u);
}
inline bool get_IC_STATUS_SLV_ACTIVITY() volatile
{
return IC_STATUS & (1u << 6u);
}
inline void get_IC_STATUS(bool &ACTIVITY, bool &TFNF, bool &TFE,
bool &RFNE, bool &RFF, bool &MST_ACTIVITY,
bool &SLV_ACTIVITY) volatile
{
uint32_t curr = IC_STATUS;
ACTIVITY = curr & (1u << 0u);
TFNF = curr & (1u << 1u);
TFE = curr & (1u << 2u);
RFNE = curr & (1u << 3u);
RFF = curr & (1u << 4u);
MST_ACTIVITY = curr & (1u << 5u);
SLV_ACTIVITY = curr & (1u << 6u);
}
inline uint8_t get_IC_TXFLR_TXFLR() volatile
{
return (IC_TXFLR >> 0u) & 0b11111u;
}
inline uint8_t get_IC_RXFLR_RXFLR() volatile
{
return (IC_RXFLR >> 0u) & 0b11111u;
}
inline uint16_t get_IC_SDA_HOLD_IC_SDA_TX_HOLD() volatile
{
return (IC_SDA_HOLD >> 0u) & 0b1111111111111111u;
}
inline void set_IC_SDA_HOLD_IC_SDA_TX_HOLD(uint16_t value) volatile
{
uint32_t curr = IC_SDA_HOLD;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
IC_SDA_HOLD = curr;
}
inline uint8_t get_IC_SDA_HOLD_IC_SDA_RX_HOLD() volatile
{
return (IC_SDA_HOLD >> 16u) & 0b11111111u;
}
inline void set_IC_SDA_HOLD_IC_SDA_RX_HOLD(uint8_t value) volatile
{
uint32_t curr = IC_SDA_HOLD;
curr &= ~(0b11111111u << 16u);
curr |= (value & 0b11111111u) << 16u;
IC_SDA_HOLD = curr;
}
inline void get_IC_SDA_HOLD(uint16_t &IC_SDA_TX_HOLD,
uint8_t &IC_SDA_RX_HOLD) volatile
{
uint32_t curr = IC_SDA_HOLD;
IC_SDA_TX_HOLD = (curr >> 0u) & 0b1111111111111111u;
IC_SDA_RX_HOLD = (curr >> 16u) & 0b11111111u;
}
inline void set_IC_SDA_HOLD(uint16_t IC_SDA_TX_HOLD,
uint8_t IC_SDA_RX_HOLD) volatile
{
uint32_t curr = IC_SDA_HOLD;
curr &= ~(0b1111111111111111u << 0u);
curr |= (IC_SDA_TX_HOLD & 0b1111111111111111u) << 0u;
curr &= ~(0b11111111u << 16u);
curr |= (IC_SDA_RX_HOLD & 0b11111111u) << 16u;
IC_SDA_HOLD = curr;
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 0u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 1u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 2u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 3u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 4u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 5u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 6u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 7u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 8u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 9u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 10u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 11u);
}
inline bool get_IC_TX_ABRT_SOURCE_ARB_LOST() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 12u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 13u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 14u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 15u);
}
inline bool get_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT() volatile
{
return IC_TX_ABRT_SOURCE & (1u << 16u);
}
inline uint16_t get_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT() volatile
{
return (IC_TX_ABRT_SOURCE >> 23u) & 0b111111111u;
}
inline void get_IC_TX_ABRT_SOURCE(
bool &ABRT_7B_ADDR_NOACK, bool &ABRT_10ADDR1_NOACK,
bool &ABRT_10ADDR2_NOACK, bool &ABRT_TXDATA_NOACK,
bool &ABRT_GCALL_NOACK, bool &ABRT_GCALL_READ, bool &ABRT_HS_ACKDET,
bool &ABRT_SBYTE_ACKDET, bool &ABRT_HS_NORSTRT,
bool &ABRT_SBYTE_NORSTRT, bool &ABRT_10B_RD_NORSTRT,
bool &ABRT_MASTER_DIS, bool &ARB_LOST, bool &ABRT_SLVFLUSH_TXFIFO,
bool &ABRT_SLV_ARBLOST, bool &ABRT_SLVRD_INTX, bool &ABRT_USER_ABRT,
uint16_t &TX_FLUSH_CNT) volatile
{
uint32_t curr = IC_TX_ABRT_SOURCE;
ABRT_7B_ADDR_NOACK = curr & (1u << 0u);
ABRT_10ADDR1_NOACK = curr & (1u << 1u);
ABRT_10ADDR2_NOACK = curr & (1u << 2u);
ABRT_TXDATA_NOACK = curr & (1u << 3u);
ABRT_GCALL_NOACK = curr & (1u << 4u);
ABRT_GCALL_READ = curr & (1u << 5u);
ABRT_HS_ACKDET = curr & (1u << 6u);
ABRT_SBYTE_ACKDET = curr & (1u << 7u);
ABRT_HS_NORSTRT = curr & (1u << 8u);
ABRT_SBYTE_NORSTRT = curr & (1u << 9u);
ABRT_10B_RD_NORSTRT = curr & (1u << 10u);
ABRT_MASTER_DIS = curr & (1u << 11u);
ARB_LOST = curr & (1u << 12u);
ABRT_SLVFLUSH_TXFIFO = curr & (1u << 13u);
ABRT_SLV_ARBLOST = curr & (1u << 14u);
ABRT_SLVRD_INTX = curr & (1u << 15u);
ABRT_USER_ABRT = curr & (1u << 16u);
TX_FLUSH_CNT = (curr >> 23u) & 0b111111111u;
}
inline bool get_IC_SLV_DATA_NACK_ONLY_NACK() volatile
{
return IC_SLV_DATA_NACK_ONLY & (1u << 0u);
}
inline void set_IC_SLV_DATA_NACK_ONLY_NACK() volatile
{
IC_SLV_DATA_NACK_ONLY |= 1u << 0u;
}
inline void clear_IC_SLV_DATA_NACK_ONLY_NACK() volatile
{
IC_SLV_DATA_NACK_ONLY &= ~(1u << 0u);
}
inline void toggle_IC_SLV_DATA_NACK_ONLY_NACK() volatile
{
IC_SLV_DATA_NACK_ONLY ^= 1u << 0u;
}
inline bool get_IC_DMA_CR_RDMAE() volatile
{
return IC_DMA_CR & (1u << 0u);
}
inline void set_IC_DMA_CR_RDMAE() volatile
{
IC_DMA_CR |= 1u << 0u;
}
inline void clear_IC_DMA_CR_RDMAE() volatile
{
IC_DMA_CR &= ~(1u << 0u);
}
inline void toggle_IC_DMA_CR_RDMAE() volatile
{
IC_DMA_CR ^= 1u << 0u;
}
inline bool get_IC_DMA_CR_TDMAE() volatile
{
return IC_DMA_CR & (1u << 1u);
}
inline void set_IC_DMA_CR_TDMAE() volatile
{
IC_DMA_CR |= 1u << 1u;
}
inline void clear_IC_DMA_CR_TDMAE() volatile
{
IC_DMA_CR &= ~(1u << 1u);
}
inline void toggle_IC_DMA_CR_TDMAE() volatile
{
IC_DMA_CR ^= 1u << 1u;
}
inline void get_IC_DMA_CR(bool &RDMAE, bool &TDMAE) volatile
{
uint32_t curr = IC_DMA_CR;
RDMAE = curr & (1u << 0u);
TDMAE = curr & (1u << 1u);
}
inline void set_IC_DMA_CR(bool RDMAE, bool TDMAE) volatile
{
uint32_t curr = IC_DMA_CR;
curr &= ~(0b1u << 0u);
curr |= (RDMAE & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (TDMAE & 0b1u) << 1u;
IC_DMA_CR = curr;
}
inline uint8_t get_IC_DMA_TDLR_DMATDL() volatile
{
return (IC_DMA_TDLR >> 0u) & 0b1111u;
}
inline void set_IC_DMA_TDLR_DMATDL(uint8_t value) volatile
{
uint32_t curr = IC_DMA_TDLR;
curr &= ~(0b1111u << 0u);
curr |= (value & 0b1111u) << 0u;
IC_DMA_TDLR = curr;
}
inline uint8_t get_IC_DMA_RDLR_DMARDL() volatile
{
return (IC_DMA_RDLR >> 0u) & 0b1111u;
}
inline void set_IC_DMA_RDLR_DMARDL(uint8_t value) volatile
{
uint32_t curr = IC_DMA_RDLR;
curr &= ~(0b1111u << 0u);
curr |= (value & 0b1111u) << 0u;
IC_DMA_RDLR = curr;
}
inline uint8_t get_IC_SDA_SETUP_SDA_SETUP() volatile
{
return (IC_SDA_SETUP >> 0u) & 0b11111111u;
}
inline void set_IC_SDA_SETUP_SDA_SETUP(uint8_t value) volatile
{
uint32_t curr = IC_SDA_SETUP;
curr &= ~(0b11111111u << 0u);
curr |= (value & 0b11111111u) << 0u;
IC_SDA_SETUP = curr;
}
inline bool get_IC_ACK_GENERAL_CALL_ACK_GEN_CALL() volatile
{
return IC_ACK_GENERAL_CALL & (1u << 0u);
}
inline void set_IC_ACK_GENERAL_CALL_ACK_GEN_CALL() volatile
{
IC_ACK_GENERAL_CALL |= 1u << 0u;
}
inline void clear_IC_ACK_GENERAL_CALL_ACK_GEN_CALL() volatile
{
IC_ACK_GENERAL_CALL &= ~(1u << 0u);
}
inline void toggle_IC_ACK_GENERAL_CALL_ACK_GEN_CALL() volatile
{
IC_ACK_GENERAL_CALL ^= 1u << 0u;
}
inline bool get_IC_ENABLE_STATUS_IC_EN() volatile
{
return IC_ENABLE_STATUS & (1u << 0u);
}
inline bool get_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY() volatile
{
return IC_ENABLE_STATUS & (1u << 1u);
}
inline bool get_IC_ENABLE_STATUS_SLV_RX_DATA_LOST() volatile
{
return IC_ENABLE_STATUS & (1u << 2u);
}
inline void get_IC_ENABLE_STATUS(bool &IC_EN,
bool &SLV_DISABLED_WHILE_BUSY,
bool &SLV_RX_DATA_LOST) volatile
{
uint32_t curr = IC_ENABLE_STATUS;
IC_EN = curr & (1u << 0u);
SLV_DISABLED_WHILE_BUSY = curr & (1u << 1u);
SLV_RX_DATA_LOST = curr & (1u << 2u);
}
inline uint8_t get_IC_FS_SPKLEN_IC_FS_SPKLEN() volatile
{
return (IC_FS_SPKLEN >> 0u) & 0b11111111u;
}
inline void set_IC_FS_SPKLEN_IC_FS_SPKLEN(uint8_t value) volatile
{
uint32_t curr = IC_FS_SPKLEN;
curr &= ~(0b11111111u << 0u);
curr |= (value & 0b11111111u) << 0u;
IC_FS_SPKLEN = curr;
}
inline bool get_IC_CLR_RESTART_DET_CLR_RESTART_DET() volatile
{
return IC_CLR_RESTART_DET & (1u << 0u);
}
inline uint8_t get_IC_COMP_PARAM_1_APB_DATA_WIDTH() volatile
{
return (IC_COMP_PARAM_1 >> 0u) & 0b11u;
}
inline uint8_t get_IC_COMP_PARAM_1_MAX_SPEED_MODE() volatile
{
return (IC_COMP_PARAM_1 >> 2u) & 0b11u;
}
inline bool get_IC_COMP_PARAM_1_HC_COUNT_VALUES() volatile
{
return IC_COMP_PARAM_1 & (1u << 4u);
}
inline bool get_IC_COMP_PARAM_1_INTR_IO() volatile
{
return IC_COMP_PARAM_1 & (1u << 5u);
}
inline bool get_IC_COMP_PARAM_1_HAS_DMA() volatile
{
return IC_COMP_PARAM_1 & (1u << 6u);
}
inline bool get_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS() volatile
{
return IC_COMP_PARAM_1 & (1u << 7u);
}
inline uint8_t get_IC_COMP_PARAM_1_RX_BUFFER_DEPTH() volatile
{
return (IC_COMP_PARAM_1 >> 8u) & 0b11111111u;
}
inline uint8_t get_IC_COMP_PARAM_1_TX_BUFFER_DEPTH() volatile
{
return (IC_COMP_PARAM_1 >> 16u) & 0b11111111u;
}
inline void get_IC_COMP_PARAM_1(uint8_t &APB_DATA_WIDTH,
uint8_t &MAX_SPEED_MODE,
bool &HC_COUNT_VALUES, bool &INTR_IO,
bool &HAS_DMA, bool &ADD_ENCODED_PARAMS,
uint8_t &RX_BUFFER_DEPTH,
uint8_t &TX_BUFFER_DEPTH) volatile
{
uint32_t curr = IC_COMP_PARAM_1;
APB_DATA_WIDTH = (curr >> 0u) & 0b11u;
MAX_SPEED_MODE = (curr >> 2u) & 0b11u;
HC_COUNT_VALUES = curr & (1u << 4u);
INTR_IO = curr & (1u << 5u);
HAS_DMA = curr & (1u << 6u);
ADD_ENCODED_PARAMS = curr & (1u << 7u);
RX_BUFFER_DEPTH = (curr >> 8u) & 0b11111111u;
TX_BUFFER_DEPTH = (curr >> 16u) & 0b11111111u;
}
inline uint32_t get_IC_COMP_VERSION_IC_COMP_VERSION() volatile
{
return (IC_COMP_VERSION >> 0u) & 0b11111111111111111111111111111111u;
}
inline uint32_t get_IC_COMP_TYPE_IC_COMP_TYPE() volatile
{
return (IC_COMP_TYPE >> 0u) & 0b11111111111111111111111111111111u;
}
};
static_assert(sizeof(i2c0) == i2c0::size);
static volatile i2c0 *const I2C0 = reinterpret_cast<i2c0 *>(0x40044000);
static volatile i2c0 *const I2C1 = reinterpret_cast<i2c0 *>(0x40048000);
}; // namespace RP2040