Program Listing for File dma.h#
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#pragma once
#include "../enums/DMA_CH0_CTRL_TRIG_DATA_SIZE.h"
#include "../enums/DMA_CH0_CTRL_TRIG_RING_SIZE.h"
#include "../enums/DMA_CH0_CTRL_TRIG_TREQ_SEL.h"
#include "../enums/DMA_CH10_CTRL_TRIG_DATA_SIZE.h"
#include "../enums/DMA_CH10_CTRL_TRIG_RING_SIZE.h"
#include "../enums/DMA_CH10_CTRL_TRIG_TREQ_SEL.h"
#include "../enums/DMA_CH11_CTRL_TRIG_DATA_SIZE.h"
#include "../enums/DMA_CH11_CTRL_TRIG_RING_SIZE.h"
#include "../enums/DMA_CH11_CTRL_TRIG_TREQ_SEL.h"
#include "../enums/DMA_CH1_CTRL_TRIG_DATA_SIZE.h"
#include "../enums/DMA_CH1_CTRL_TRIG_RING_SIZE.h"
#include "../enums/DMA_CH1_CTRL_TRIG_TREQ_SEL.h"
#include "../enums/DMA_CH2_CTRL_TRIG_DATA_SIZE.h"
#include "../enums/DMA_CH2_CTRL_TRIG_RING_SIZE.h"
#include "../enums/DMA_CH2_CTRL_TRIG_TREQ_SEL.h"
#include "../enums/DMA_CH3_CTRL_TRIG_DATA_SIZE.h"
#include "../enums/DMA_CH3_CTRL_TRIG_RING_SIZE.h"
#include "../enums/DMA_CH3_CTRL_TRIG_TREQ_SEL.h"
#include "../enums/DMA_CH4_CTRL_TRIG_DATA_SIZE.h"
#include "../enums/DMA_CH4_CTRL_TRIG_RING_SIZE.h"
#include "../enums/DMA_CH4_CTRL_TRIG_TREQ_SEL.h"
#include "../enums/DMA_CH5_CTRL_TRIG_DATA_SIZE.h"
#include "../enums/DMA_CH5_CTRL_TRIG_RING_SIZE.h"
#include "../enums/DMA_CH5_CTRL_TRIG_TREQ_SEL.h"
#include "../enums/DMA_CH6_CTRL_TRIG_DATA_SIZE.h"
#include "../enums/DMA_CH6_CTRL_TRIG_RING_SIZE.h"
#include "../enums/DMA_CH6_CTRL_TRIG_TREQ_SEL.h"
#include "../enums/DMA_CH7_CTRL_TRIG_DATA_SIZE.h"
#include "../enums/DMA_CH7_CTRL_TRIG_RING_SIZE.h"
#include "../enums/DMA_CH7_CTRL_TRIG_TREQ_SEL.h"
#include "../enums/DMA_CH8_CTRL_TRIG_DATA_SIZE.h"
#include "../enums/DMA_CH8_CTRL_TRIG_RING_SIZE.h"
#include "../enums/DMA_CH8_CTRL_TRIG_TREQ_SEL.h"
#include "../enums/DMA_CH9_CTRL_TRIG_DATA_SIZE.h"
#include "../enums/DMA_CH9_CTRL_TRIG_RING_SIZE.h"
#include "../enums/DMA_CH9_CTRL_TRIG_TREQ_SEL.h"
#include "../enums/DMA_SNIFF_CTRL_CALC.h"
#include "../ifgen/common.h"
namespace RP2040
{
struct [[gnu::packed]] dma
{
/* Constant attributes. */
static constexpr std::size_t size = 2760;
/* Fields. */
uint32_t CH0_READ_ADDR;
uint32_t CH0_WRITE_ADDR;
uint32_t CH0_TRANS_COUNT;
uint32_t
CH0_CTRL_TRIG;
uint32_t
CH0_AL1_CTRL;
uint32_t CH0_AL1_READ_ADDR;
uint32_t CH0_AL1_WRITE_ADDR;
uint32_t CH0_AL1_TRANS_COUNT_TRIG;
uint32_t
CH0_AL2_CTRL;
uint32_t CH0_AL2_TRANS_COUNT;
uint32_t CH0_AL2_READ_ADDR;
uint32_t CH0_AL2_WRITE_ADDR_TRIG;
uint32_t
CH0_AL3_CTRL;
uint32_t CH0_AL3_WRITE_ADDR;
uint32_t CH0_AL3_TRANS_COUNT;
uint32_t CH0_AL3_READ_ADDR_TRIG;
uint32_t CH1_READ_ADDR;
uint32_t CH1_WRITE_ADDR;
uint32_t CH1_TRANS_COUNT;
uint32_t
CH1_CTRL_TRIG;
uint32_t
CH1_AL1_CTRL;
uint32_t CH1_AL1_READ_ADDR;
uint32_t CH1_AL1_WRITE_ADDR;
uint32_t CH1_AL1_TRANS_COUNT_TRIG;
uint32_t
CH1_AL2_CTRL;
uint32_t CH1_AL2_TRANS_COUNT;
uint32_t CH1_AL2_READ_ADDR;
uint32_t CH1_AL2_WRITE_ADDR_TRIG;
uint32_t
CH1_AL3_CTRL;
uint32_t CH1_AL3_WRITE_ADDR;
uint32_t CH1_AL3_TRANS_COUNT;
uint32_t CH1_AL3_READ_ADDR_TRIG;
uint32_t CH2_READ_ADDR;
uint32_t CH2_WRITE_ADDR;
uint32_t CH2_TRANS_COUNT;
uint32_t
CH2_CTRL_TRIG;
uint32_t
CH2_AL1_CTRL;
uint32_t CH2_AL1_READ_ADDR;
uint32_t CH2_AL1_WRITE_ADDR;
uint32_t CH2_AL1_TRANS_COUNT_TRIG;
uint32_t
CH2_AL2_CTRL;
uint32_t CH2_AL2_TRANS_COUNT;
uint32_t CH2_AL2_READ_ADDR;
uint32_t CH2_AL2_WRITE_ADDR_TRIG;
uint32_t
CH2_AL3_CTRL;
uint32_t CH2_AL3_WRITE_ADDR;
uint32_t CH2_AL3_TRANS_COUNT;
uint32_t CH2_AL3_READ_ADDR_TRIG;
uint32_t CH3_READ_ADDR;
uint32_t CH3_WRITE_ADDR;
uint32_t CH3_TRANS_COUNT;
uint32_t
CH3_CTRL_TRIG;
uint32_t
CH3_AL1_CTRL;
uint32_t CH3_AL1_READ_ADDR;
uint32_t CH3_AL1_WRITE_ADDR;
uint32_t CH3_AL1_TRANS_COUNT_TRIG;
uint32_t
CH3_AL2_CTRL;
uint32_t CH3_AL2_TRANS_COUNT;
uint32_t CH3_AL2_READ_ADDR;
uint32_t CH3_AL2_WRITE_ADDR_TRIG;
uint32_t
CH3_AL3_CTRL;
uint32_t CH3_AL3_WRITE_ADDR;
uint32_t CH3_AL3_TRANS_COUNT;
uint32_t CH3_AL3_READ_ADDR_TRIG;
uint32_t CH4_READ_ADDR;
uint32_t CH4_WRITE_ADDR;
uint32_t CH4_TRANS_COUNT;
uint32_t
CH4_CTRL_TRIG;
uint32_t
CH4_AL1_CTRL;
uint32_t CH4_AL1_READ_ADDR;
uint32_t CH4_AL1_WRITE_ADDR;
uint32_t CH4_AL1_TRANS_COUNT_TRIG;
uint32_t
CH4_AL2_CTRL;
uint32_t CH4_AL2_TRANS_COUNT;
uint32_t CH4_AL2_READ_ADDR;
uint32_t CH4_AL2_WRITE_ADDR_TRIG;
uint32_t
CH4_AL3_CTRL;
uint32_t CH4_AL3_WRITE_ADDR;
uint32_t CH4_AL3_TRANS_COUNT;
uint32_t CH4_AL3_READ_ADDR_TRIG;
uint32_t CH5_READ_ADDR;
uint32_t CH5_WRITE_ADDR;
uint32_t CH5_TRANS_COUNT;
uint32_t
CH5_CTRL_TRIG;
uint32_t
CH5_AL1_CTRL;
uint32_t CH5_AL1_READ_ADDR;
uint32_t CH5_AL1_WRITE_ADDR;
uint32_t CH5_AL1_TRANS_COUNT_TRIG;
uint32_t
CH5_AL2_CTRL;
uint32_t CH5_AL2_TRANS_COUNT;
uint32_t CH5_AL2_READ_ADDR;
uint32_t CH5_AL2_WRITE_ADDR_TRIG;
uint32_t
CH5_AL3_CTRL;
uint32_t CH5_AL3_WRITE_ADDR;
uint32_t CH5_AL3_TRANS_COUNT;
uint32_t CH5_AL3_READ_ADDR_TRIG;
uint32_t CH6_READ_ADDR;
uint32_t CH6_WRITE_ADDR;
uint32_t CH6_TRANS_COUNT;
uint32_t
CH6_CTRL_TRIG;
uint32_t
CH6_AL1_CTRL;
uint32_t CH6_AL1_READ_ADDR;
uint32_t CH6_AL1_WRITE_ADDR;
uint32_t CH6_AL1_TRANS_COUNT_TRIG;
uint32_t
CH6_AL2_CTRL;
uint32_t CH6_AL2_TRANS_COUNT;
uint32_t CH6_AL2_READ_ADDR;
uint32_t CH6_AL2_WRITE_ADDR_TRIG;
uint32_t
CH6_AL3_CTRL;
uint32_t CH6_AL3_WRITE_ADDR;
uint32_t CH6_AL3_TRANS_COUNT;
uint32_t CH6_AL3_READ_ADDR_TRIG;
uint32_t CH7_READ_ADDR;
uint32_t CH7_WRITE_ADDR;
uint32_t CH7_TRANS_COUNT;
uint32_t
CH7_CTRL_TRIG;
uint32_t
CH7_AL1_CTRL;
uint32_t CH7_AL1_READ_ADDR;
uint32_t CH7_AL1_WRITE_ADDR;
uint32_t CH7_AL1_TRANS_COUNT_TRIG;
uint32_t
CH7_AL2_CTRL;
uint32_t CH7_AL2_TRANS_COUNT;
uint32_t CH7_AL2_READ_ADDR;
uint32_t CH7_AL2_WRITE_ADDR_TRIG;
uint32_t
CH7_AL3_CTRL;
uint32_t CH7_AL3_WRITE_ADDR;
uint32_t CH7_AL3_TRANS_COUNT;
uint32_t CH7_AL3_READ_ADDR_TRIG;
uint32_t CH8_READ_ADDR;
uint32_t CH8_WRITE_ADDR;
uint32_t CH8_TRANS_COUNT;
uint32_t
CH8_CTRL_TRIG;
uint32_t
CH8_AL1_CTRL;
uint32_t CH8_AL1_READ_ADDR;
uint32_t CH8_AL1_WRITE_ADDR;
uint32_t CH8_AL1_TRANS_COUNT_TRIG;
uint32_t
CH8_AL2_CTRL;
uint32_t CH8_AL2_TRANS_COUNT;
uint32_t CH8_AL2_READ_ADDR;
uint32_t CH8_AL2_WRITE_ADDR_TRIG;
uint32_t
CH8_AL3_CTRL;
uint32_t CH8_AL3_WRITE_ADDR;
uint32_t CH8_AL3_TRANS_COUNT;
uint32_t CH8_AL3_READ_ADDR_TRIG;
uint32_t CH9_READ_ADDR;
uint32_t CH9_WRITE_ADDR;
uint32_t CH9_TRANS_COUNT;
uint32_t
CH9_CTRL_TRIG;
uint32_t
CH9_AL1_CTRL;
uint32_t CH9_AL1_READ_ADDR;
uint32_t CH9_AL1_WRITE_ADDR;
uint32_t CH9_AL1_TRANS_COUNT_TRIG;
uint32_t
CH9_AL2_CTRL;
uint32_t CH9_AL2_TRANS_COUNT;
uint32_t CH9_AL2_READ_ADDR;
uint32_t CH9_AL2_WRITE_ADDR_TRIG;
uint32_t
CH9_AL3_CTRL;
uint32_t CH9_AL3_WRITE_ADDR;
uint32_t CH9_AL3_TRANS_COUNT;
uint32_t CH9_AL3_READ_ADDR_TRIG;
uint32_t CH10_READ_ADDR;
uint32_t CH10_WRITE_ADDR;
uint32_t CH10_TRANS_COUNT;
uint32_t
CH10_CTRL_TRIG;
uint32_t
CH10_AL1_CTRL;
uint32_t CH10_AL1_READ_ADDR;
uint32_t CH10_AL1_WRITE_ADDR;
uint32_t CH10_AL1_TRANS_COUNT_TRIG;
uint32_t
CH10_AL2_CTRL;
uint32_t CH10_AL2_TRANS_COUNT;
uint32_t CH10_AL2_READ_ADDR;
uint32_t CH10_AL2_WRITE_ADDR_TRIG;
uint32_t
CH10_AL3_CTRL;
uint32_t CH10_AL3_WRITE_ADDR;
uint32_t CH10_AL3_TRANS_COUNT;
uint32_t CH10_AL3_READ_ADDR_TRIG;
uint32_t CH11_READ_ADDR;
uint32_t CH11_WRITE_ADDR;
uint32_t CH11_TRANS_COUNT;
uint32_t
CH11_CTRL_TRIG;
uint32_t
CH11_AL1_CTRL;
uint32_t CH11_AL1_READ_ADDR;
uint32_t CH11_AL1_WRITE_ADDR;
uint32_t CH11_AL1_TRANS_COUNT_TRIG;
uint32_t
CH11_AL2_CTRL;
uint32_t CH11_AL2_TRANS_COUNT;
uint32_t CH11_AL2_READ_ADDR;
uint32_t CH11_AL2_WRITE_ADDR_TRIG;
uint32_t
CH11_AL3_CTRL;
uint32_t CH11_AL3_WRITE_ADDR;
uint32_t CH11_AL3_TRANS_COUNT;
uint32_t CH11_AL3_READ_ADDR_TRIG;
static constexpr std::size_t reserved_padding0_length = 64;
const uint32_t reserved_padding0[reserved_padding0_length] = {};
uint32_t INTR;
uint32_t INTE0;
uint32_t INTF0;
uint32_t INTS0;
const uint32_t reserved_padding1 = {};
uint32_t INTE1;
uint32_t INTF1;
uint32_t INTS1;
uint32_t TIMER0;
uint32_t TIMER1;
uint32_t TIMER2;
uint32_t TIMER3;
uint32_t MULTI_CHAN_TRIGGER;
uint32_t SNIFF_CTRL;
uint32_t SNIFF_DATA;
const uint32_t reserved_padding2 = {};
const uint32_t FIFO_LEVELS =
{};
uint32_t CHAN_ABORT;
const uint32_t N_CHANNELS =
{};
static constexpr std::size_t reserved_padding3_length = 237;
const uint32_t reserved_padding3[reserved_padding3_length] = {};
uint32_t
CH0_DBG_CTDREQ;
uint32_t
CH0_DBG_TCR;
static constexpr std::size_t reserved_padding4_length = 14;
const uint32_t reserved_padding4[reserved_padding4_length] = {};
uint32_t
CH1_DBG_CTDREQ;
uint32_t
CH1_DBG_TCR;
static constexpr std::size_t reserved_padding5_length = 14;
const uint32_t reserved_padding5[reserved_padding5_length] = {};
uint32_t
CH2_DBG_CTDREQ;
uint32_t
CH2_DBG_TCR;
static constexpr std::size_t reserved_padding6_length = 14;
const uint32_t reserved_padding6[reserved_padding6_length] = {};
uint32_t
CH3_DBG_CTDREQ;
uint32_t
CH3_DBG_TCR;
static constexpr std::size_t reserved_padding7_length = 14;
const uint32_t reserved_padding7[reserved_padding7_length] = {};
uint32_t
CH4_DBG_CTDREQ;
uint32_t
CH4_DBG_TCR;
static constexpr std::size_t reserved_padding8_length = 14;
const uint32_t reserved_padding8[reserved_padding8_length] = {};
uint32_t
CH5_DBG_CTDREQ;
uint32_t
CH5_DBG_TCR;
static constexpr std::size_t reserved_padding9_length = 14;
const uint32_t reserved_padding9[reserved_padding9_length] = {};
uint32_t
CH6_DBG_CTDREQ;
uint32_t
CH6_DBG_TCR;
static constexpr std::size_t reserved_padding10_length = 14;
const uint32_t reserved_padding10[reserved_padding10_length] = {};
uint32_t
CH7_DBG_CTDREQ;
uint32_t
CH7_DBG_TCR;
static constexpr std::size_t reserved_padding11_length = 14;
const uint32_t reserved_padding11[reserved_padding11_length] = {};
uint32_t
CH8_DBG_CTDREQ;
uint32_t
CH8_DBG_TCR;
static constexpr std::size_t reserved_padding12_length = 14;
const uint32_t reserved_padding12[reserved_padding12_length] = {};
uint32_t
CH9_DBG_CTDREQ;
uint32_t
CH9_DBG_TCR;
static constexpr std::size_t reserved_padding13_length = 14;
const uint32_t reserved_padding13[reserved_padding13_length] = {};
uint32_t
CH10_DBG_CTDREQ;
uint32_t
CH10_DBG_TCR;
static constexpr std::size_t reserved_padding14_length = 14;
const uint32_t reserved_padding14[reserved_padding14_length] = {};
uint32_t
CH11_DBG_CTDREQ;
uint32_t
CH11_DBG_TCR;
/* Methods. */
inline bool get_CH0_CTRL_TRIG_EN() volatile
{
return CH0_CTRL_TRIG & (1u << 0u);
}
inline void set_CH0_CTRL_TRIG_EN() volatile
{
CH0_CTRL_TRIG |= 1u << 0u;
}
inline void clear_CH0_CTRL_TRIG_EN() volatile
{
CH0_CTRL_TRIG &= ~(1u << 0u);
}
inline void toggle_CH0_CTRL_TRIG_EN() volatile
{
CH0_CTRL_TRIG ^= 1u << 0u;
}
inline bool get_CH0_CTRL_TRIG_HIGH_PRIORITY() volatile
{
return CH0_CTRL_TRIG & (1u << 1u);
}
inline void set_CH0_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH0_CTRL_TRIG |= 1u << 1u;
}
inline void clear_CH0_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH0_CTRL_TRIG &= ~(1u << 1u);
}
inline void toggle_CH0_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH0_CTRL_TRIG ^= 1u << 1u;
}
inline DMA_CH0_CTRL_TRIG_DATA_SIZE get_CH0_CTRL_TRIG_DATA_SIZE() volatile
{
return DMA_CH0_CTRL_TRIG_DATA_SIZE((CH0_CTRL_TRIG >> 2u) & 0b11u);
}
inline void set_CH0_CTRL_TRIG_DATA_SIZE(
DMA_CH0_CTRL_TRIG_DATA_SIZE value) volatile
{
uint32_t curr = CH0_CTRL_TRIG;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(value) & 0b11u) << 2u;
CH0_CTRL_TRIG = curr;
}
inline bool get_CH0_CTRL_TRIG_INCR_READ() volatile
{
return CH0_CTRL_TRIG & (1u << 4u);
}
inline void set_CH0_CTRL_TRIG_INCR_READ() volatile
{
CH0_CTRL_TRIG |= 1u << 4u;
}
inline void clear_CH0_CTRL_TRIG_INCR_READ() volatile
{
CH0_CTRL_TRIG &= ~(1u << 4u);
}
inline void toggle_CH0_CTRL_TRIG_INCR_READ() volatile
{
CH0_CTRL_TRIG ^= 1u << 4u;
}
inline bool get_CH0_CTRL_TRIG_INCR_WRITE() volatile
{
return CH0_CTRL_TRIG & (1u << 5u);
}
inline void set_CH0_CTRL_TRIG_INCR_WRITE() volatile
{
CH0_CTRL_TRIG |= 1u << 5u;
}
inline void clear_CH0_CTRL_TRIG_INCR_WRITE() volatile
{
CH0_CTRL_TRIG &= ~(1u << 5u);
}
inline void toggle_CH0_CTRL_TRIG_INCR_WRITE() volatile
{
CH0_CTRL_TRIG ^= 1u << 5u;
}
inline DMA_CH0_CTRL_TRIG_RING_SIZE get_CH0_CTRL_TRIG_RING_SIZE() volatile
{
return DMA_CH0_CTRL_TRIG_RING_SIZE((CH0_CTRL_TRIG >> 6u) & 0b1111u);
}
inline void set_CH0_CTRL_TRIG_RING_SIZE(
DMA_CH0_CTRL_TRIG_RING_SIZE value) volatile
{
uint32_t curr = CH0_CTRL_TRIG;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(value) & 0b1111u) << 6u;
CH0_CTRL_TRIG = curr;
}
inline bool get_CH0_CTRL_TRIG_RING_SEL() volatile
{
return CH0_CTRL_TRIG & (1u << 10u);
}
inline void set_CH0_CTRL_TRIG_RING_SEL() volatile
{
CH0_CTRL_TRIG |= 1u << 10u;
}
inline void clear_CH0_CTRL_TRIG_RING_SEL() volatile
{
CH0_CTRL_TRIG &= ~(1u << 10u);
}
inline void toggle_CH0_CTRL_TRIG_RING_SEL() volatile
{
CH0_CTRL_TRIG ^= 1u << 10u;
}
inline uint8_t get_CH0_CTRL_TRIG_CHAIN_TO() volatile
{
return (CH0_CTRL_TRIG >> 11u) & 0b1111u;
}
inline void set_CH0_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile
{
uint32_t curr = CH0_CTRL_TRIG;
curr &= ~(0b1111u << 11u);
curr |= (value & 0b1111u) << 11u;
CH0_CTRL_TRIG = curr;
}
inline DMA_CH0_CTRL_TRIG_TREQ_SEL get_CH0_CTRL_TRIG_TREQ_SEL() volatile
{
return DMA_CH0_CTRL_TRIG_TREQ_SEL((CH0_CTRL_TRIG >> 15u) & 0b111111u);
}
inline void set_CH0_CTRL_TRIG_TREQ_SEL(
DMA_CH0_CTRL_TRIG_TREQ_SEL value) volatile
{
uint32_t curr = CH0_CTRL_TRIG;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(value) & 0b111111u) << 15u;
CH0_CTRL_TRIG = curr;
}
inline bool get_CH0_CTRL_TRIG_IRQ_QUIET() volatile
{
return CH0_CTRL_TRIG & (1u << 21u);
}
inline void set_CH0_CTRL_TRIG_IRQ_QUIET() volatile
{
CH0_CTRL_TRIG |= 1u << 21u;
}
inline void clear_CH0_CTRL_TRIG_IRQ_QUIET() volatile
{
CH0_CTRL_TRIG &= ~(1u << 21u);
}
inline void toggle_CH0_CTRL_TRIG_IRQ_QUIET() volatile
{
CH0_CTRL_TRIG ^= 1u << 21u;
}
inline bool get_CH0_CTRL_TRIG_BSWAP() volatile
{
return CH0_CTRL_TRIG & (1u << 22u);
}
inline void set_CH0_CTRL_TRIG_BSWAP() volatile
{
CH0_CTRL_TRIG |= 1u << 22u;
}
inline void clear_CH0_CTRL_TRIG_BSWAP() volatile
{
CH0_CTRL_TRIG &= ~(1u << 22u);
}
inline void toggle_CH0_CTRL_TRIG_BSWAP() volatile
{
CH0_CTRL_TRIG ^= 1u << 22u;
}
inline bool get_CH0_CTRL_TRIG_SNIFF_EN() volatile
{
return CH0_CTRL_TRIG & (1u << 23u);
}
inline void set_CH0_CTRL_TRIG_SNIFF_EN() volatile
{
CH0_CTRL_TRIG |= 1u << 23u;
}
inline void clear_CH0_CTRL_TRIG_SNIFF_EN() volatile
{
CH0_CTRL_TRIG &= ~(1u << 23u);
}
inline void toggle_CH0_CTRL_TRIG_SNIFF_EN() volatile
{
CH0_CTRL_TRIG ^= 1u << 23u;
}
inline bool get_CH0_CTRL_TRIG_BUSY() volatile
{
return CH0_CTRL_TRIG & (1u << 24u);
}
inline bool get_CH0_CTRL_TRIG_WRITE_ERROR() volatile
{
return CH0_CTRL_TRIG & (1u << 29u);
}
inline void set_CH0_CTRL_TRIG_WRITE_ERROR() volatile
{
CH0_CTRL_TRIG |= 1u << 29u;
}
inline void clear_CH0_CTRL_TRIG_WRITE_ERROR() volatile
{
CH0_CTRL_TRIG &= ~(1u << 29u);
}
inline void toggle_CH0_CTRL_TRIG_WRITE_ERROR() volatile
{
CH0_CTRL_TRIG ^= 1u << 29u;
}
inline bool get_CH0_CTRL_TRIG_READ_ERROR() volatile
{
return CH0_CTRL_TRIG & (1u << 30u);
}
inline void set_CH0_CTRL_TRIG_READ_ERROR() volatile
{
CH0_CTRL_TRIG |= 1u << 30u;
}
inline void clear_CH0_CTRL_TRIG_READ_ERROR() volatile
{
CH0_CTRL_TRIG &= ~(1u << 30u);
}
inline void toggle_CH0_CTRL_TRIG_READ_ERROR() volatile
{
CH0_CTRL_TRIG ^= 1u << 30u;
}
inline bool get_CH0_CTRL_TRIG_AHB_ERROR() volatile
{
return CH0_CTRL_TRIG & (1u << 31u);
}
inline void get_CH0_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY,
DMA_CH0_CTRL_TRIG_DATA_SIZE &DATA_SIZE,
bool &INCR_READ, bool &INCR_WRITE,
DMA_CH0_CTRL_TRIG_RING_SIZE &RING_SIZE,
bool &RING_SEL, uint8_t &CHAIN_TO,
DMA_CH0_CTRL_TRIG_TREQ_SEL &TREQ_SEL,
bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN,
bool &BUSY, bool &WRITE_ERROR,
bool &READ_ERROR, bool &AHB_ERROR) volatile
{
uint32_t curr = CH0_CTRL_TRIG;
EN = curr & (1u << 0u);
HIGH_PRIORITY = curr & (1u << 1u);
DATA_SIZE = DMA_CH0_CTRL_TRIG_DATA_SIZE((curr >> 2u) & 0b11u);
INCR_READ = curr & (1u << 4u);
INCR_WRITE = curr & (1u << 5u);
RING_SIZE = DMA_CH0_CTRL_TRIG_RING_SIZE((curr >> 6u) & 0b1111u);
RING_SEL = curr & (1u << 10u);
CHAIN_TO = (curr >> 11u) & 0b1111u;
TREQ_SEL = DMA_CH0_CTRL_TRIG_TREQ_SEL((curr >> 15u) & 0b111111u);
IRQ_QUIET = curr & (1u << 21u);
BSWAP = curr & (1u << 22u);
SNIFF_EN = curr & (1u << 23u);
BUSY = curr & (1u << 24u);
WRITE_ERROR = curr & (1u << 29u);
READ_ERROR = curr & (1u << 30u);
AHB_ERROR = curr & (1u << 31u);
}
inline void set_CH0_CTRL_TRIG(bool EN, bool HIGH_PRIORITY,
DMA_CH0_CTRL_TRIG_DATA_SIZE DATA_SIZE,
bool INCR_READ, bool INCR_WRITE,
DMA_CH0_CTRL_TRIG_RING_SIZE RING_SIZE,
bool RING_SEL, uint8_t CHAIN_TO,
DMA_CH0_CTRL_TRIG_TREQ_SEL TREQ_SEL,
bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN,
bool WRITE_ERROR, bool READ_ERROR) volatile
{
uint32_t curr = CH0_CTRL_TRIG;
curr &= ~(0b1u << 0u);
curr |= (EN & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (HIGH_PRIORITY & 0b1u) << 1u;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
curr &= ~(0b1u << 4u);
curr |= (INCR_READ & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (INCR_WRITE & 0b1u) << 5u;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(RING_SIZE) & 0b1111u) << 6u;
curr &= ~(0b1u << 10u);
curr |= (RING_SEL & 0b1u) << 10u;
curr &= ~(0b1111u << 11u);
curr |= (CHAIN_TO & 0b1111u) << 11u;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
curr &= ~(0b1u << 21u);
curr |= (IRQ_QUIET & 0b1u) << 21u;
curr &= ~(0b1u << 22u);
curr |= (BSWAP & 0b1u) << 22u;
curr &= ~(0b1u << 23u);
curr |= (SNIFF_EN & 0b1u) << 23u;
curr &= ~(0b1u << 29u);
curr |= (WRITE_ERROR & 0b1u) << 29u;
curr &= ~(0b1u << 30u);
curr |= (READ_ERROR & 0b1u) << 30u;
CH0_CTRL_TRIG = curr;
}
inline bool get_CH1_CTRL_TRIG_EN() volatile
{
return CH1_CTRL_TRIG & (1u << 0u);
}
inline void set_CH1_CTRL_TRIG_EN() volatile
{
CH1_CTRL_TRIG |= 1u << 0u;
}
inline void clear_CH1_CTRL_TRIG_EN() volatile
{
CH1_CTRL_TRIG &= ~(1u << 0u);
}
inline void toggle_CH1_CTRL_TRIG_EN() volatile
{
CH1_CTRL_TRIG ^= 1u << 0u;
}
inline bool get_CH1_CTRL_TRIG_HIGH_PRIORITY() volatile
{
return CH1_CTRL_TRIG & (1u << 1u);
}
inline void set_CH1_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH1_CTRL_TRIG |= 1u << 1u;
}
inline void clear_CH1_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH1_CTRL_TRIG &= ~(1u << 1u);
}
inline void toggle_CH1_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH1_CTRL_TRIG ^= 1u << 1u;
}
inline DMA_CH1_CTRL_TRIG_DATA_SIZE get_CH1_CTRL_TRIG_DATA_SIZE() volatile
{
return DMA_CH1_CTRL_TRIG_DATA_SIZE((CH1_CTRL_TRIG >> 2u) & 0b11u);
}
inline void set_CH1_CTRL_TRIG_DATA_SIZE(
DMA_CH1_CTRL_TRIG_DATA_SIZE value) volatile
{
uint32_t curr = CH1_CTRL_TRIG;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(value) & 0b11u) << 2u;
CH1_CTRL_TRIG = curr;
}
inline bool get_CH1_CTRL_TRIG_INCR_READ() volatile
{
return CH1_CTRL_TRIG & (1u << 4u);
}
inline void set_CH1_CTRL_TRIG_INCR_READ() volatile
{
CH1_CTRL_TRIG |= 1u << 4u;
}
inline void clear_CH1_CTRL_TRIG_INCR_READ() volatile
{
CH1_CTRL_TRIG &= ~(1u << 4u);
}
inline void toggle_CH1_CTRL_TRIG_INCR_READ() volatile
{
CH1_CTRL_TRIG ^= 1u << 4u;
}
inline bool get_CH1_CTRL_TRIG_INCR_WRITE() volatile
{
return CH1_CTRL_TRIG & (1u << 5u);
}
inline void set_CH1_CTRL_TRIG_INCR_WRITE() volatile
{
CH1_CTRL_TRIG |= 1u << 5u;
}
inline void clear_CH1_CTRL_TRIG_INCR_WRITE() volatile
{
CH1_CTRL_TRIG &= ~(1u << 5u);
}
inline void toggle_CH1_CTRL_TRIG_INCR_WRITE() volatile
{
CH1_CTRL_TRIG ^= 1u << 5u;
}
inline DMA_CH1_CTRL_TRIG_RING_SIZE get_CH1_CTRL_TRIG_RING_SIZE() volatile
{
return DMA_CH1_CTRL_TRIG_RING_SIZE((CH1_CTRL_TRIG >> 6u) & 0b1111u);
}
inline void set_CH1_CTRL_TRIG_RING_SIZE(
DMA_CH1_CTRL_TRIG_RING_SIZE value) volatile
{
uint32_t curr = CH1_CTRL_TRIG;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(value) & 0b1111u) << 6u;
CH1_CTRL_TRIG = curr;
}
inline bool get_CH1_CTRL_TRIG_RING_SEL() volatile
{
return CH1_CTRL_TRIG & (1u << 10u);
}
inline void set_CH1_CTRL_TRIG_RING_SEL() volatile
{
CH1_CTRL_TRIG |= 1u << 10u;
}
inline void clear_CH1_CTRL_TRIG_RING_SEL() volatile
{
CH1_CTRL_TRIG &= ~(1u << 10u);
}
inline void toggle_CH1_CTRL_TRIG_RING_SEL() volatile
{
CH1_CTRL_TRIG ^= 1u << 10u;
}
inline uint8_t get_CH1_CTRL_TRIG_CHAIN_TO() volatile
{
return (CH1_CTRL_TRIG >> 11u) & 0b1111u;
}
inline void set_CH1_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile
{
uint32_t curr = CH1_CTRL_TRIG;
curr &= ~(0b1111u << 11u);
curr |= (value & 0b1111u) << 11u;
CH1_CTRL_TRIG = curr;
}
inline DMA_CH1_CTRL_TRIG_TREQ_SEL get_CH1_CTRL_TRIG_TREQ_SEL() volatile
{
return DMA_CH1_CTRL_TRIG_TREQ_SEL((CH1_CTRL_TRIG >> 15u) & 0b111111u);
}
inline void set_CH1_CTRL_TRIG_TREQ_SEL(
DMA_CH1_CTRL_TRIG_TREQ_SEL value) volatile
{
uint32_t curr = CH1_CTRL_TRIG;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(value) & 0b111111u) << 15u;
CH1_CTRL_TRIG = curr;
}
inline bool get_CH1_CTRL_TRIG_IRQ_QUIET() volatile
{
return CH1_CTRL_TRIG & (1u << 21u);
}
inline void set_CH1_CTRL_TRIG_IRQ_QUIET() volatile
{
CH1_CTRL_TRIG |= 1u << 21u;
}
inline void clear_CH1_CTRL_TRIG_IRQ_QUIET() volatile
{
CH1_CTRL_TRIG &= ~(1u << 21u);
}
inline void toggle_CH1_CTRL_TRIG_IRQ_QUIET() volatile
{
CH1_CTRL_TRIG ^= 1u << 21u;
}
inline bool get_CH1_CTRL_TRIG_BSWAP() volatile
{
return CH1_CTRL_TRIG & (1u << 22u);
}
inline void set_CH1_CTRL_TRIG_BSWAP() volatile
{
CH1_CTRL_TRIG |= 1u << 22u;
}
inline void clear_CH1_CTRL_TRIG_BSWAP() volatile
{
CH1_CTRL_TRIG &= ~(1u << 22u);
}
inline void toggle_CH1_CTRL_TRIG_BSWAP() volatile
{
CH1_CTRL_TRIG ^= 1u << 22u;
}
inline bool get_CH1_CTRL_TRIG_SNIFF_EN() volatile
{
return CH1_CTRL_TRIG & (1u << 23u);
}
inline void set_CH1_CTRL_TRIG_SNIFF_EN() volatile
{
CH1_CTRL_TRIG |= 1u << 23u;
}
inline void clear_CH1_CTRL_TRIG_SNIFF_EN() volatile
{
CH1_CTRL_TRIG &= ~(1u << 23u);
}
inline void toggle_CH1_CTRL_TRIG_SNIFF_EN() volatile
{
CH1_CTRL_TRIG ^= 1u << 23u;
}
inline bool get_CH1_CTRL_TRIG_BUSY() volatile
{
return CH1_CTRL_TRIG & (1u << 24u);
}
inline bool get_CH1_CTRL_TRIG_WRITE_ERROR() volatile
{
return CH1_CTRL_TRIG & (1u << 29u);
}
inline void set_CH1_CTRL_TRIG_WRITE_ERROR() volatile
{
CH1_CTRL_TRIG |= 1u << 29u;
}
inline void clear_CH1_CTRL_TRIG_WRITE_ERROR() volatile
{
CH1_CTRL_TRIG &= ~(1u << 29u);
}
inline void toggle_CH1_CTRL_TRIG_WRITE_ERROR() volatile
{
CH1_CTRL_TRIG ^= 1u << 29u;
}
inline bool get_CH1_CTRL_TRIG_READ_ERROR() volatile
{
return CH1_CTRL_TRIG & (1u << 30u);
}
inline void set_CH1_CTRL_TRIG_READ_ERROR() volatile
{
CH1_CTRL_TRIG |= 1u << 30u;
}
inline void clear_CH1_CTRL_TRIG_READ_ERROR() volatile
{
CH1_CTRL_TRIG &= ~(1u << 30u);
}
inline void toggle_CH1_CTRL_TRIG_READ_ERROR() volatile
{
CH1_CTRL_TRIG ^= 1u << 30u;
}
inline bool get_CH1_CTRL_TRIG_AHB_ERROR() volatile
{
return CH1_CTRL_TRIG & (1u << 31u);
}
inline void get_CH1_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY,
DMA_CH1_CTRL_TRIG_DATA_SIZE &DATA_SIZE,
bool &INCR_READ, bool &INCR_WRITE,
DMA_CH1_CTRL_TRIG_RING_SIZE &RING_SIZE,
bool &RING_SEL, uint8_t &CHAIN_TO,
DMA_CH1_CTRL_TRIG_TREQ_SEL &TREQ_SEL,
bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN,
bool &BUSY, bool &WRITE_ERROR,
bool &READ_ERROR, bool &AHB_ERROR) volatile
{
uint32_t curr = CH1_CTRL_TRIG;
EN = curr & (1u << 0u);
HIGH_PRIORITY = curr & (1u << 1u);
DATA_SIZE = DMA_CH1_CTRL_TRIG_DATA_SIZE((curr >> 2u) & 0b11u);
INCR_READ = curr & (1u << 4u);
INCR_WRITE = curr & (1u << 5u);
RING_SIZE = DMA_CH1_CTRL_TRIG_RING_SIZE((curr >> 6u) & 0b1111u);
RING_SEL = curr & (1u << 10u);
CHAIN_TO = (curr >> 11u) & 0b1111u;
TREQ_SEL = DMA_CH1_CTRL_TRIG_TREQ_SEL((curr >> 15u) & 0b111111u);
IRQ_QUIET = curr & (1u << 21u);
BSWAP = curr & (1u << 22u);
SNIFF_EN = curr & (1u << 23u);
BUSY = curr & (1u << 24u);
WRITE_ERROR = curr & (1u << 29u);
READ_ERROR = curr & (1u << 30u);
AHB_ERROR = curr & (1u << 31u);
}
inline void set_CH1_CTRL_TRIG(bool EN, bool HIGH_PRIORITY,
DMA_CH1_CTRL_TRIG_DATA_SIZE DATA_SIZE,
bool INCR_READ, bool INCR_WRITE,
DMA_CH1_CTRL_TRIG_RING_SIZE RING_SIZE,
bool RING_SEL, uint8_t CHAIN_TO,
DMA_CH1_CTRL_TRIG_TREQ_SEL TREQ_SEL,
bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN,
bool WRITE_ERROR, bool READ_ERROR) volatile
{
uint32_t curr = CH1_CTRL_TRIG;
curr &= ~(0b1u << 0u);
curr |= (EN & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (HIGH_PRIORITY & 0b1u) << 1u;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
curr &= ~(0b1u << 4u);
curr |= (INCR_READ & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (INCR_WRITE & 0b1u) << 5u;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(RING_SIZE) & 0b1111u) << 6u;
curr &= ~(0b1u << 10u);
curr |= (RING_SEL & 0b1u) << 10u;
curr &= ~(0b1111u << 11u);
curr |= (CHAIN_TO & 0b1111u) << 11u;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
curr &= ~(0b1u << 21u);
curr |= (IRQ_QUIET & 0b1u) << 21u;
curr &= ~(0b1u << 22u);
curr |= (BSWAP & 0b1u) << 22u;
curr &= ~(0b1u << 23u);
curr |= (SNIFF_EN & 0b1u) << 23u;
curr &= ~(0b1u << 29u);
curr |= (WRITE_ERROR & 0b1u) << 29u;
curr &= ~(0b1u << 30u);
curr |= (READ_ERROR & 0b1u) << 30u;
CH1_CTRL_TRIG = curr;
}
inline bool get_CH2_CTRL_TRIG_EN() volatile
{
return CH2_CTRL_TRIG & (1u << 0u);
}
inline void set_CH2_CTRL_TRIG_EN() volatile
{
CH2_CTRL_TRIG |= 1u << 0u;
}
inline void clear_CH2_CTRL_TRIG_EN() volatile
{
CH2_CTRL_TRIG &= ~(1u << 0u);
}
inline void toggle_CH2_CTRL_TRIG_EN() volatile
{
CH2_CTRL_TRIG ^= 1u << 0u;
}
inline bool get_CH2_CTRL_TRIG_HIGH_PRIORITY() volatile
{
return CH2_CTRL_TRIG & (1u << 1u);
}
inline void set_CH2_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH2_CTRL_TRIG |= 1u << 1u;
}
inline void clear_CH2_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH2_CTRL_TRIG &= ~(1u << 1u);
}
inline void toggle_CH2_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH2_CTRL_TRIG ^= 1u << 1u;
}
inline DMA_CH2_CTRL_TRIG_DATA_SIZE get_CH2_CTRL_TRIG_DATA_SIZE() volatile
{
return DMA_CH2_CTRL_TRIG_DATA_SIZE((CH2_CTRL_TRIG >> 2u) & 0b11u);
}
inline void set_CH2_CTRL_TRIG_DATA_SIZE(
DMA_CH2_CTRL_TRIG_DATA_SIZE value) volatile
{
uint32_t curr = CH2_CTRL_TRIG;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(value) & 0b11u) << 2u;
CH2_CTRL_TRIG = curr;
}
inline bool get_CH2_CTRL_TRIG_INCR_READ() volatile
{
return CH2_CTRL_TRIG & (1u << 4u);
}
inline void set_CH2_CTRL_TRIG_INCR_READ() volatile
{
CH2_CTRL_TRIG |= 1u << 4u;
}
inline void clear_CH2_CTRL_TRIG_INCR_READ() volatile
{
CH2_CTRL_TRIG &= ~(1u << 4u);
}
inline void toggle_CH2_CTRL_TRIG_INCR_READ() volatile
{
CH2_CTRL_TRIG ^= 1u << 4u;
}
inline bool get_CH2_CTRL_TRIG_INCR_WRITE() volatile
{
return CH2_CTRL_TRIG & (1u << 5u);
}
inline void set_CH2_CTRL_TRIG_INCR_WRITE() volatile
{
CH2_CTRL_TRIG |= 1u << 5u;
}
inline void clear_CH2_CTRL_TRIG_INCR_WRITE() volatile
{
CH2_CTRL_TRIG &= ~(1u << 5u);
}
inline void toggle_CH2_CTRL_TRIG_INCR_WRITE() volatile
{
CH2_CTRL_TRIG ^= 1u << 5u;
}
inline DMA_CH2_CTRL_TRIG_RING_SIZE get_CH2_CTRL_TRIG_RING_SIZE() volatile
{
return DMA_CH2_CTRL_TRIG_RING_SIZE((CH2_CTRL_TRIG >> 6u) & 0b1111u);
}
inline void set_CH2_CTRL_TRIG_RING_SIZE(
DMA_CH2_CTRL_TRIG_RING_SIZE value) volatile
{
uint32_t curr = CH2_CTRL_TRIG;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(value) & 0b1111u) << 6u;
CH2_CTRL_TRIG = curr;
}
inline bool get_CH2_CTRL_TRIG_RING_SEL() volatile
{
return CH2_CTRL_TRIG & (1u << 10u);
}
inline void set_CH2_CTRL_TRIG_RING_SEL() volatile
{
CH2_CTRL_TRIG |= 1u << 10u;
}
inline void clear_CH2_CTRL_TRIG_RING_SEL() volatile
{
CH2_CTRL_TRIG &= ~(1u << 10u);
}
inline void toggle_CH2_CTRL_TRIG_RING_SEL() volatile
{
CH2_CTRL_TRIG ^= 1u << 10u;
}
inline uint8_t get_CH2_CTRL_TRIG_CHAIN_TO() volatile
{
return (CH2_CTRL_TRIG >> 11u) & 0b1111u;
}
inline void set_CH2_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile
{
uint32_t curr = CH2_CTRL_TRIG;
curr &= ~(0b1111u << 11u);
curr |= (value & 0b1111u) << 11u;
CH2_CTRL_TRIG = curr;
}
inline DMA_CH2_CTRL_TRIG_TREQ_SEL get_CH2_CTRL_TRIG_TREQ_SEL() volatile
{
return DMA_CH2_CTRL_TRIG_TREQ_SEL((CH2_CTRL_TRIG >> 15u) & 0b111111u);
}
inline void set_CH2_CTRL_TRIG_TREQ_SEL(
DMA_CH2_CTRL_TRIG_TREQ_SEL value) volatile
{
uint32_t curr = CH2_CTRL_TRIG;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(value) & 0b111111u) << 15u;
CH2_CTRL_TRIG = curr;
}
inline bool get_CH2_CTRL_TRIG_IRQ_QUIET() volatile
{
return CH2_CTRL_TRIG & (1u << 21u);
}
inline void set_CH2_CTRL_TRIG_IRQ_QUIET() volatile
{
CH2_CTRL_TRIG |= 1u << 21u;
}
inline void clear_CH2_CTRL_TRIG_IRQ_QUIET() volatile
{
CH2_CTRL_TRIG &= ~(1u << 21u);
}
inline void toggle_CH2_CTRL_TRIG_IRQ_QUIET() volatile
{
CH2_CTRL_TRIG ^= 1u << 21u;
}
inline bool get_CH2_CTRL_TRIG_BSWAP() volatile
{
return CH2_CTRL_TRIG & (1u << 22u);
}
inline void set_CH2_CTRL_TRIG_BSWAP() volatile
{
CH2_CTRL_TRIG |= 1u << 22u;
}
inline void clear_CH2_CTRL_TRIG_BSWAP() volatile
{
CH2_CTRL_TRIG &= ~(1u << 22u);
}
inline void toggle_CH2_CTRL_TRIG_BSWAP() volatile
{
CH2_CTRL_TRIG ^= 1u << 22u;
}
inline bool get_CH2_CTRL_TRIG_SNIFF_EN() volatile
{
return CH2_CTRL_TRIG & (1u << 23u);
}
inline void set_CH2_CTRL_TRIG_SNIFF_EN() volatile
{
CH2_CTRL_TRIG |= 1u << 23u;
}
inline void clear_CH2_CTRL_TRIG_SNIFF_EN() volatile
{
CH2_CTRL_TRIG &= ~(1u << 23u);
}
inline void toggle_CH2_CTRL_TRIG_SNIFF_EN() volatile
{
CH2_CTRL_TRIG ^= 1u << 23u;
}
inline bool get_CH2_CTRL_TRIG_BUSY() volatile
{
return CH2_CTRL_TRIG & (1u << 24u);
}
inline bool get_CH2_CTRL_TRIG_WRITE_ERROR() volatile
{
return CH2_CTRL_TRIG & (1u << 29u);
}
inline void set_CH2_CTRL_TRIG_WRITE_ERROR() volatile
{
CH2_CTRL_TRIG |= 1u << 29u;
}
inline void clear_CH2_CTRL_TRIG_WRITE_ERROR() volatile
{
CH2_CTRL_TRIG &= ~(1u << 29u);
}
inline void toggle_CH2_CTRL_TRIG_WRITE_ERROR() volatile
{
CH2_CTRL_TRIG ^= 1u << 29u;
}
inline bool get_CH2_CTRL_TRIG_READ_ERROR() volatile
{
return CH2_CTRL_TRIG & (1u << 30u);
}
inline void set_CH2_CTRL_TRIG_READ_ERROR() volatile
{
CH2_CTRL_TRIG |= 1u << 30u;
}
inline void clear_CH2_CTRL_TRIG_READ_ERROR() volatile
{
CH2_CTRL_TRIG &= ~(1u << 30u);
}
inline void toggle_CH2_CTRL_TRIG_READ_ERROR() volatile
{
CH2_CTRL_TRIG ^= 1u << 30u;
}
inline bool get_CH2_CTRL_TRIG_AHB_ERROR() volatile
{
return CH2_CTRL_TRIG & (1u << 31u);
}
inline void get_CH2_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY,
DMA_CH2_CTRL_TRIG_DATA_SIZE &DATA_SIZE,
bool &INCR_READ, bool &INCR_WRITE,
DMA_CH2_CTRL_TRIG_RING_SIZE &RING_SIZE,
bool &RING_SEL, uint8_t &CHAIN_TO,
DMA_CH2_CTRL_TRIG_TREQ_SEL &TREQ_SEL,
bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN,
bool &BUSY, bool &WRITE_ERROR,
bool &READ_ERROR, bool &AHB_ERROR) volatile
{
uint32_t curr = CH2_CTRL_TRIG;
EN = curr & (1u << 0u);
HIGH_PRIORITY = curr & (1u << 1u);
DATA_SIZE = DMA_CH2_CTRL_TRIG_DATA_SIZE((curr >> 2u) & 0b11u);
INCR_READ = curr & (1u << 4u);
INCR_WRITE = curr & (1u << 5u);
RING_SIZE = DMA_CH2_CTRL_TRIG_RING_SIZE((curr >> 6u) & 0b1111u);
RING_SEL = curr & (1u << 10u);
CHAIN_TO = (curr >> 11u) & 0b1111u;
TREQ_SEL = DMA_CH2_CTRL_TRIG_TREQ_SEL((curr >> 15u) & 0b111111u);
IRQ_QUIET = curr & (1u << 21u);
BSWAP = curr & (1u << 22u);
SNIFF_EN = curr & (1u << 23u);
BUSY = curr & (1u << 24u);
WRITE_ERROR = curr & (1u << 29u);
READ_ERROR = curr & (1u << 30u);
AHB_ERROR = curr & (1u << 31u);
}
inline void set_CH2_CTRL_TRIG(bool EN, bool HIGH_PRIORITY,
DMA_CH2_CTRL_TRIG_DATA_SIZE DATA_SIZE,
bool INCR_READ, bool INCR_WRITE,
DMA_CH2_CTRL_TRIG_RING_SIZE RING_SIZE,
bool RING_SEL, uint8_t CHAIN_TO,
DMA_CH2_CTRL_TRIG_TREQ_SEL TREQ_SEL,
bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN,
bool WRITE_ERROR, bool READ_ERROR) volatile
{
uint32_t curr = CH2_CTRL_TRIG;
curr &= ~(0b1u << 0u);
curr |= (EN & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (HIGH_PRIORITY & 0b1u) << 1u;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
curr &= ~(0b1u << 4u);
curr |= (INCR_READ & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (INCR_WRITE & 0b1u) << 5u;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(RING_SIZE) & 0b1111u) << 6u;
curr &= ~(0b1u << 10u);
curr |= (RING_SEL & 0b1u) << 10u;
curr &= ~(0b1111u << 11u);
curr |= (CHAIN_TO & 0b1111u) << 11u;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
curr &= ~(0b1u << 21u);
curr |= (IRQ_QUIET & 0b1u) << 21u;
curr &= ~(0b1u << 22u);
curr |= (BSWAP & 0b1u) << 22u;
curr &= ~(0b1u << 23u);
curr |= (SNIFF_EN & 0b1u) << 23u;
curr &= ~(0b1u << 29u);
curr |= (WRITE_ERROR & 0b1u) << 29u;
curr &= ~(0b1u << 30u);
curr |= (READ_ERROR & 0b1u) << 30u;
CH2_CTRL_TRIG = curr;
}
inline bool get_CH3_CTRL_TRIG_EN() volatile
{
return CH3_CTRL_TRIG & (1u << 0u);
}
inline void set_CH3_CTRL_TRIG_EN() volatile
{
CH3_CTRL_TRIG |= 1u << 0u;
}
inline void clear_CH3_CTRL_TRIG_EN() volatile
{
CH3_CTRL_TRIG &= ~(1u << 0u);
}
inline void toggle_CH3_CTRL_TRIG_EN() volatile
{
CH3_CTRL_TRIG ^= 1u << 0u;
}
inline bool get_CH3_CTRL_TRIG_HIGH_PRIORITY() volatile
{
return CH3_CTRL_TRIG & (1u << 1u);
}
inline void set_CH3_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH3_CTRL_TRIG |= 1u << 1u;
}
inline void clear_CH3_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH3_CTRL_TRIG &= ~(1u << 1u);
}
inline void toggle_CH3_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH3_CTRL_TRIG ^= 1u << 1u;
}
inline DMA_CH3_CTRL_TRIG_DATA_SIZE get_CH3_CTRL_TRIG_DATA_SIZE() volatile
{
return DMA_CH3_CTRL_TRIG_DATA_SIZE((CH3_CTRL_TRIG >> 2u) & 0b11u);
}
inline void set_CH3_CTRL_TRIG_DATA_SIZE(
DMA_CH3_CTRL_TRIG_DATA_SIZE value) volatile
{
uint32_t curr = CH3_CTRL_TRIG;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(value) & 0b11u) << 2u;
CH3_CTRL_TRIG = curr;
}
inline bool get_CH3_CTRL_TRIG_INCR_READ() volatile
{
return CH3_CTRL_TRIG & (1u << 4u);
}
inline void set_CH3_CTRL_TRIG_INCR_READ() volatile
{
CH3_CTRL_TRIG |= 1u << 4u;
}
inline void clear_CH3_CTRL_TRIG_INCR_READ() volatile
{
CH3_CTRL_TRIG &= ~(1u << 4u);
}
inline void toggle_CH3_CTRL_TRIG_INCR_READ() volatile
{
CH3_CTRL_TRIG ^= 1u << 4u;
}
inline bool get_CH3_CTRL_TRIG_INCR_WRITE() volatile
{
return CH3_CTRL_TRIG & (1u << 5u);
}
inline void set_CH3_CTRL_TRIG_INCR_WRITE() volatile
{
CH3_CTRL_TRIG |= 1u << 5u;
}
inline void clear_CH3_CTRL_TRIG_INCR_WRITE() volatile
{
CH3_CTRL_TRIG &= ~(1u << 5u);
}
inline void toggle_CH3_CTRL_TRIG_INCR_WRITE() volatile
{
CH3_CTRL_TRIG ^= 1u << 5u;
}
inline DMA_CH3_CTRL_TRIG_RING_SIZE get_CH3_CTRL_TRIG_RING_SIZE() volatile
{
return DMA_CH3_CTRL_TRIG_RING_SIZE((CH3_CTRL_TRIG >> 6u) & 0b1111u);
}
inline void set_CH3_CTRL_TRIG_RING_SIZE(
DMA_CH3_CTRL_TRIG_RING_SIZE value) volatile
{
uint32_t curr = CH3_CTRL_TRIG;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(value) & 0b1111u) << 6u;
CH3_CTRL_TRIG = curr;
}
inline bool get_CH3_CTRL_TRIG_RING_SEL() volatile
{
return CH3_CTRL_TRIG & (1u << 10u);
}
inline void set_CH3_CTRL_TRIG_RING_SEL() volatile
{
CH3_CTRL_TRIG |= 1u << 10u;
}
inline void clear_CH3_CTRL_TRIG_RING_SEL() volatile
{
CH3_CTRL_TRIG &= ~(1u << 10u);
}
inline void toggle_CH3_CTRL_TRIG_RING_SEL() volatile
{
CH3_CTRL_TRIG ^= 1u << 10u;
}
inline uint8_t get_CH3_CTRL_TRIG_CHAIN_TO() volatile
{
return (CH3_CTRL_TRIG >> 11u) & 0b1111u;
}
inline void set_CH3_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile
{
uint32_t curr = CH3_CTRL_TRIG;
curr &= ~(0b1111u << 11u);
curr |= (value & 0b1111u) << 11u;
CH3_CTRL_TRIG = curr;
}
inline DMA_CH3_CTRL_TRIG_TREQ_SEL get_CH3_CTRL_TRIG_TREQ_SEL() volatile
{
return DMA_CH3_CTRL_TRIG_TREQ_SEL((CH3_CTRL_TRIG >> 15u) & 0b111111u);
}
inline void set_CH3_CTRL_TRIG_TREQ_SEL(
DMA_CH3_CTRL_TRIG_TREQ_SEL value) volatile
{
uint32_t curr = CH3_CTRL_TRIG;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(value) & 0b111111u) << 15u;
CH3_CTRL_TRIG = curr;
}
inline bool get_CH3_CTRL_TRIG_IRQ_QUIET() volatile
{
return CH3_CTRL_TRIG & (1u << 21u);
}
inline void set_CH3_CTRL_TRIG_IRQ_QUIET() volatile
{
CH3_CTRL_TRIG |= 1u << 21u;
}
inline void clear_CH3_CTRL_TRIG_IRQ_QUIET() volatile
{
CH3_CTRL_TRIG &= ~(1u << 21u);
}
inline void toggle_CH3_CTRL_TRIG_IRQ_QUIET() volatile
{
CH3_CTRL_TRIG ^= 1u << 21u;
}
inline bool get_CH3_CTRL_TRIG_BSWAP() volatile
{
return CH3_CTRL_TRIG & (1u << 22u);
}
inline void set_CH3_CTRL_TRIG_BSWAP() volatile
{
CH3_CTRL_TRIG |= 1u << 22u;
}
inline void clear_CH3_CTRL_TRIG_BSWAP() volatile
{
CH3_CTRL_TRIG &= ~(1u << 22u);
}
inline void toggle_CH3_CTRL_TRIG_BSWAP() volatile
{
CH3_CTRL_TRIG ^= 1u << 22u;
}
inline bool get_CH3_CTRL_TRIG_SNIFF_EN() volatile
{
return CH3_CTRL_TRIG & (1u << 23u);
}
inline void set_CH3_CTRL_TRIG_SNIFF_EN() volatile
{
CH3_CTRL_TRIG |= 1u << 23u;
}
inline void clear_CH3_CTRL_TRIG_SNIFF_EN() volatile
{
CH3_CTRL_TRIG &= ~(1u << 23u);
}
inline void toggle_CH3_CTRL_TRIG_SNIFF_EN() volatile
{
CH3_CTRL_TRIG ^= 1u << 23u;
}
inline bool get_CH3_CTRL_TRIG_BUSY() volatile
{
return CH3_CTRL_TRIG & (1u << 24u);
}
inline bool get_CH3_CTRL_TRIG_WRITE_ERROR() volatile
{
return CH3_CTRL_TRIG & (1u << 29u);
}
inline void set_CH3_CTRL_TRIG_WRITE_ERROR() volatile
{
CH3_CTRL_TRIG |= 1u << 29u;
}
inline void clear_CH3_CTRL_TRIG_WRITE_ERROR() volatile
{
CH3_CTRL_TRIG &= ~(1u << 29u);
}
inline void toggle_CH3_CTRL_TRIG_WRITE_ERROR() volatile
{
CH3_CTRL_TRIG ^= 1u << 29u;
}
inline bool get_CH3_CTRL_TRIG_READ_ERROR() volatile
{
return CH3_CTRL_TRIG & (1u << 30u);
}
inline void set_CH3_CTRL_TRIG_READ_ERROR() volatile
{
CH3_CTRL_TRIG |= 1u << 30u;
}
inline void clear_CH3_CTRL_TRIG_READ_ERROR() volatile
{
CH3_CTRL_TRIG &= ~(1u << 30u);
}
inline void toggle_CH3_CTRL_TRIG_READ_ERROR() volatile
{
CH3_CTRL_TRIG ^= 1u << 30u;
}
inline bool get_CH3_CTRL_TRIG_AHB_ERROR() volatile
{
return CH3_CTRL_TRIG & (1u << 31u);
}
inline void get_CH3_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY,
DMA_CH3_CTRL_TRIG_DATA_SIZE &DATA_SIZE,
bool &INCR_READ, bool &INCR_WRITE,
DMA_CH3_CTRL_TRIG_RING_SIZE &RING_SIZE,
bool &RING_SEL, uint8_t &CHAIN_TO,
DMA_CH3_CTRL_TRIG_TREQ_SEL &TREQ_SEL,
bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN,
bool &BUSY, bool &WRITE_ERROR,
bool &READ_ERROR, bool &AHB_ERROR) volatile
{
uint32_t curr = CH3_CTRL_TRIG;
EN = curr & (1u << 0u);
HIGH_PRIORITY = curr & (1u << 1u);
DATA_SIZE = DMA_CH3_CTRL_TRIG_DATA_SIZE((curr >> 2u) & 0b11u);
INCR_READ = curr & (1u << 4u);
INCR_WRITE = curr & (1u << 5u);
RING_SIZE = DMA_CH3_CTRL_TRIG_RING_SIZE((curr >> 6u) & 0b1111u);
RING_SEL = curr & (1u << 10u);
CHAIN_TO = (curr >> 11u) & 0b1111u;
TREQ_SEL = DMA_CH3_CTRL_TRIG_TREQ_SEL((curr >> 15u) & 0b111111u);
IRQ_QUIET = curr & (1u << 21u);
BSWAP = curr & (1u << 22u);
SNIFF_EN = curr & (1u << 23u);
BUSY = curr & (1u << 24u);
WRITE_ERROR = curr & (1u << 29u);
READ_ERROR = curr & (1u << 30u);
AHB_ERROR = curr & (1u << 31u);
}
inline void set_CH3_CTRL_TRIG(bool EN, bool HIGH_PRIORITY,
DMA_CH3_CTRL_TRIG_DATA_SIZE DATA_SIZE,
bool INCR_READ, bool INCR_WRITE,
DMA_CH3_CTRL_TRIG_RING_SIZE RING_SIZE,
bool RING_SEL, uint8_t CHAIN_TO,
DMA_CH3_CTRL_TRIG_TREQ_SEL TREQ_SEL,
bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN,
bool WRITE_ERROR, bool READ_ERROR) volatile
{
uint32_t curr = CH3_CTRL_TRIG;
curr &= ~(0b1u << 0u);
curr |= (EN & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (HIGH_PRIORITY & 0b1u) << 1u;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
curr &= ~(0b1u << 4u);
curr |= (INCR_READ & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (INCR_WRITE & 0b1u) << 5u;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(RING_SIZE) & 0b1111u) << 6u;
curr &= ~(0b1u << 10u);
curr |= (RING_SEL & 0b1u) << 10u;
curr &= ~(0b1111u << 11u);
curr |= (CHAIN_TO & 0b1111u) << 11u;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
curr &= ~(0b1u << 21u);
curr |= (IRQ_QUIET & 0b1u) << 21u;
curr &= ~(0b1u << 22u);
curr |= (BSWAP & 0b1u) << 22u;
curr &= ~(0b1u << 23u);
curr |= (SNIFF_EN & 0b1u) << 23u;
curr &= ~(0b1u << 29u);
curr |= (WRITE_ERROR & 0b1u) << 29u;
curr &= ~(0b1u << 30u);
curr |= (READ_ERROR & 0b1u) << 30u;
CH3_CTRL_TRIG = curr;
}
inline bool get_CH4_CTRL_TRIG_EN() volatile
{
return CH4_CTRL_TRIG & (1u << 0u);
}
inline void set_CH4_CTRL_TRIG_EN() volatile
{
CH4_CTRL_TRIG |= 1u << 0u;
}
inline void clear_CH4_CTRL_TRIG_EN() volatile
{
CH4_CTRL_TRIG &= ~(1u << 0u);
}
inline void toggle_CH4_CTRL_TRIG_EN() volatile
{
CH4_CTRL_TRIG ^= 1u << 0u;
}
inline bool get_CH4_CTRL_TRIG_HIGH_PRIORITY() volatile
{
return CH4_CTRL_TRIG & (1u << 1u);
}
inline void set_CH4_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH4_CTRL_TRIG |= 1u << 1u;
}
inline void clear_CH4_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH4_CTRL_TRIG &= ~(1u << 1u);
}
inline void toggle_CH4_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH4_CTRL_TRIG ^= 1u << 1u;
}
inline DMA_CH4_CTRL_TRIG_DATA_SIZE get_CH4_CTRL_TRIG_DATA_SIZE() volatile
{
return DMA_CH4_CTRL_TRIG_DATA_SIZE((CH4_CTRL_TRIG >> 2u) & 0b11u);
}
inline void set_CH4_CTRL_TRIG_DATA_SIZE(
DMA_CH4_CTRL_TRIG_DATA_SIZE value) volatile
{
uint32_t curr = CH4_CTRL_TRIG;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(value) & 0b11u) << 2u;
CH4_CTRL_TRIG = curr;
}
inline bool get_CH4_CTRL_TRIG_INCR_READ() volatile
{
return CH4_CTRL_TRIG & (1u << 4u);
}
inline void set_CH4_CTRL_TRIG_INCR_READ() volatile
{
CH4_CTRL_TRIG |= 1u << 4u;
}
inline void clear_CH4_CTRL_TRIG_INCR_READ() volatile
{
CH4_CTRL_TRIG &= ~(1u << 4u);
}
inline void toggle_CH4_CTRL_TRIG_INCR_READ() volatile
{
CH4_CTRL_TRIG ^= 1u << 4u;
}
inline bool get_CH4_CTRL_TRIG_INCR_WRITE() volatile
{
return CH4_CTRL_TRIG & (1u << 5u);
}
inline void set_CH4_CTRL_TRIG_INCR_WRITE() volatile
{
CH4_CTRL_TRIG |= 1u << 5u;
}
inline void clear_CH4_CTRL_TRIG_INCR_WRITE() volatile
{
CH4_CTRL_TRIG &= ~(1u << 5u);
}
inline void toggle_CH4_CTRL_TRIG_INCR_WRITE() volatile
{
CH4_CTRL_TRIG ^= 1u << 5u;
}
inline DMA_CH4_CTRL_TRIG_RING_SIZE get_CH4_CTRL_TRIG_RING_SIZE() volatile
{
return DMA_CH4_CTRL_TRIG_RING_SIZE((CH4_CTRL_TRIG >> 6u) & 0b1111u);
}
inline void set_CH4_CTRL_TRIG_RING_SIZE(
DMA_CH4_CTRL_TRIG_RING_SIZE value) volatile
{
uint32_t curr = CH4_CTRL_TRIG;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(value) & 0b1111u) << 6u;
CH4_CTRL_TRIG = curr;
}
inline bool get_CH4_CTRL_TRIG_RING_SEL() volatile
{
return CH4_CTRL_TRIG & (1u << 10u);
}
inline void set_CH4_CTRL_TRIG_RING_SEL() volatile
{
CH4_CTRL_TRIG |= 1u << 10u;
}
inline void clear_CH4_CTRL_TRIG_RING_SEL() volatile
{
CH4_CTRL_TRIG &= ~(1u << 10u);
}
inline void toggle_CH4_CTRL_TRIG_RING_SEL() volatile
{
CH4_CTRL_TRIG ^= 1u << 10u;
}
inline uint8_t get_CH4_CTRL_TRIG_CHAIN_TO() volatile
{
return (CH4_CTRL_TRIG >> 11u) & 0b1111u;
}
inline void set_CH4_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile
{
uint32_t curr = CH4_CTRL_TRIG;
curr &= ~(0b1111u << 11u);
curr |= (value & 0b1111u) << 11u;
CH4_CTRL_TRIG = curr;
}
inline DMA_CH4_CTRL_TRIG_TREQ_SEL get_CH4_CTRL_TRIG_TREQ_SEL() volatile
{
return DMA_CH4_CTRL_TRIG_TREQ_SEL((CH4_CTRL_TRIG >> 15u) & 0b111111u);
}
inline void set_CH4_CTRL_TRIG_TREQ_SEL(
DMA_CH4_CTRL_TRIG_TREQ_SEL value) volatile
{
uint32_t curr = CH4_CTRL_TRIG;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(value) & 0b111111u) << 15u;
CH4_CTRL_TRIG = curr;
}
inline bool get_CH4_CTRL_TRIG_IRQ_QUIET() volatile
{
return CH4_CTRL_TRIG & (1u << 21u);
}
inline void set_CH4_CTRL_TRIG_IRQ_QUIET() volatile
{
CH4_CTRL_TRIG |= 1u << 21u;
}
inline void clear_CH4_CTRL_TRIG_IRQ_QUIET() volatile
{
CH4_CTRL_TRIG &= ~(1u << 21u);
}
inline void toggle_CH4_CTRL_TRIG_IRQ_QUIET() volatile
{
CH4_CTRL_TRIG ^= 1u << 21u;
}
inline bool get_CH4_CTRL_TRIG_BSWAP() volatile
{
return CH4_CTRL_TRIG & (1u << 22u);
}
inline void set_CH4_CTRL_TRIG_BSWAP() volatile
{
CH4_CTRL_TRIG |= 1u << 22u;
}
inline void clear_CH4_CTRL_TRIG_BSWAP() volatile
{
CH4_CTRL_TRIG &= ~(1u << 22u);
}
inline void toggle_CH4_CTRL_TRIG_BSWAP() volatile
{
CH4_CTRL_TRIG ^= 1u << 22u;
}
inline bool get_CH4_CTRL_TRIG_SNIFF_EN() volatile
{
return CH4_CTRL_TRIG & (1u << 23u);
}
inline void set_CH4_CTRL_TRIG_SNIFF_EN() volatile
{
CH4_CTRL_TRIG |= 1u << 23u;
}
inline void clear_CH4_CTRL_TRIG_SNIFF_EN() volatile
{
CH4_CTRL_TRIG &= ~(1u << 23u);
}
inline void toggle_CH4_CTRL_TRIG_SNIFF_EN() volatile
{
CH4_CTRL_TRIG ^= 1u << 23u;
}
inline bool get_CH4_CTRL_TRIG_BUSY() volatile
{
return CH4_CTRL_TRIG & (1u << 24u);
}
inline bool get_CH4_CTRL_TRIG_WRITE_ERROR() volatile
{
return CH4_CTRL_TRIG & (1u << 29u);
}
inline void set_CH4_CTRL_TRIG_WRITE_ERROR() volatile
{
CH4_CTRL_TRIG |= 1u << 29u;
}
inline void clear_CH4_CTRL_TRIG_WRITE_ERROR() volatile
{
CH4_CTRL_TRIG &= ~(1u << 29u);
}
inline void toggle_CH4_CTRL_TRIG_WRITE_ERROR() volatile
{
CH4_CTRL_TRIG ^= 1u << 29u;
}
inline bool get_CH4_CTRL_TRIG_READ_ERROR() volatile
{
return CH4_CTRL_TRIG & (1u << 30u);
}
inline void set_CH4_CTRL_TRIG_READ_ERROR() volatile
{
CH4_CTRL_TRIG |= 1u << 30u;
}
inline void clear_CH4_CTRL_TRIG_READ_ERROR() volatile
{
CH4_CTRL_TRIG &= ~(1u << 30u);
}
inline void toggle_CH4_CTRL_TRIG_READ_ERROR() volatile
{
CH4_CTRL_TRIG ^= 1u << 30u;
}
inline bool get_CH4_CTRL_TRIG_AHB_ERROR() volatile
{
return CH4_CTRL_TRIG & (1u << 31u);
}
inline void get_CH4_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY,
DMA_CH4_CTRL_TRIG_DATA_SIZE &DATA_SIZE,
bool &INCR_READ, bool &INCR_WRITE,
DMA_CH4_CTRL_TRIG_RING_SIZE &RING_SIZE,
bool &RING_SEL, uint8_t &CHAIN_TO,
DMA_CH4_CTRL_TRIG_TREQ_SEL &TREQ_SEL,
bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN,
bool &BUSY, bool &WRITE_ERROR,
bool &READ_ERROR, bool &AHB_ERROR) volatile
{
uint32_t curr = CH4_CTRL_TRIG;
EN = curr & (1u << 0u);
HIGH_PRIORITY = curr & (1u << 1u);
DATA_SIZE = DMA_CH4_CTRL_TRIG_DATA_SIZE((curr >> 2u) & 0b11u);
INCR_READ = curr & (1u << 4u);
INCR_WRITE = curr & (1u << 5u);
RING_SIZE = DMA_CH4_CTRL_TRIG_RING_SIZE((curr >> 6u) & 0b1111u);
RING_SEL = curr & (1u << 10u);
CHAIN_TO = (curr >> 11u) & 0b1111u;
TREQ_SEL = DMA_CH4_CTRL_TRIG_TREQ_SEL((curr >> 15u) & 0b111111u);
IRQ_QUIET = curr & (1u << 21u);
BSWAP = curr & (1u << 22u);
SNIFF_EN = curr & (1u << 23u);
BUSY = curr & (1u << 24u);
WRITE_ERROR = curr & (1u << 29u);
READ_ERROR = curr & (1u << 30u);
AHB_ERROR = curr & (1u << 31u);
}
inline void set_CH4_CTRL_TRIG(bool EN, bool HIGH_PRIORITY,
DMA_CH4_CTRL_TRIG_DATA_SIZE DATA_SIZE,
bool INCR_READ, bool INCR_WRITE,
DMA_CH4_CTRL_TRIG_RING_SIZE RING_SIZE,
bool RING_SEL, uint8_t CHAIN_TO,
DMA_CH4_CTRL_TRIG_TREQ_SEL TREQ_SEL,
bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN,
bool WRITE_ERROR, bool READ_ERROR) volatile
{
uint32_t curr = CH4_CTRL_TRIG;
curr &= ~(0b1u << 0u);
curr |= (EN & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (HIGH_PRIORITY & 0b1u) << 1u;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
curr &= ~(0b1u << 4u);
curr |= (INCR_READ & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (INCR_WRITE & 0b1u) << 5u;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(RING_SIZE) & 0b1111u) << 6u;
curr &= ~(0b1u << 10u);
curr |= (RING_SEL & 0b1u) << 10u;
curr &= ~(0b1111u << 11u);
curr |= (CHAIN_TO & 0b1111u) << 11u;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
curr &= ~(0b1u << 21u);
curr |= (IRQ_QUIET & 0b1u) << 21u;
curr &= ~(0b1u << 22u);
curr |= (BSWAP & 0b1u) << 22u;
curr &= ~(0b1u << 23u);
curr |= (SNIFF_EN & 0b1u) << 23u;
curr &= ~(0b1u << 29u);
curr |= (WRITE_ERROR & 0b1u) << 29u;
curr &= ~(0b1u << 30u);
curr |= (READ_ERROR & 0b1u) << 30u;
CH4_CTRL_TRIG = curr;
}
inline bool get_CH5_CTRL_TRIG_EN() volatile
{
return CH5_CTRL_TRIG & (1u << 0u);
}
inline void set_CH5_CTRL_TRIG_EN() volatile
{
CH5_CTRL_TRIG |= 1u << 0u;
}
inline void clear_CH5_CTRL_TRIG_EN() volatile
{
CH5_CTRL_TRIG &= ~(1u << 0u);
}
inline void toggle_CH5_CTRL_TRIG_EN() volatile
{
CH5_CTRL_TRIG ^= 1u << 0u;
}
inline bool get_CH5_CTRL_TRIG_HIGH_PRIORITY() volatile
{
return CH5_CTRL_TRIG & (1u << 1u);
}
inline void set_CH5_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH5_CTRL_TRIG |= 1u << 1u;
}
inline void clear_CH5_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH5_CTRL_TRIG &= ~(1u << 1u);
}
inline void toggle_CH5_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH5_CTRL_TRIG ^= 1u << 1u;
}
inline DMA_CH5_CTRL_TRIG_DATA_SIZE get_CH5_CTRL_TRIG_DATA_SIZE() volatile
{
return DMA_CH5_CTRL_TRIG_DATA_SIZE((CH5_CTRL_TRIG >> 2u) & 0b11u);
}
inline void set_CH5_CTRL_TRIG_DATA_SIZE(
DMA_CH5_CTRL_TRIG_DATA_SIZE value) volatile
{
uint32_t curr = CH5_CTRL_TRIG;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(value) & 0b11u) << 2u;
CH5_CTRL_TRIG = curr;
}
inline bool get_CH5_CTRL_TRIG_INCR_READ() volatile
{
return CH5_CTRL_TRIG & (1u << 4u);
}
inline void set_CH5_CTRL_TRIG_INCR_READ() volatile
{
CH5_CTRL_TRIG |= 1u << 4u;
}
inline void clear_CH5_CTRL_TRIG_INCR_READ() volatile
{
CH5_CTRL_TRIG &= ~(1u << 4u);
}
inline void toggle_CH5_CTRL_TRIG_INCR_READ() volatile
{
CH5_CTRL_TRIG ^= 1u << 4u;
}
inline bool get_CH5_CTRL_TRIG_INCR_WRITE() volatile
{
return CH5_CTRL_TRIG & (1u << 5u);
}
inline void set_CH5_CTRL_TRIG_INCR_WRITE() volatile
{
CH5_CTRL_TRIG |= 1u << 5u;
}
inline void clear_CH5_CTRL_TRIG_INCR_WRITE() volatile
{
CH5_CTRL_TRIG &= ~(1u << 5u);
}
inline void toggle_CH5_CTRL_TRIG_INCR_WRITE() volatile
{
CH5_CTRL_TRIG ^= 1u << 5u;
}
inline DMA_CH5_CTRL_TRIG_RING_SIZE get_CH5_CTRL_TRIG_RING_SIZE() volatile
{
return DMA_CH5_CTRL_TRIG_RING_SIZE((CH5_CTRL_TRIG >> 6u) & 0b1111u);
}
inline void set_CH5_CTRL_TRIG_RING_SIZE(
DMA_CH5_CTRL_TRIG_RING_SIZE value) volatile
{
uint32_t curr = CH5_CTRL_TRIG;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(value) & 0b1111u) << 6u;
CH5_CTRL_TRIG = curr;
}
inline bool get_CH5_CTRL_TRIG_RING_SEL() volatile
{
return CH5_CTRL_TRIG & (1u << 10u);
}
inline void set_CH5_CTRL_TRIG_RING_SEL() volatile
{
CH5_CTRL_TRIG |= 1u << 10u;
}
inline void clear_CH5_CTRL_TRIG_RING_SEL() volatile
{
CH5_CTRL_TRIG &= ~(1u << 10u);
}
inline void toggle_CH5_CTRL_TRIG_RING_SEL() volatile
{
CH5_CTRL_TRIG ^= 1u << 10u;
}
inline uint8_t get_CH5_CTRL_TRIG_CHAIN_TO() volatile
{
return (CH5_CTRL_TRIG >> 11u) & 0b1111u;
}
inline void set_CH5_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile
{
uint32_t curr = CH5_CTRL_TRIG;
curr &= ~(0b1111u << 11u);
curr |= (value & 0b1111u) << 11u;
CH5_CTRL_TRIG = curr;
}
inline DMA_CH5_CTRL_TRIG_TREQ_SEL get_CH5_CTRL_TRIG_TREQ_SEL() volatile
{
return DMA_CH5_CTRL_TRIG_TREQ_SEL((CH5_CTRL_TRIG >> 15u) & 0b111111u);
}
inline void set_CH5_CTRL_TRIG_TREQ_SEL(
DMA_CH5_CTRL_TRIG_TREQ_SEL value) volatile
{
uint32_t curr = CH5_CTRL_TRIG;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(value) & 0b111111u) << 15u;
CH5_CTRL_TRIG = curr;
}
inline bool get_CH5_CTRL_TRIG_IRQ_QUIET() volatile
{
return CH5_CTRL_TRIG & (1u << 21u);
}
inline void set_CH5_CTRL_TRIG_IRQ_QUIET() volatile
{
CH5_CTRL_TRIG |= 1u << 21u;
}
inline void clear_CH5_CTRL_TRIG_IRQ_QUIET() volatile
{
CH5_CTRL_TRIG &= ~(1u << 21u);
}
inline void toggle_CH5_CTRL_TRIG_IRQ_QUIET() volatile
{
CH5_CTRL_TRIG ^= 1u << 21u;
}
inline bool get_CH5_CTRL_TRIG_BSWAP() volatile
{
return CH5_CTRL_TRIG & (1u << 22u);
}
inline void set_CH5_CTRL_TRIG_BSWAP() volatile
{
CH5_CTRL_TRIG |= 1u << 22u;
}
inline void clear_CH5_CTRL_TRIG_BSWAP() volatile
{
CH5_CTRL_TRIG &= ~(1u << 22u);
}
inline void toggle_CH5_CTRL_TRIG_BSWAP() volatile
{
CH5_CTRL_TRIG ^= 1u << 22u;
}
inline bool get_CH5_CTRL_TRIG_SNIFF_EN() volatile
{
return CH5_CTRL_TRIG & (1u << 23u);
}
inline void set_CH5_CTRL_TRIG_SNIFF_EN() volatile
{
CH5_CTRL_TRIG |= 1u << 23u;
}
inline void clear_CH5_CTRL_TRIG_SNIFF_EN() volatile
{
CH5_CTRL_TRIG &= ~(1u << 23u);
}
inline void toggle_CH5_CTRL_TRIG_SNIFF_EN() volatile
{
CH5_CTRL_TRIG ^= 1u << 23u;
}
inline bool get_CH5_CTRL_TRIG_BUSY() volatile
{
return CH5_CTRL_TRIG & (1u << 24u);
}
inline bool get_CH5_CTRL_TRIG_WRITE_ERROR() volatile
{
return CH5_CTRL_TRIG & (1u << 29u);
}
inline void set_CH5_CTRL_TRIG_WRITE_ERROR() volatile
{
CH5_CTRL_TRIG |= 1u << 29u;
}
inline void clear_CH5_CTRL_TRIG_WRITE_ERROR() volatile
{
CH5_CTRL_TRIG &= ~(1u << 29u);
}
inline void toggle_CH5_CTRL_TRIG_WRITE_ERROR() volatile
{
CH5_CTRL_TRIG ^= 1u << 29u;
}
inline bool get_CH5_CTRL_TRIG_READ_ERROR() volatile
{
return CH5_CTRL_TRIG & (1u << 30u);
}
inline void set_CH5_CTRL_TRIG_READ_ERROR() volatile
{
CH5_CTRL_TRIG |= 1u << 30u;
}
inline void clear_CH5_CTRL_TRIG_READ_ERROR() volatile
{
CH5_CTRL_TRIG &= ~(1u << 30u);
}
inline void toggle_CH5_CTRL_TRIG_READ_ERROR() volatile
{
CH5_CTRL_TRIG ^= 1u << 30u;
}
inline bool get_CH5_CTRL_TRIG_AHB_ERROR() volatile
{
return CH5_CTRL_TRIG & (1u << 31u);
}
inline void get_CH5_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY,
DMA_CH5_CTRL_TRIG_DATA_SIZE &DATA_SIZE,
bool &INCR_READ, bool &INCR_WRITE,
DMA_CH5_CTRL_TRIG_RING_SIZE &RING_SIZE,
bool &RING_SEL, uint8_t &CHAIN_TO,
DMA_CH5_CTRL_TRIG_TREQ_SEL &TREQ_SEL,
bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN,
bool &BUSY, bool &WRITE_ERROR,
bool &READ_ERROR, bool &AHB_ERROR) volatile
{
uint32_t curr = CH5_CTRL_TRIG;
EN = curr & (1u << 0u);
HIGH_PRIORITY = curr & (1u << 1u);
DATA_SIZE = DMA_CH5_CTRL_TRIG_DATA_SIZE((curr >> 2u) & 0b11u);
INCR_READ = curr & (1u << 4u);
INCR_WRITE = curr & (1u << 5u);
RING_SIZE = DMA_CH5_CTRL_TRIG_RING_SIZE((curr >> 6u) & 0b1111u);
RING_SEL = curr & (1u << 10u);
CHAIN_TO = (curr >> 11u) & 0b1111u;
TREQ_SEL = DMA_CH5_CTRL_TRIG_TREQ_SEL((curr >> 15u) & 0b111111u);
IRQ_QUIET = curr & (1u << 21u);
BSWAP = curr & (1u << 22u);
SNIFF_EN = curr & (1u << 23u);
BUSY = curr & (1u << 24u);
WRITE_ERROR = curr & (1u << 29u);
READ_ERROR = curr & (1u << 30u);
AHB_ERROR = curr & (1u << 31u);
}
inline void set_CH5_CTRL_TRIG(bool EN, bool HIGH_PRIORITY,
DMA_CH5_CTRL_TRIG_DATA_SIZE DATA_SIZE,
bool INCR_READ, bool INCR_WRITE,
DMA_CH5_CTRL_TRIG_RING_SIZE RING_SIZE,
bool RING_SEL, uint8_t CHAIN_TO,
DMA_CH5_CTRL_TRIG_TREQ_SEL TREQ_SEL,
bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN,
bool WRITE_ERROR, bool READ_ERROR) volatile
{
uint32_t curr = CH5_CTRL_TRIG;
curr &= ~(0b1u << 0u);
curr |= (EN & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (HIGH_PRIORITY & 0b1u) << 1u;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
curr &= ~(0b1u << 4u);
curr |= (INCR_READ & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (INCR_WRITE & 0b1u) << 5u;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(RING_SIZE) & 0b1111u) << 6u;
curr &= ~(0b1u << 10u);
curr |= (RING_SEL & 0b1u) << 10u;
curr &= ~(0b1111u << 11u);
curr |= (CHAIN_TO & 0b1111u) << 11u;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
curr &= ~(0b1u << 21u);
curr |= (IRQ_QUIET & 0b1u) << 21u;
curr &= ~(0b1u << 22u);
curr |= (BSWAP & 0b1u) << 22u;
curr &= ~(0b1u << 23u);
curr |= (SNIFF_EN & 0b1u) << 23u;
curr &= ~(0b1u << 29u);
curr |= (WRITE_ERROR & 0b1u) << 29u;
curr &= ~(0b1u << 30u);
curr |= (READ_ERROR & 0b1u) << 30u;
CH5_CTRL_TRIG = curr;
}
inline bool get_CH6_CTRL_TRIG_EN() volatile
{
return CH6_CTRL_TRIG & (1u << 0u);
}
inline void set_CH6_CTRL_TRIG_EN() volatile
{
CH6_CTRL_TRIG |= 1u << 0u;
}
inline void clear_CH6_CTRL_TRIG_EN() volatile
{
CH6_CTRL_TRIG &= ~(1u << 0u);
}
inline void toggle_CH6_CTRL_TRIG_EN() volatile
{
CH6_CTRL_TRIG ^= 1u << 0u;
}
inline bool get_CH6_CTRL_TRIG_HIGH_PRIORITY() volatile
{
return CH6_CTRL_TRIG & (1u << 1u);
}
inline void set_CH6_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH6_CTRL_TRIG |= 1u << 1u;
}
inline void clear_CH6_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH6_CTRL_TRIG &= ~(1u << 1u);
}
inline void toggle_CH6_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH6_CTRL_TRIG ^= 1u << 1u;
}
inline DMA_CH6_CTRL_TRIG_DATA_SIZE get_CH6_CTRL_TRIG_DATA_SIZE() volatile
{
return DMA_CH6_CTRL_TRIG_DATA_SIZE((CH6_CTRL_TRIG >> 2u) & 0b11u);
}
inline void set_CH6_CTRL_TRIG_DATA_SIZE(
DMA_CH6_CTRL_TRIG_DATA_SIZE value) volatile
{
uint32_t curr = CH6_CTRL_TRIG;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(value) & 0b11u) << 2u;
CH6_CTRL_TRIG = curr;
}
inline bool get_CH6_CTRL_TRIG_INCR_READ() volatile
{
return CH6_CTRL_TRIG & (1u << 4u);
}
inline void set_CH6_CTRL_TRIG_INCR_READ() volatile
{
CH6_CTRL_TRIG |= 1u << 4u;
}
inline void clear_CH6_CTRL_TRIG_INCR_READ() volatile
{
CH6_CTRL_TRIG &= ~(1u << 4u);
}
inline void toggle_CH6_CTRL_TRIG_INCR_READ() volatile
{
CH6_CTRL_TRIG ^= 1u << 4u;
}
inline bool get_CH6_CTRL_TRIG_INCR_WRITE() volatile
{
return CH6_CTRL_TRIG & (1u << 5u);
}
inline void set_CH6_CTRL_TRIG_INCR_WRITE() volatile
{
CH6_CTRL_TRIG |= 1u << 5u;
}
inline void clear_CH6_CTRL_TRIG_INCR_WRITE() volatile
{
CH6_CTRL_TRIG &= ~(1u << 5u);
}
inline void toggle_CH6_CTRL_TRIG_INCR_WRITE() volatile
{
CH6_CTRL_TRIG ^= 1u << 5u;
}
inline DMA_CH6_CTRL_TRIG_RING_SIZE get_CH6_CTRL_TRIG_RING_SIZE() volatile
{
return DMA_CH6_CTRL_TRIG_RING_SIZE((CH6_CTRL_TRIG >> 6u) & 0b1111u);
}
inline void set_CH6_CTRL_TRIG_RING_SIZE(
DMA_CH6_CTRL_TRIG_RING_SIZE value) volatile
{
uint32_t curr = CH6_CTRL_TRIG;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(value) & 0b1111u) << 6u;
CH6_CTRL_TRIG = curr;
}
inline bool get_CH6_CTRL_TRIG_RING_SEL() volatile
{
return CH6_CTRL_TRIG & (1u << 10u);
}
inline void set_CH6_CTRL_TRIG_RING_SEL() volatile
{
CH6_CTRL_TRIG |= 1u << 10u;
}
inline void clear_CH6_CTRL_TRIG_RING_SEL() volatile
{
CH6_CTRL_TRIG &= ~(1u << 10u);
}
inline void toggle_CH6_CTRL_TRIG_RING_SEL() volatile
{
CH6_CTRL_TRIG ^= 1u << 10u;
}
inline uint8_t get_CH6_CTRL_TRIG_CHAIN_TO() volatile
{
return (CH6_CTRL_TRIG >> 11u) & 0b1111u;
}
inline void set_CH6_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile
{
uint32_t curr = CH6_CTRL_TRIG;
curr &= ~(0b1111u << 11u);
curr |= (value & 0b1111u) << 11u;
CH6_CTRL_TRIG = curr;
}
inline DMA_CH6_CTRL_TRIG_TREQ_SEL get_CH6_CTRL_TRIG_TREQ_SEL() volatile
{
return DMA_CH6_CTRL_TRIG_TREQ_SEL((CH6_CTRL_TRIG >> 15u) & 0b111111u);
}
inline void set_CH6_CTRL_TRIG_TREQ_SEL(
DMA_CH6_CTRL_TRIG_TREQ_SEL value) volatile
{
uint32_t curr = CH6_CTRL_TRIG;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(value) & 0b111111u) << 15u;
CH6_CTRL_TRIG = curr;
}
inline bool get_CH6_CTRL_TRIG_IRQ_QUIET() volatile
{
return CH6_CTRL_TRIG & (1u << 21u);
}
inline void set_CH6_CTRL_TRIG_IRQ_QUIET() volatile
{
CH6_CTRL_TRIG |= 1u << 21u;
}
inline void clear_CH6_CTRL_TRIG_IRQ_QUIET() volatile
{
CH6_CTRL_TRIG &= ~(1u << 21u);
}
inline void toggle_CH6_CTRL_TRIG_IRQ_QUIET() volatile
{
CH6_CTRL_TRIG ^= 1u << 21u;
}
inline bool get_CH6_CTRL_TRIG_BSWAP() volatile
{
return CH6_CTRL_TRIG & (1u << 22u);
}
inline void set_CH6_CTRL_TRIG_BSWAP() volatile
{
CH6_CTRL_TRIG |= 1u << 22u;
}
inline void clear_CH6_CTRL_TRIG_BSWAP() volatile
{
CH6_CTRL_TRIG &= ~(1u << 22u);
}
inline void toggle_CH6_CTRL_TRIG_BSWAP() volatile
{
CH6_CTRL_TRIG ^= 1u << 22u;
}
inline bool get_CH6_CTRL_TRIG_SNIFF_EN() volatile
{
return CH6_CTRL_TRIG & (1u << 23u);
}
inline void set_CH6_CTRL_TRIG_SNIFF_EN() volatile
{
CH6_CTRL_TRIG |= 1u << 23u;
}
inline void clear_CH6_CTRL_TRIG_SNIFF_EN() volatile
{
CH6_CTRL_TRIG &= ~(1u << 23u);
}
inline void toggle_CH6_CTRL_TRIG_SNIFF_EN() volatile
{
CH6_CTRL_TRIG ^= 1u << 23u;
}
inline bool get_CH6_CTRL_TRIG_BUSY() volatile
{
return CH6_CTRL_TRIG & (1u << 24u);
}
inline bool get_CH6_CTRL_TRIG_WRITE_ERROR() volatile
{
return CH6_CTRL_TRIG & (1u << 29u);
}
inline void set_CH6_CTRL_TRIG_WRITE_ERROR() volatile
{
CH6_CTRL_TRIG |= 1u << 29u;
}
inline void clear_CH6_CTRL_TRIG_WRITE_ERROR() volatile
{
CH6_CTRL_TRIG &= ~(1u << 29u);
}
inline void toggle_CH6_CTRL_TRIG_WRITE_ERROR() volatile
{
CH6_CTRL_TRIG ^= 1u << 29u;
}
inline bool get_CH6_CTRL_TRIG_READ_ERROR() volatile
{
return CH6_CTRL_TRIG & (1u << 30u);
}
inline void set_CH6_CTRL_TRIG_READ_ERROR() volatile
{
CH6_CTRL_TRIG |= 1u << 30u;
}
inline void clear_CH6_CTRL_TRIG_READ_ERROR() volatile
{
CH6_CTRL_TRIG &= ~(1u << 30u);
}
inline void toggle_CH6_CTRL_TRIG_READ_ERROR() volatile
{
CH6_CTRL_TRIG ^= 1u << 30u;
}
inline bool get_CH6_CTRL_TRIG_AHB_ERROR() volatile
{
return CH6_CTRL_TRIG & (1u << 31u);
}
inline void get_CH6_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY,
DMA_CH6_CTRL_TRIG_DATA_SIZE &DATA_SIZE,
bool &INCR_READ, bool &INCR_WRITE,
DMA_CH6_CTRL_TRIG_RING_SIZE &RING_SIZE,
bool &RING_SEL, uint8_t &CHAIN_TO,
DMA_CH6_CTRL_TRIG_TREQ_SEL &TREQ_SEL,
bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN,
bool &BUSY, bool &WRITE_ERROR,
bool &READ_ERROR, bool &AHB_ERROR) volatile
{
uint32_t curr = CH6_CTRL_TRIG;
EN = curr & (1u << 0u);
HIGH_PRIORITY = curr & (1u << 1u);
DATA_SIZE = DMA_CH6_CTRL_TRIG_DATA_SIZE((curr >> 2u) & 0b11u);
INCR_READ = curr & (1u << 4u);
INCR_WRITE = curr & (1u << 5u);
RING_SIZE = DMA_CH6_CTRL_TRIG_RING_SIZE((curr >> 6u) & 0b1111u);
RING_SEL = curr & (1u << 10u);
CHAIN_TO = (curr >> 11u) & 0b1111u;
TREQ_SEL = DMA_CH6_CTRL_TRIG_TREQ_SEL((curr >> 15u) & 0b111111u);
IRQ_QUIET = curr & (1u << 21u);
BSWAP = curr & (1u << 22u);
SNIFF_EN = curr & (1u << 23u);
BUSY = curr & (1u << 24u);
WRITE_ERROR = curr & (1u << 29u);
READ_ERROR = curr & (1u << 30u);
AHB_ERROR = curr & (1u << 31u);
}
inline void set_CH6_CTRL_TRIG(bool EN, bool HIGH_PRIORITY,
DMA_CH6_CTRL_TRIG_DATA_SIZE DATA_SIZE,
bool INCR_READ, bool INCR_WRITE,
DMA_CH6_CTRL_TRIG_RING_SIZE RING_SIZE,
bool RING_SEL, uint8_t CHAIN_TO,
DMA_CH6_CTRL_TRIG_TREQ_SEL TREQ_SEL,
bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN,
bool WRITE_ERROR, bool READ_ERROR) volatile
{
uint32_t curr = CH6_CTRL_TRIG;
curr &= ~(0b1u << 0u);
curr |= (EN & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (HIGH_PRIORITY & 0b1u) << 1u;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
curr &= ~(0b1u << 4u);
curr |= (INCR_READ & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (INCR_WRITE & 0b1u) << 5u;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(RING_SIZE) & 0b1111u) << 6u;
curr &= ~(0b1u << 10u);
curr |= (RING_SEL & 0b1u) << 10u;
curr &= ~(0b1111u << 11u);
curr |= (CHAIN_TO & 0b1111u) << 11u;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
curr &= ~(0b1u << 21u);
curr |= (IRQ_QUIET & 0b1u) << 21u;
curr &= ~(0b1u << 22u);
curr |= (BSWAP & 0b1u) << 22u;
curr &= ~(0b1u << 23u);
curr |= (SNIFF_EN & 0b1u) << 23u;
curr &= ~(0b1u << 29u);
curr |= (WRITE_ERROR & 0b1u) << 29u;
curr &= ~(0b1u << 30u);
curr |= (READ_ERROR & 0b1u) << 30u;
CH6_CTRL_TRIG = curr;
}
inline bool get_CH7_CTRL_TRIG_EN() volatile
{
return CH7_CTRL_TRIG & (1u << 0u);
}
inline void set_CH7_CTRL_TRIG_EN() volatile
{
CH7_CTRL_TRIG |= 1u << 0u;
}
inline void clear_CH7_CTRL_TRIG_EN() volatile
{
CH7_CTRL_TRIG &= ~(1u << 0u);
}
inline void toggle_CH7_CTRL_TRIG_EN() volatile
{
CH7_CTRL_TRIG ^= 1u << 0u;
}
inline bool get_CH7_CTRL_TRIG_HIGH_PRIORITY() volatile
{
return CH7_CTRL_TRIG & (1u << 1u);
}
inline void set_CH7_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH7_CTRL_TRIG |= 1u << 1u;
}
inline void clear_CH7_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH7_CTRL_TRIG &= ~(1u << 1u);
}
inline void toggle_CH7_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH7_CTRL_TRIG ^= 1u << 1u;
}
inline DMA_CH7_CTRL_TRIG_DATA_SIZE get_CH7_CTRL_TRIG_DATA_SIZE() volatile
{
return DMA_CH7_CTRL_TRIG_DATA_SIZE((CH7_CTRL_TRIG >> 2u) & 0b11u);
}
inline void set_CH7_CTRL_TRIG_DATA_SIZE(
DMA_CH7_CTRL_TRIG_DATA_SIZE value) volatile
{
uint32_t curr = CH7_CTRL_TRIG;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(value) & 0b11u) << 2u;
CH7_CTRL_TRIG = curr;
}
inline bool get_CH7_CTRL_TRIG_INCR_READ() volatile
{
return CH7_CTRL_TRIG & (1u << 4u);
}
inline void set_CH7_CTRL_TRIG_INCR_READ() volatile
{
CH7_CTRL_TRIG |= 1u << 4u;
}
inline void clear_CH7_CTRL_TRIG_INCR_READ() volatile
{
CH7_CTRL_TRIG &= ~(1u << 4u);
}
inline void toggle_CH7_CTRL_TRIG_INCR_READ() volatile
{
CH7_CTRL_TRIG ^= 1u << 4u;
}
inline bool get_CH7_CTRL_TRIG_INCR_WRITE() volatile
{
return CH7_CTRL_TRIG & (1u << 5u);
}
inline void set_CH7_CTRL_TRIG_INCR_WRITE() volatile
{
CH7_CTRL_TRIG |= 1u << 5u;
}
inline void clear_CH7_CTRL_TRIG_INCR_WRITE() volatile
{
CH7_CTRL_TRIG &= ~(1u << 5u);
}
inline void toggle_CH7_CTRL_TRIG_INCR_WRITE() volatile
{
CH7_CTRL_TRIG ^= 1u << 5u;
}
inline DMA_CH7_CTRL_TRIG_RING_SIZE get_CH7_CTRL_TRIG_RING_SIZE() volatile
{
return DMA_CH7_CTRL_TRIG_RING_SIZE((CH7_CTRL_TRIG >> 6u) & 0b1111u);
}
inline void set_CH7_CTRL_TRIG_RING_SIZE(
DMA_CH7_CTRL_TRIG_RING_SIZE value) volatile
{
uint32_t curr = CH7_CTRL_TRIG;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(value) & 0b1111u) << 6u;
CH7_CTRL_TRIG = curr;
}
inline bool get_CH7_CTRL_TRIG_RING_SEL() volatile
{
return CH7_CTRL_TRIG & (1u << 10u);
}
inline void set_CH7_CTRL_TRIG_RING_SEL() volatile
{
CH7_CTRL_TRIG |= 1u << 10u;
}
inline void clear_CH7_CTRL_TRIG_RING_SEL() volatile
{
CH7_CTRL_TRIG &= ~(1u << 10u);
}
inline void toggle_CH7_CTRL_TRIG_RING_SEL() volatile
{
CH7_CTRL_TRIG ^= 1u << 10u;
}
inline uint8_t get_CH7_CTRL_TRIG_CHAIN_TO() volatile
{
return (CH7_CTRL_TRIG >> 11u) & 0b1111u;
}
inline void set_CH7_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile
{
uint32_t curr = CH7_CTRL_TRIG;
curr &= ~(0b1111u << 11u);
curr |= (value & 0b1111u) << 11u;
CH7_CTRL_TRIG = curr;
}
inline DMA_CH7_CTRL_TRIG_TREQ_SEL get_CH7_CTRL_TRIG_TREQ_SEL() volatile
{
return DMA_CH7_CTRL_TRIG_TREQ_SEL((CH7_CTRL_TRIG >> 15u) & 0b111111u);
}
inline void set_CH7_CTRL_TRIG_TREQ_SEL(
DMA_CH7_CTRL_TRIG_TREQ_SEL value) volatile
{
uint32_t curr = CH7_CTRL_TRIG;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(value) & 0b111111u) << 15u;
CH7_CTRL_TRIG = curr;
}
inline bool get_CH7_CTRL_TRIG_IRQ_QUIET() volatile
{
return CH7_CTRL_TRIG & (1u << 21u);
}
inline void set_CH7_CTRL_TRIG_IRQ_QUIET() volatile
{
CH7_CTRL_TRIG |= 1u << 21u;
}
inline void clear_CH7_CTRL_TRIG_IRQ_QUIET() volatile
{
CH7_CTRL_TRIG &= ~(1u << 21u);
}
inline void toggle_CH7_CTRL_TRIG_IRQ_QUIET() volatile
{
CH7_CTRL_TRIG ^= 1u << 21u;
}
inline bool get_CH7_CTRL_TRIG_BSWAP() volatile
{
return CH7_CTRL_TRIG & (1u << 22u);
}
inline void set_CH7_CTRL_TRIG_BSWAP() volatile
{
CH7_CTRL_TRIG |= 1u << 22u;
}
inline void clear_CH7_CTRL_TRIG_BSWAP() volatile
{
CH7_CTRL_TRIG &= ~(1u << 22u);
}
inline void toggle_CH7_CTRL_TRIG_BSWAP() volatile
{
CH7_CTRL_TRIG ^= 1u << 22u;
}
inline bool get_CH7_CTRL_TRIG_SNIFF_EN() volatile
{
return CH7_CTRL_TRIG & (1u << 23u);
}
inline void set_CH7_CTRL_TRIG_SNIFF_EN() volatile
{
CH7_CTRL_TRIG |= 1u << 23u;
}
inline void clear_CH7_CTRL_TRIG_SNIFF_EN() volatile
{
CH7_CTRL_TRIG &= ~(1u << 23u);
}
inline void toggle_CH7_CTRL_TRIG_SNIFF_EN() volatile
{
CH7_CTRL_TRIG ^= 1u << 23u;
}
inline bool get_CH7_CTRL_TRIG_BUSY() volatile
{
return CH7_CTRL_TRIG & (1u << 24u);
}
inline bool get_CH7_CTRL_TRIG_WRITE_ERROR() volatile
{
return CH7_CTRL_TRIG & (1u << 29u);
}
inline void set_CH7_CTRL_TRIG_WRITE_ERROR() volatile
{
CH7_CTRL_TRIG |= 1u << 29u;
}
inline void clear_CH7_CTRL_TRIG_WRITE_ERROR() volatile
{
CH7_CTRL_TRIG &= ~(1u << 29u);
}
inline void toggle_CH7_CTRL_TRIG_WRITE_ERROR() volatile
{
CH7_CTRL_TRIG ^= 1u << 29u;
}
inline bool get_CH7_CTRL_TRIG_READ_ERROR() volatile
{
return CH7_CTRL_TRIG & (1u << 30u);
}
inline void set_CH7_CTRL_TRIG_READ_ERROR() volatile
{
CH7_CTRL_TRIG |= 1u << 30u;
}
inline void clear_CH7_CTRL_TRIG_READ_ERROR() volatile
{
CH7_CTRL_TRIG &= ~(1u << 30u);
}
inline void toggle_CH7_CTRL_TRIG_READ_ERROR() volatile
{
CH7_CTRL_TRIG ^= 1u << 30u;
}
inline bool get_CH7_CTRL_TRIG_AHB_ERROR() volatile
{
return CH7_CTRL_TRIG & (1u << 31u);
}
inline void get_CH7_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY,
DMA_CH7_CTRL_TRIG_DATA_SIZE &DATA_SIZE,
bool &INCR_READ, bool &INCR_WRITE,
DMA_CH7_CTRL_TRIG_RING_SIZE &RING_SIZE,
bool &RING_SEL, uint8_t &CHAIN_TO,
DMA_CH7_CTRL_TRIG_TREQ_SEL &TREQ_SEL,
bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN,
bool &BUSY, bool &WRITE_ERROR,
bool &READ_ERROR, bool &AHB_ERROR) volatile
{
uint32_t curr = CH7_CTRL_TRIG;
EN = curr & (1u << 0u);
HIGH_PRIORITY = curr & (1u << 1u);
DATA_SIZE = DMA_CH7_CTRL_TRIG_DATA_SIZE((curr >> 2u) & 0b11u);
INCR_READ = curr & (1u << 4u);
INCR_WRITE = curr & (1u << 5u);
RING_SIZE = DMA_CH7_CTRL_TRIG_RING_SIZE((curr >> 6u) & 0b1111u);
RING_SEL = curr & (1u << 10u);
CHAIN_TO = (curr >> 11u) & 0b1111u;
TREQ_SEL = DMA_CH7_CTRL_TRIG_TREQ_SEL((curr >> 15u) & 0b111111u);
IRQ_QUIET = curr & (1u << 21u);
BSWAP = curr & (1u << 22u);
SNIFF_EN = curr & (1u << 23u);
BUSY = curr & (1u << 24u);
WRITE_ERROR = curr & (1u << 29u);
READ_ERROR = curr & (1u << 30u);
AHB_ERROR = curr & (1u << 31u);
}
inline void set_CH7_CTRL_TRIG(bool EN, bool HIGH_PRIORITY,
DMA_CH7_CTRL_TRIG_DATA_SIZE DATA_SIZE,
bool INCR_READ, bool INCR_WRITE,
DMA_CH7_CTRL_TRIG_RING_SIZE RING_SIZE,
bool RING_SEL, uint8_t CHAIN_TO,
DMA_CH7_CTRL_TRIG_TREQ_SEL TREQ_SEL,
bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN,
bool WRITE_ERROR, bool READ_ERROR) volatile
{
uint32_t curr = CH7_CTRL_TRIG;
curr &= ~(0b1u << 0u);
curr |= (EN & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (HIGH_PRIORITY & 0b1u) << 1u;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
curr &= ~(0b1u << 4u);
curr |= (INCR_READ & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (INCR_WRITE & 0b1u) << 5u;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(RING_SIZE) & 0b1111u) << 6u;
curr &= ~(0b1u << 10u);
curr |= (RING_SEL & 0b1u) << 10u;
curr &= ~(0b1111u << 11u);
curr |= (CHAIN_TO & 0b1111u) << 11u;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
curr &= ~(0b1u << 21u);
curr |= (IRQ_QUIET & 0b1u) << 21u;
curr &= ~(0b1u << 22u);
curr |= (BSWAP & 0b1u) << 22u;
curr &= ~(0b1u << 23u);
curr |= (SNIFF_EN & 0b1u) << 23u;
curr &= ~(0b1u << 29u);
curr |= (WRITE_ERROR & 0b1u) << 29u;
curr &= ~(0b1u << 30u);
curr |= (READ_ERROR & 0b1u) << 30u;
CH7_CTRL_TRIG = curr;
}
inline bool get_CH8_CTRL_TRIG_EN() volatile
{
return CH8_CTRL_TRIG & (1u << 0u);
}
inline void set_CH8_CTRL_TRIG_EN() volatile
{
CH8_CTRL_TRIG |= 1u << 0u;
}
inline void clear_CH8_CTRL_TRIG_EN() volatile
{
CH8_CTRL_TRIG &= ~(1u << 0u);
}
inline void toggle_CH8_CTRL_TRIG_EN() volatile
{
CH8_CTRL_TRIG ^= 1u << 0u;
}
inline bool get_CH8_CTRL_TRIG_HIGH_PRIORITY() volatile
{
return CH8_CTRL_TRIG & (1u << 1u);
}
inline void set_CH8_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH8_CTRL_TRIG |= 1u << 1u;
}
inline void clear_CH8_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH8_CTRL_TRIG &= ~(1u << 1u);
}
inline void toggle_CH8_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH8_CTRL_TRIG ^= 1u << 1u;
}
inline DMA_CH8_CTRL_TRIG_DATA_SIZE get_CH8_CTRL_TRIG_DATA_SIZE() volatile
{
return DMA_CH8_CTRL_TRIG_DATA_SIZE((CH8_CTRL_TRIG >> 2u) & 0b11u);
}
inline void set_CH8_CTRL_TRIG_DATA_SIZE(
DMA_CH8_CTRL_TRIG_DATA_SIZE value) volatile
{
uint32_t curr = CH8_CTRL_TRIG;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(value) & 0b11u) << 2u;
CH8_CTRL_TRIG = curr;
}
inline bool get_CH8_CTRL_TRIG_INCR_READ() volatile
{
return CH8_CTRL_TRIG & (1u << 4u);
}
inline void set_CH8_CTRL_TRIG_INCR_READ() volatile
{
CH8_CTRL_TRIG |= 1u << 4u;
}
inline void clear_CH8_CTRL_TRIG_INCR_READ() volatile
{
CH8_CTRL_TRIG &= ~(1u << 4u);
}
inline void toggle_CH8_CTRL_TRIG_INCR_READ() volatile
{
CH8_CTRL_TRIG ^= 1u << 4u;
}
inline bool get_CH8_CTRL_TRIG_INCR_WRITE() volatile
{
return CH8_CTRL_TRIG & (1u << 5u);
}
inline void set_CH8_CTRL_TRIG_INCR_WRITE() volatile
{
CH8_CTRL_TRIG |= 1u << 5u;
}
inline void clear_CH8_CTRL_TRIG_INCR_WRITE() volatile
{
CH8_CTRL_TRIG &= ~(1u << 5u);
}
inline void toggle_CH8_CTRL_TRIG_INCR_WRITE() volatile
{
CH8_CTRL_TRIG ^= 1u << 5u;
}
inline DMA_CH8_CTRL_TRIG_RING_SIZE get_CH8_CTRL_TRIG_RING_SIZE() volatile
{
return DMA_CH8_CTRL_TRIG_RING_SIZE((CH8_CTRL_TRIG >> 6u) & 0b1111u);
}
inline void set_CH8_CTRL_TRIG_RING_SIZE(
DMA_CH8_CTRL_TRIG_RING_SIZE value) volatile
{
uint32_t curr = CH8_CTRL_TRIG;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(value) & 0b1111u) << 6u;
CH8_CTRL_TRIG = curr;
}
inline bool get_CH8_CTRL_TRIG_RING_SEL() volatile
{
return CH8_CTRL_TRIG & (1u << 10u);
}
inline void set_CH8_CTRL_TRIG_RING_SEL() volatile
{
CH8_CTRL_TRIG |= 1u << 10u;
}
inline void clear_CH8_CTRL_TRIG_RING_SEL() volatile
{
CH8_CTRL_TRIG &= ~(1u << 10u);
}
inline void toggle_CH8_CTRL_TRIG_RING_SEL() volatile
{
CH8_CTRL_TRIG ^= 1u << 10u;
}
inline uint8_t get_CH8_CTRL_TRIG_CHAIN_TO() volatile
{
return (CH8_CTRL_TRIG >> 11u) & 0b1111u;
}
inline void set_CH8_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile
{
uint32_t curr = CH8_CTRL_TRIG;
curr &= ~(0b1111u << 11u);
curr |= (value & 0b1111u) << 11u;
CH8_CTRL_TRIG = curr;
}
inline DMA_CH8_CTRL_TRIG_TREQ_SEL get_CH8_CTRL_TRIG_TREQ_SEL() volatile
{
return DMA_CH8_CTRL_TRIG_TREQ_SEL((CH8_CTRL_TRIG >> 15u) & 0b111111u);
}
inline void set_CH8_CTRL_TRIG_TREQ_SEL(
DMA_CH8_CTRL_TRIG_TREQ_SEL value) volatile
{
uint32_t curr = CH8_CTRL_TRIG;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(value) & 0b111111u) << 15u;
CH8_CTRL_TRIG = curr;
}
inline bool get_CH8_CTRL_TRIG_IRQ_QUIET() volatile
{
return CH8_CTRL_TRIG & (1u << 21u);
}
inline void set_CH8_CTRL_TRIG_IRQ_QUIET() volatile
{
CH8_CTRL_TRIG |= 1u << 21u;
}
inline void clear_CH8_CTRL_TRIG_IRQ_QUIET() volatile
{
CH8_CTRL_TRIG &= ~(1u << 21u);
}
inline void toggle_CH8_CTRL_TRIG_IRQ_QUIET() volatile
{
CH8_CTRL_TRIG ^= 1u << 21u;
}
inline bool get_CH8_CTRL_TRIG_BSWAP() volatile
{
return CH8_CTRL_TRIG & (1u << 22u);
}
inline void set_CH8_CTRL_TRIG_BSWAP() volatile
{
CH8_CTRL_TRIG |= 1u << 22u;
}
inline void clear_CH8_CTRL_TRIG_BSWAP() volatile
{
CH8_CTRL_TRIG &= ~(1u << 22u);
}
inline void toggle_CH8_CTRL_TRIG_BSWAP() volatile
{
CH8_CTRL_TRIG ^= 1u << 22u;
}
inline bool get_CH8_CTRL_TRIG_SNIFF_EN() volatile
{
return CH8_CTRL_TRIG & (1u << 23u);
}
inline void set_CH8_CTRL_TRIG_SNIFF_EN() volatile
{
CH8_CTRL_TRIG |= 1u << 23u;
}
inline void clear_CH8_CTRL_TRIG_SNIFF_EN() volatile
{
CH8_CTRL_TRIG &= ~(1u << 23u);
}
inline void toggle_CH8_CTRL_TRIG_SNIFF_EN() volatile
{
CH8_CTRL_TRIG ^= 1u << 23u;
}
inline bool get_CH8_CTRL_TRIG_BUSY() volatile
{
return CH8_CTRL_TRIG & (1u << 24u);
}
inline bool get_CH8_CTRL_TRIG_WRITE_ERROR() volatile
{
return CH8_CTRL_TRIG & (1u << 29u);
}
inline void set_CH8_CTRL_TRIG_WRITE_ERROR() volatile
{
CH8_CTRL_TRIG |= 1u << 29u;
}
inline void clear_CH8_CTRL_TRIG_WRITE_ERROR() volatile
{
CH8_CTRL_TRIG &= ~(1u << 29u);
}
inline void toggle_CH8_CTRL_TRIG_WRITE_ERROR() volatile
{
CH8_CTRL_TRIG ^= 1u << 29u;
}
inline bool get_CH8_CTRL_TRIG_READ_ERROR() volatile
{
return CH8_CTRL_TRIG & (1u << 30u);
}
inline void set_CH8_CTRL_TRIG_READ_ERROR() volatile
{
CH8_CTRL_TRIG |= 1u << 30u;
}
inline void clear_CH8_CTRL_TRIG_READ_ERROR() volatile
{
CH8_CTRL_TRIG &= ~(1u << 30u);
}
inline void toggle_CH8_CTRL_TRIG_READ_ERROR() volatile
{
CH8_CTRL_TRIG ^= 1u << 30u;
}
inline bool get_CH8_CTRL_TRIG_AHB_ERROR() volatile
{
return CH8_CTRL_TRIG & (1u << 31u);
}
inline void get_CH8_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY,
DMA_CH8_CTRL_TRIG_DATA_SIZE &DATA_SIZE,
bool &INCR_READ, bool &INCR_WRITE,
DMA_CH8_CTRL_TRIG_RING_SIZE &RING_SIZE,
bool &RING_SEL, uint8_t &CHAIN_TO,
DMA_CH8_CTRL_TRIG_TREQ_SEL &TREQ_SEL,
bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN,
bool &BUSY, bool &WRITE_ERROR,
bool &READ_ERROR, bool &AHB_ERROR) volatile
{
uint32_t curr = CH8_CTRL_TRIG;
EN = curr & (1u << 0u);
HIGH_PRIORITY = curr & (1u << 1u);
DATA_SIZE = DMA_CH8_CTRL_TRIG_DATA_SIZE((curr >> 2u) & 0b11u);
INCR_READ = curr & (1u << 4u);
INCR_WRITE = curr & (1u << 5u);
RING_SIZE = DMA_CH8_CTRL_TRIG_RING_SIZE((curr >> 6u) & 0b1111u);
RING_SEL = curr & (1u << 10u);
CHAIN_TO = (curr >> 11u) & 0b1111u;
TREQ_SEL = DMA_CH8_CTRL_TRIG_TREQ_SEL((curr >> 15u) & 0b111111u);
IRQ_QUIET = curr & (1u << 21u);
BSWAP = curr & (1u << 22u);
SNIFF_EN = curr & (1u << 23u);
BUSY = curr & (1u << 24u);
WRITE_ERROR = curr & (1u << 29u);
READ_ERROR = curr & (1u << 30u);
AHB_ERROR = curr & (1u << 31u);
}
inline void set_CH8_CTRL_TRIG(bool EN, bool HIGH_PRIORITY,
DMA_CH8_CTRL_TRIG_DATA_SIZE DATA_SIZE,
bool INCR_READ, bool INCR_WRITE,
DMA_CH8_CTRL_TRIG_RING_SIZE RING_SIZE,
bool RING_SEL, uint8_t CHAIN_TO,
DMA_CH8_CTRL_TRIG_TREQ_SEL TREQ_SEL,
bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN,
bool WRITE_ERROR, bool READ_ERROR) volatile
{
uint32_t curr = CH8_CTRL_TRIG;
curr &= ~(0b1u << 0u);
curr |= (EN & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (HIGH_PRIORITY & 0b1u) << 1u;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
curr &= ~(0b1u << 4u);
curr |= (INCR_READ & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (INCR_WRITE & 0b1u) << 5u;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(RING_SIZE) & 0b1111u) << 6u;
curr &= ~(0b1u << 10u);
curr |= (RING_SEL & 0b1u) << 10u;
curr &= ~(0b1111u << 11u);
curr |= (CHAIN_TO & 0b1111u) << 11u;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
curr &= ~(0b1u << 21u);
curr |= (IRQ_QUIET & 0b1u) << 21u;
curr &= ~(0b1u << 22u);
curr |= (BSWAP & 0b1u) << 22u;
curr &= ~(0b1u << 23u);
curr |= (SNIFF_EN & 0b1u) << 23u;
curr &= ~(0b1u << 29u);
curr |= (WRITE_ERROR & 0b1u) << 29u;
curr &= ~(0b1u << 30u);
curr |= (READ_ERROR & 0b1u) << 30u;
CH8_CTRL_TRIG = curr;
}
inline bool get_CH9_CTRL_TRIG_EN() volatile
{
return CH9_CTRL_TRIG & (1u << 0u);
}
inline void set_CH9_CTRL_TRIG_EN() volatile
{
CH9_CTRL_TRIG |= 1u << 0u;
}
inline void clear_CH9_CTRL_TRIG_EN() volatile
{
CH9_CTRL_TRIG &= ~(1u << 0u);
}
inline void toggle_CH9_CTRL_TRIG_EN() volatile
{
CH9_CTRL_TRIG ^= 1u << 0u;
}
inline bool get_CH9_CTRL_TRIG_HIGH_PRIORITY() volatile
{
return CH9_CTRL_TRIG & (1u << 1u);
}
inline void set_CH9_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH9_CTRL_TRIG |= 1u << 1u;
}
inline void clear_CH9_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH9_CTRL_TRIG &= ~(1u << 1u);
}
inline void toggle_CH9_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH9_CTRL_TRIG ^= 1u << 1u;
}
inline DMA_CH9_CTRL_TRIG_DATA_SIZE get_CH9_CTRL_TRIG_DATA_SIZE() volatile
{
return DMA_CH9_CTRL_TRIG_DATA_SIZE((CH9_CTRL_TRIG >> 2u) & 0b11u);
}
inline void set_CH9_CTRL_TRIG_DATA_SIZE(
DMA_CH9_CTRL_TRIG_DATA_SIZE value) volatile
{
uint32_t curr = CH9_CTRL_TRIG;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(value) & 0b11u) << 2u;
CH9_CTRL_TRIG = curr;
}
inline bool get_CH9_CTRL_TRIG_INCR_READ() volatile
{
return CH9_CTRL_TRIG & (1u << 4u);
}
inline void set_CH9_CTRL_TRIG_INCR_READ() volatile
{
CH9_CTRL_TRIG |= 1u << 4u;
}
inline void clear_CH9_CTRL_TRIG_INCR_READ() volatile
{
CH9_CTRL_TRIG &= ~(1u << 4u);
}
inline void toggle_CH9_CTRL_TRIG_INCR_READ() volatile
{
CH9_CTRL_TRIG ^= 1u << 4u;
}
inline bool get_CH9_CTRL_TRIG_INCR_WRITE() volatile
{
return CH9_CTRL_TRIG & (1u << 5u);
}
inline void set_CH9_CTRL_TRIG_INCR_WRITE() volatile
{
CH9_CTRL_TRIG |= 1u << 5u;
}
inline void clear_CH9_CTRL_TRIG_INCR_WRITE() volatile
{
CH9_CTRL_TRIG &= ~(1u << 5u);
}
inline void toggle_CH9_CTRL_TRIG_INCR_WRITE() volatile
{
CH9_CTRL_TRIG ^= 1u << 5u;
}
inline DMA_CH9_CTRL_TRIG_RING_SIZE get_CH9_CTRL_TRIG_RING_SIZE() volatile
{
return DMA_CH9_CTRL_TRIG_RING_SIZE((CH9_CTRL_TRIG >> 6u) & 0b1111u);
}
inline void set_CH9_CTRL_TRIG_RING_SIZE(
DMA_CH9_CTRL_TRIG_RING_SIZE value) volatile
{
uint32_t curr = CH9_CTRL_TRIG;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(value) & 0b1111u) << 6u;
CH9_CTRL_TRIG = curr;
}
inline bool get_CH9_CTRL_TRIG_RING_SEL() volatile
{
return CH9_CTRL_TRIG & (1u << 10u);
}
inline void set_CH9_CTRL_TRIG_RING_SEL() volatile
{
CH9_CTRL_TRIG |= 1u << 10u;
}
inline void clear_CH9_CTRL_TRIG_RING_SEL() volatile
{
CH9_CTRL_TRIG &= ~(1u << 10u);
}
inline void toggle_CH9_CTRL_TRIG_RING_SEL() volatile
{
CH9_CTRL_TRIG ^= 1u << 10u;
}
inline uint8_t get_CH9_CTRL_TRIG_CHAIN_TO() volatile
{
return (CH9_CTRL_TRIG >> 11u) & 0b1111u;
}
inline void set_CH9_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile
{
uint32_t curr = CH9_CTRL_TRIG;
curr &= ~(0b1111u << 11u);
curr |= (value & 0b1111u) << 11u;
CH9_CTRL_TRIG = curr;
}
inline DMA_CH9_CTRL_TRIG_TREQ_SEL get_CH9_CTRL_TRIG_TREQ_SEL() volatile
{
return DMA_CH9_CTRL_TRIG_TREQ_SEL((CH9_CTRL_TRIG >> 15u) & 0b111111u);
}
inline void set_CH9_CTRL_TRIG_TREQ_SEL(
DMA_CH9_CTRL_TRIG_TREQ_SEL value) volatile
{
uint32_t curr = CH9_CTRL_TRIG;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(value) & 0b111111u) << 15u;
CH9_CTRL_TRIG = curr;
}
inline bool get_CH9_CTRL_TRIG_IRQ_QUIET() volatile
{
return CH9_CTRL_TRIG & (1u << 21u);
}
inline void set_CH9_CTRL_TRIG_IRQ_QUIET() volatile
{
CH9_CTRL_TRIG |= 1u << 21u;
}
inline void clear_CH9_CTRL_TRIG_IRQ_QUIET() volatile
{
CH9_CTRL_TRIG &= ~(1u << 21u);
}
inline void toggle_CH9_CTRL_TRIG_IRQ_QUIET() volatile
{
CH9_CTRL_TRIG ^= 1u << 21u;
}
inline bool get_CH9_CTRL_TRIG_BSWAP() volatile
{
return CH9_CTRL_TRIG & (1u << 22u);
}
inline void set_CH9_CTRL_TRIG_BSWAP() volatile
{
CH9_CTRL_TRIG |= 1u << 22u;
}
inline void clear_CH9_CTRL_TRIG_BSWAP() volatile
{
CH9_CTRL_TRIG &= ~(1u << 22u);
}
inline void toggle_CH9_CTRL_TRIG_BSWAP() volatile
{
CH9_CTRL_TRIG ^= 1u << 22u;
}
inline bool get_CH9_CTRL_TRIG_SNIFF_EN() volatile
{
return CH9_CTRL_TRIG & (1u << 23u);
}
inline void set_CH9_CTRL_TRIG_SNIFF_EN() volatile
{
CH9_CTRL_TRIG |= 1u << 23u;
}
inline void clear_CH9_CTRL_TRIG_SNIFF_EN() volatile
{
CH9_CTRL_TRIG &= ~(1u << 23u);
}
inline void toggle_CH9_CTRL_TRIG_SNIFF_EN() volatile
{
CH9_CTRL_TRIG ^= 1u << 23u;
}
inline bool get_CH9_CTRL_TRIG_BUSY() volatile
{
return CH9_CTRL_TRIG & (1u << 24u);
}
inline bool get_CH9_CTRL_TRIG_WRITE_ERROR() volatile
{
return CH9_CTRL_TRIG & (1u << 29u);
}
inline void set_CH9_CTRL_TRIG_WRITE_ERROR() volatile
{
CH9_CTRL_TRIG |= 1u << 29u;
}
inline void clear_CH9_CTRL_TRIG_WRITE_ERROR() volatile
{
CH9_CTRL_TRIG &= ~(1u << 29u);
}
inline void toggle_CH9_CTRL_TRIG_WRITE_ERROR() volatile
{
CH9_CTRL_TRIG ^= 1u << 29u;
}
inline bool get_CH9_CTRL_TRIG_READ_ERROR() volatile
{
return CH9_CTRL_TRIG & (1u << 30u);
}
inline void set_CH9_CTRL_TRIG_READ_ERROR() volatile
{
CH9_CTRL_TRIG |= 1u << 30u;
}
inline void clear_CH9_CTRL_TRIG_READ_ERROR() volatile
{
CH9_CTRL_TRIG &= ~(1u << 30u);
}
inline void toggle_CH9_CTRL_TRIG_READ_ERROR() volatile
{
CH9_CTRL_TRIG ^= 1u << 30u;
}
inline bool get_CH9_CTRL_TRIG_AHB_ERROR() volatile
{
return CH9_CTRL_TRIG & (1u << 31u);
}
inline void get_CH9_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY,
DMA_CH9_CTRL_TRIG_DATA_SIZE &DATA_SIZE,
bool &INCR_READ, bool &INCR_WRITE,
DMA_CH9_CTRL_TRIG_RING_SIZE &RING_SIZE,
bool &RING_SEL, uint8_t &CHAIN_TO,
DMA_CH9_CTRL_TRIG_TREQ_SEL &TREQ_SEL,
bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN,
bool &BUSY, bool &WRITE_ERROR,
bool &READ_ERROR, bool &AHB_ERROR) volatile
{
uint32_t curr = CH9_CTRL_TRIG;
EN = curr & (1u << 0u);
HIGH_PRIORITY = curr & (1u << 1u);
DATA_SIZE = DMA_CH9_CTRL_TRIG_DATA_SIZE((curr >> 2u) & 0b11u);
INCR_READ = curr & (1u << 4u);
INCR_WRITE = curr & (1u << 5u);
RING_SIZE = DMA_CH9_CTRL_TRIG_RING_SIZE((curr >> 6u) & 0b1111u);
RING_SEL = curr & (1u << 10u);
CHAIN_TO = (curr >> 11u) & 0b1111u;
TREQ_SEL = DMA_CH9_CTRL_TRIG_TREQ_SEL((curr >> 15u) & 0b111111u);
IRQ_QUIET = curr & (1u << 21u);
BSWAP = curr & (1u << 22u);
SNIFF_EN = curr & (1u << 23u);
BUSY = curr & (1u << 24u);
WRITE_ERROR = curr & (1u << 29u);
READ_ERROR = curr & (1u << 30u);
AHB_ERROR = curr & (1u << 31u);
}
inline void set_CH9_CTRL_TRIG(bool EN, bool HIGH_PRIORITY,
DMA_CH9_CTRL_TRIG_DATA_SIZE DATA_SIZE,
bool INCR_READ, bool INCR_WRITE,
DMA_CH9_CTRL_TRIG_RING_SIZE RING_SIZE,
bool RING_SEL, uint8_t CHAIN_TO,
DMA_CH9_CTRL_TRIG_TREQ_SEL TREQ_SEL,
bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN,
bool WRITE_ERROR, bool READ_ERROR) volatile
{
uint32_t curr = CH9_CTRL_TRIG;
curr &= ~(0b1u << 0u);
curr |= (EN & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (HIGH_PRIORITY & 0b1u) << 1u;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
curr &= ~(0b1u << 4u);
curr |= (INCR_READ & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (INCR_WRITE & 0b1u) << 5u;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(RING_SIZE) & 0b1111u) << 6u;
curr &= ~(0b1u << 10u);
curr |= (RING_SEL & 0b1u) << 10u;
curr &= ~(0b1111u << 11u);
curr |= (CHAIN_TO & 0b1111u) << 11u;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
curr &= ~(0b1u << 21u);
curr |= (IRQ_QUIET & 0b1u) << 21u;
curr &= ~(0b1u << 22u);
curr |= (BSWAP & 0b1u) << 22u;
curr &= ~(0b1u << 23u);
curr |= (SNIFF_EN & 0b1u) << 23u;
curr &= ~(0b1u << 29u);
curr |= (WRITE_ERROR & 0b1u) << 29u;
curr &= ~(0b1u << 30u);
curr |= (READ_ERROR & 0b1u) << 30u;
CH9_CTRL_TRIG = curr;
}
inline bool get_CH10_CTRL_TRIG_EN() volatile
{
return CH10_CTRL_TRIG & (1u << 0u);
}
inline void set_CH10_CTRL_TRIG_EN() volatile
{
CH10_CTRL_TRIG |= 1u << 0u;
}
inline void clear_CH10_CTRL_TRIG_EN() volatile
{
CH10_CTRL_TRIG &= ~(1u << 0u);
}
inline void toggle_CH10_CTRL_TRIG_EN() volatile
{
CH10_CTRL_TRIG ^= 1u << 0u;
}
inline bool get_CH10_CTRL_TRIG_HIGH_PRIORITY() volatile
{
return CH10_CTRL_TRIG & (1u << 1u);
}
inline void set_CH10_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH10_CTRL_TRIG |= 1u << 1u;
}
inline void clear_CH10_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH10_CTRL_TRIG &= ~(1u << 1u);
}
inline void toggle_CH10_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH10_CTRL_TRIG ^= 1u << 1u;
}
inline DMA_CH10_CTRL_TRIG_DATA_SIZE get_CH10_CTRL_TRIG_DATA_SIZE() volatile
{
return DMA_CH10_CTRL_TRIG_DATA_SIZE((CH10_CTRL_TRIG >> 2u) & 0b11u);
}
inline void set_CH10_CTRL_TRIG_DATA_SIZE(
DMA_CH10_CTRL_TRIG_DATA_SIZE value) volatile
{
uint32_t curr = CH10_CTRL_TRIG;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(value) & 0b11u) << 2u;
CH10_CTRL_TRIG = curr;
}
inline bool get_CH10_CTRL_TRIG_INCR_READ() volatile
{
return CH10_CTRL_TRIG & (1u << 4u);
}
inline void set_CH10_CTRL_TRIG_INCR_READ() volatile
{
CH10_CTRL_TRIG |= 1u << 4u;
}
inline void clear_CH10_CTRL_TRIG_INCR_READ() volatile
{
CH10_CTRL_TRIG &= ~(1u << 4u);
}
inline void toggle_CH10_CTRL_TRIG_INCR_READ() volatile
{
CH10_CTRL_TRIG ^= 1u << 4u;
}
inline bool get_CH10_CTRL_TRIG_INCR_WRITE() volatile
{
return CH10_CTRL_TRIG & (1u << 5u);
}
inline void set_CH10_CTRL_TRIG_INCR_WRITE() volatile
{
CH10_CTRL_TRIG |= 1u << 5u;
}
inline void clear_CH10_CTRL_TRIG_INCR_WRITE() volatile
{
CH10_CTRL_TRIG &= ~(1u << 5u);
}
inline void toggle_CH10_CTRL_TRIG_INCR_WRITE() volatile
{
CH10_CTRL_TRIG ^= 1u << 5u;
}
inline DMA_CH10_CTRL_TRIG_RING_SIZE get_CH10_CTRL_TRIG_RING_SIZE() volatile
{
return DMA_CH10_CTRL_TRIG_RING_SIZE((CH10_CTRL_TRIG >> 6u) & 0b1111u);
}
inline void set_CH10_CTRL_TRIG_RING_SIZE(
DMA_CH10_CTRL_TRIG_RING_SIZE value) volatile
{
uint32_t curr = CH10_CTRL_TRIG;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(value) & 0b1111u) << 6u;
CH10_CTRL_TRIG = curr;
}
inline bool get_CH10_CTRL_TRIG_RING_SEL() volatile
{
return CH10_CTRL_TRIG & (1u << 10u);
}
inline void set_CH10_CTRL_TRIG_RING_SEL() volatile
{
CH10_CTRL_TRIG |= 1u << 10u;
}
inline void clear_CH10_CTRL_TRIG_RING_SEL() volatile
{
CH10_CTRL_TRIG &= ~(1u << 10u);
}
inline void toggle_CH10_CTRL_TRIG_RING_SEL() volatile
{
CH10_CTRL_TRIG ^= 1u << 10u;
}
inline uint8_t get_CH10_CTRL_TRIG_CHAIN_TO() volatile
{
return (CH10_CTRL_TRIG >> 11u) & 0b1111u;
}
inline void set_CH10_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile
{
uint32_t curr = CH10_CTRL_TRIG;
curr &= ~(0b1111u << 11u);
curr |= (value & 0b1111u) << 11u;
CH10_CTRL_TRIG = curr;
}
inline DMA_CH10_CTRL_TRIG_TREQ_SEL get_CH10_CTRL_TRIG_TREQ_SEL() volatile
{
return DMA_CH10_CTRL_TRIG_TREQ_SEL((CH10_CTRL_TRIG >> 15u) &
0b111111u);
}
inline void set_CH10_CTRL_TRIG_TREQ_SEL(
DMA_CH10_CTRL_TRIG_TREQ_SEL value) volatile
{
uint32_t curr = CH10_CTRL_TRIG;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(value) & 0b111111u) << 15u;
CH10_CTRL_TRIG = curr;
}
inline bool get_CH10_CTRL_TRIG_IRQ_QUIET() volatile
{
return CH10_CTRL_TRIG & (1u << 21u);
}
inline void set_CH10_CTRL_TRIG_IRQ_QUIET() volatile
{
CH10_CTRL_TRIG |= 1u << 21u;
}
inline void clear_CH10_CTRL_TRIG_IRQ_QUIET() volatile
{
CH10_CTRL_TRIG &= ~(1u << 21u);
}
inline void toggle_CH10_CTRL_TRIG_IRQ_QUIET() volatile
{
CH10_CTRL_TRIG ^= 1u << 21u;
}
inline bool get_CH10_CTRL_TRIG_BSWAP() volatile
{
return CH10_CTRL_TRIG & (1u << 22u);
}
inline void set_CH10_CTRL_TRIG_BSWAP() volatile
{
CH10_CTRL_TRIG |= 1u << 22u;
}
inline void clear_CH10_CTRL_TRIG_BSWAP() volatile
{
CH10_CTRL_TRIG &= ~(1u << 22u);
}
inline void toggle_CH10_CTRL_TRIG_BSWAP() volatile
{
CH10_CTRL_TRIG ^= 1u << 22u;
}
inline bool get_CH10_CTRL_TRIG_SNIFF_EN() volatile
{
return CH10_CTRL_TRIG & (1u << 23u);
}
inline void set_CH10_CTRL_TRIG_SNIFF_EN() volatile
{
CH10_CTRL_TRIG |= 1u << 23u;
}
inline void clear_CH10_CTRL_TRIG_SNIFF_EN() volatile
{
CH10_CTRL_TRIG &= ~(1u << 23u);
}
inline void toggle_CH10_CTRL_TRIG_SNIFF_EN() volatile
{
CH10_CTRL_TRIG ^= 1u << 23u;
}
inline bool get_CH10_CTRL_TRIG_BUSY() volatile
{
return CH10_CTRL_TRIG & (1u << 24u);
}
inline bool get_CH10_CTRL_TRIG_WRITE_ERROR() volatile
{
return CH10_CTRL_TRIG & (1u << 29u);
}
inline void set_CH10_CTRL_TRIG_WRITE_ERROR() volatile
{
CH10_CTRL_TRIG |= 1u << 29u;
}
inline void clear_CH10_CTRL_TRIG_WRITE_ERROR() volatile
{
CH10_CTRL_TRIG &= ~(1u << 29u);
}
inline void toggle_CH10_CTRL_TRIG_WRITE_ERROR() volatile
{
CH10_CTRL_TRIG ^= 1u << 29u;
}
inline bool get_CH10_CTRL_TRIG_READ_ERROR() volatile
{
return CH10_CTRL_TRIG & (1u << 30u);
}
inline void set_CH10_CTRL_TRIG_READ_ERROR() volatile
{
CH10_CTRL_TRIG |= 1u << 30u;
}
inline void clear_CH10_CTRL_TRIG_READ_ERROR() volatile
{
CH10_CTRL_TRIG &= ~(1u << 30u);
}
inline void toggle_CH10_CTRL_TRIG_READ_ERROR() volatile
{
CH10_CTRL_TRIG ^= 1u << 30u;
}
inline bool get_CH10_CTRL_TRIG_AHB_ERROR() volatile
{
return CH10_CTRL_TRIG & (1u << 31u);
}
inline void get_CH10_CTRL_TRIG(
bool &EN, bool &HIGH_PRIORITY, DMA_CH10_CTRL_TRIG_DATA_SIZE &DATA_SIZE,
bool &INCR_READ, bool &INCR_WRITE,
DMA_CH10_CTRL_TRIG_RING_SIZE &RING_SIZE, bool &RING_SEL,
uint8_t &CHAIN_TO, DMA_CH10_CTRL_TRIG_TREQ_SEL &TREQ_SEL,
bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY,
bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR) volatile
{
uint32_t curr = CH10_CTRL_TRIG;
EN = curr & (1u << 0u);
HIGH_PRIORITY = curr & (1u << 1u);
DATA_SIZE = DMA_CH10_CTRL_TRIG_DATA_SIZE((curr >> 2u) & 0b11u);
INCR_READ = curr & (1u << 4u);
INCR_WRITE = curr & (1u << 5u);
RING_SIZE = DMA_CH10_CTRL_TRIG_RING_SIZE((curr >> 6u) & 0b1111u);
RING_SEL = curr & (1u << 10u);
CHAIN_TO = (curr >> 11u) & 0b1111u;
TREQ_SEL = DMA_CH10_CTRL_TRIG_TREQ_SEL((curr >> 15u) & 0b111111u);
IRQ_QUIET = curr & (1u << 21u);
BSWAP = curr & (1u << 22u);
SNIFF_EN = curr & (1u << 23u);
BUSY = curr & (1u << 24u);
WRITE_ERROR = curr & (1u << 29u);
READ_ERROR = curr & (1u << 30u);
AHB_ERROR = curr & (1u << 31u);
}
inline void set_CH10_CTRL_TRIG(bool EN, bool HIGH_PRIORITY,
DMA_CH10_CTRL_TRIG_DATA_SIZE DATA_SIZE,
bool INCR_READ, bool INCR_WRITE,
DMA_CH10_CTRL_TRIG_RING_SIZE RING_SIZE,
bool RING_SEL, uint8_t CHAIN_TO,
DMA_CH10_CTRL_TRIG_TREQ_SEL TREQ_SEL,
bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN,
bool WRITE_ERROR, bool READ_ERROR) volatile
{
uint32_t curr = CH10_CTRL_TRIG;
curr &= ~(0b1u << 0u);
curr |= (EN & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (HIGH_PRIORITY & 0b1u) << 1u;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
curr &= ~(0b1u << 4u);
curr |= (INCR_READ & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (INCR_WRITE & 0b1u) << 5u;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(RING_SIZE) & 0b1111u) << 6u;
curr &= ~(0b1u << 10u);
curr |= (RING_SEL & 0b1u) << 10u;
curr &= ~(0b1111u << 11u);
curr |= (CHAIN_TO & 0b1111u) << 11u;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
curr &= ~(0b1u << 21u);
curr |= (IRQ_QUIET & 0b1u) << 21u;
curr &= ~(0b1u << 22u);
curr |= (BSWAP & 0b1u) << 22u;
curr &= ~(0b1u << 23u);
curr |= (SNIFF_EN & 0b1u) << 23u;
curr &= ~(0b1u << 29u);
curr |= (WRITE_ERROR & 0b1u) << 29u;
curr &= ~(0b1u << 30u);
curr |= (READ_ERROR & 0b1u) << 30u;
CH10_CTRL_TRIG = curr;
}
inline bool get_CH11_CTRL_TRIG_EN() volatile
{
return CH11_CTRL_TRIG & (1u << 0u);
}
inline void set_CH11_CTRL_TRIG_EN() volatile
{
CH11_CTRL_TRIG |= 1u << 0u;
}
inline void clear_CH11_CTRL_TRIG_EN() volatile
{
CH11_CTRL_TRIG &= ~(1u << 0u);
}
inline void toggle_CH11_CTRL_TRIG_EN() volatile
{
CH11_CTRL_TRIG ^= 1u << 0u;
}
inline bool get_CH11_CTRL_TRIG_HIGH_PRIORITY() volatile
{
return CH11_CTRL_TRIG & (1u << 1u);
}
inline void set_CH11_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH11_CTRL_TRIG |= 1u << 1u;
}
inline void clear_CH11_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH11_CTRL_TRIG &= ~(1u << 1u);
}
inline void toggle_CH11_CTRL_TRIG_HIGH_PRIORITY() volatile
{
CH11_CTRL_TRIG ^= 1u << 1u;
}
inline DMA_CH11_CTRL_TRIG_DATA_SIZE get_CH11_CTRL_TRIG_DATA_SIZE() volatile
{
return DMA_CH11_CTRL_TRIG_DATA_SIZE((CH11_CTRL_TRIG >> 2u) & 0b11u);
}
inline void set_CH11_CTRL_TRIG_DATA_SIZE(
DMA_CH11_CTRL_TRIG_DATA_SIZE value) volatile
{
uint32_t curr = CH11_CTRL_TRIG;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(value) & 0b11u) << 2u;
CH11_CTRL_TRIG = curr;
}
inline bool get_CH11_CTRL_TRIG_INCR_READ() volatile
{
return CH11_CTRL_TRIG & (1u << 4u);
}
inline void set_CH11_CTRL_TRIG_INCR_READ() volatile
{
CH11_CTRL_TRIG |= 1u << 4u;
}
inline void clear_CH11_CTRL_TRIG_INCR_READ() volatile
{
CH11_CTRL_TRIG &= ~(1u << 4u);
}
inline void toggle_CH11_CTRL_TRIG_INCR_READ() volatile
{
CH11_CTRL_TRIG ^= 1u << 4u;
}
inline bool get_CH11_CTRL_TRIG_INCR_WRITE() volatile
{
return CH11_CTRL_TRIG & (1u << 5u);
}
inline void set_CH11_CTRL_TRIG_INCR_WRITE() volatile
{
CH11_CTRL_TRIG |= 1u << 5u;
}
inline void clear_CH11_CTRL_TRIG_INCR_WRITE() volatile
{
CH11_CTRL_TRIG &= ~(1u << 5u);
}
inline void toggle_CH11_CTRL_TRIG_INCR_WRITE() volatile
{
CH11_CTRL_TRIG ^= 1u << 5u;
}
inline DMA_CH11_CTRL_TRIG_RING_SIZE get_CH11_CTRL_TRIG_RING_SIZE() volatile
{
return DMA_CH11_CTRL_TRIG_RING_SIZE((CH11_CTRL_TRIG >> 6u) & 0b1111u);
}
inline void set_CH11_CTRL_TRIG_RING_SIZE(
DMA_CH11_CTRL_TRIG_RING_SIZE value) volatile
{
uint32_t curr = CH11_CTRL_TRIG;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(value) & 0b1111u) << 6u;
CH11_CTRL_TRIG = curr;
}
inline bool get_CH11_CTRL_TRIG_RING_SEL() volatile
{
return CH11_CTRL_TRIG & (1u << 10u);
}
inline void set_CH11_CTRL_TRIG_RING_SEL() volatile
{
CH11_CTRL_TRIG |= 1u << 10u;
}
inline void clear_CH11_CTRL_TRIG_RING_SEL() volatile
{
CH11_CTRL_TRIG &= ~(1u << 10u);
}
inline void toggle_CH11_CTRL_TRIG_RING_SEL() volatile
{
CH11_CTRL_TRIG ^= 1u << 10u;
}
inline uint8_t get_CH11_CTRL_TRIG_CHAIN_TO() volatile
{
return (CH11_CTRL_TRIG >> 11u) & 0b1111u;
}
inline void set_CH11_CTRL_TRIG_CHAIN_TO(uint8_t value) volatile
{
uint32_t curr = CH11_CTRL_TRIG;
curr &= ~(0b1111u << 11u);
curr |= (value & 0b1111u) << 11u;
CH11_CTRL_TRIG = curr;
}
inline DMA_CH11_CTRL_TRIG_TREQ_SEL get_CH11_CTRL_TRIG_TREQ_SEL() volatile
{
return DMA_CH11_CTRL_TRIG_TREQ_SEL((CH11_CTRL_TRIG >> 15u) &
0b111111u);
}
inline void set_CH11_CTRL_TRIG_TREQ_SEL(
DMA_CH11_CTRL_TRIG_TREQ_SEL value) volatile
{
uint32_t curr = CH11_CTRL_TRIG;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(value) & 0b111111u) << 15u;
CH11_CTRL_TRIG = curr;
}
inline bool get_CH11_CTRL_TRIG_IRQ_QUIET() volatile
{
return CH11_CTRL_TRIG & (1u << 21u);
}
inline void set_CH11_CTRL_TRIG_IRQ_QUIET() volatile
{
CH11_CTRL_TRIG |= 1u << 21u;
}
inline void clear_CH11_CTRL_TRIG_IRQ_QUIET() volatile
{
CH11_CTRL_TRIG &= ~(1u << 21u);
}
inline void toggle_CH11_CTRL_TRIG_IRQ_QUIET() volatile
{
CH11_CTRL_TRIG ^= 1u << 21u;
}
inline bool get_CH11_CTRL_TRIG_BSWAP() volatile
{
return CH11_CTRL_TRIG & (1u << 22u);
}
inline void set_CH11_CTRL_TRIG_BSWAP() volatile
{
CH11_CTRL_TRIG |= 1u << 22u;
}
inline void clear_CH11_CTRL_TRIG_BSWAP() volatile
{
CH11_CTRL_TRIG &= ~(1u << 22u);
}
inline void toggle_CH11_CTRL_TRIG_BSWAP() volatile
{
CH11_CTRL_TRIG ^= 1u << 22u;
}
inline bool get_CH11_CTRL_TRIG_SNIFF_EN() volatile
{
return CH11_CTRL_TRIG & (1u << 23u);
}
inline void set_CH11_CTRL_TRIG_SNIFF_EN() volatile
{
CH11_CTRL_TRIG |= 1u << 23u;
}
inline void clear_CH11_CTRL_TRIG_SNIFF_EN() volatile
{
CH11_CTRL_TRIG &= ~(1u << 23u);
}
inline void toggle_CH11_CTRL_TRIG_SNIFF_EN() volatile
{
CH11_CTRL_TRIG ^= 1u << 23u;
}
inline bool get_CH11_CTRL_TRIG_BUSY() volatile
{
return CH11_CTRL_TRIG & (1u << 24u);
}
inline bool get_CH11_CTRL_TRIG_WRITE_ERROR() volatile
{
return CH11_CTRL_TRIG & (1u << 29u);
}
inline void set_CH11_CTRL_TRIG_WRITE_ERROR() volatile
{
CH11_CTRL_TRIG |= 1u << 29u;
}
inline void clear_CH11_CTRL_TRIG_WRITE_ERROR() volatile
{
CH11_CTRL_TRIG &= ~(1u << 29u);
}
inline void toggle_CH11_CTRL_TRIG_WRITE_ERROR() volatile
{
CH11_CTRL_TRIG ^= 1u << 29u;
}
inline bool get_CH11_CTRL_TRIG_READ_ERROR() volatile
{
return CH11_CTRL_TRIG & (1u << 30u);
}
inline void set_CH11_CTRL_TRIG_READ_ERROR() volatile
{
CH11_CTRL_TRIG |= 1u << 30u;
}
inline void clear_CH11_CTRL_TRIG_READ_ERROR() volatile
{
CH11_CTRL_TRIG &= ~(1u << 30u);
}
inline void toggle_CH11_CTRL_TRIG_READ_ERROR() volatile
{
CH11_CTRL_TRIG ^= 1u << 30u;
}
inline bool get_CH11_CTRL_TRIG_AHB_ERROR() volatile
{
return CH11_CTRL_TRIG & (1u << 31u);
}
inline void get_CH11_CTRL_TRIG(
bool &EN, bool &HIGH_PRIORITY, DMA_CH11_CTRL_TRIG_DATA_SIZE &DATA_SIZE,
bool &INCR_READ, bool &INCR_WRITE,
DMA_CH11_CTRL_TRIG_RING_SIZE &RING_SIZE, bool &RING_SEL,
uint8_t &CHAIN_TO, DMA_CH11_CTRL_TRIG_TREQ_SEL &TREQ_SEL,
bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY,
bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR) volatile
{
uint32_t curr = CH11_CTRL_TRIG;
EN = curr & (1u << 0u);
HIGH_PRIORITY = curr & (1u << 1u);
DATA_SIZE = DMA_CH11_CTRL_TRIG_DATA_SIZE((curr >> 2u) & 0b11u);
INCR_READ = curr & (1u << 4u);
INCR_WRITE = curr & (1u << 5u);
RING_SIZE = DMA_CH11_CTRL_TRIG_RING_SIZE((curr >> 6u) & 0b1111u);
RING_SEL = curr & (1u << 10u);
CHAIN_TO = (curr >> 11u) & 0b1111u;
TREQ_SEL = DMA_CH11_CTRL_TRIG_TREQ_SEL((curr >> 15u) & 0b111111u);
IRQ_QUIET = curr & (1u << 21u);
BSWAP = curr & (1u << 22u);
SNIFF_EN = curr & (1u << 23u);
BUSY = curr & (1u << 24u);
WRITE_ERROR = curr & (1u << 29u);
READ_ERROR = curr & (1u << 30u);
AHB_ERROR = curr & (1u << 31u);
}
inline void set_CH11_CTRL_TRIG(bool EN, bool HIGH_PRIORITY,
DMA_CH11_CTRL_TRIG_DATA_SIZE DATA_SIZE,
bool INCR_READ, bool INCR_WRITE,
DMA_CH11_CTRL_TRIG_RING_SIZE RING_SIZE,
bool RING_SEL, uint8_t CHAIN_TO,
DMA_CH11_CTRL_TRIG_TREQ_SEL TREQ_SEL,
bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN,
bool WRITE_ERROR, bool READ_ERROR) volatile
{
uint32_t curr = CH11_CTRL_TRIG;
curr &= ~(0b1u << 0u);
curr |= (EN & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (HIGH_PRIORITY & 0b1u) << 1u;
curr &= ~(0b11u << 2u);
curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
curr &= ~(0b1u << 4u);
curr |= (INCR_READ & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (INCR_WRITE & 0b1u) << 5u;
curr &= ~(0b1111u << 6u);
curr |= (std::to_underlying(RING_SIZE) & 0b1111u) << 6u;
curr &= ~(0b1u << 10u);
curr |= (RING_SEL & 0b1u) << 10u;
curr &= ~(0b1111u << 11u);
curr |= (CHAIN_TO & 0b1111u) << 11u;
curr &= ~(0b111111u << 15u);
curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
curr &= ~(0b1u << 21u);
curr |= (IRQ_QUIET & 0b1u) << 21u;
curr &= ~(0b1u << 22u);
curr |= (BSWAP & 0b1u) << 22u;
curr &= ~(0b1u << 23u);
curr |= (SNIFF_EN & 0b1u) << 23u;
curr &= ~(0b1u << 29u);
curr |= (WRITE_ERROR & 0b1u) << 29u;
curr &= ~(0b1u << 30u);
curr |= (READ_ERROR & 0b1u) << 30u;
CH11_CTRL_TRIG = curr;
}
inline uint16_t get_INTR_INTR() volatile
{
return (INTR >> 0u) & 0b1111111111111111u;
}
inline void set_INTR_INTR(uint16_t value) volatile
{
uint32_t curr = INTR;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
INTR = curr;
}
inline uint16_t get_INTE0_INTE0() volatile
{
return (INTE0 >> 0u) & 0b1111111111111111u;
}
inline void set_INTE0_INTE0(uint16_t value) volatile
{
uint32_t curr = INTE0;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
INTE0 = curr;
}
inline uint16_t get_INTF0_INTF0() volatile
{
return (INTF0 >> 0u) & 0b1111111111111111u;
}
inline void set_INTF0_INTF0(uint16_t value) volatile
{
uint32_t curr = INTF0;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
INTF0 = curr;
}
inline uint16_t get_INTS0_INTS0() volatile
{
return (INTS0 >> 0u) & 0b1111111111111111u;
}
inline void set_INTS0_INTS0(uint16_t value) volatile
{
uint32_t curr = INTS0;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
INTS0 = curr;
}
inline uint16_t get_INTE1_INTE1() volatile
{
return (INTE1 >> 0u) & 0b1111111111111111u;
}
inline void set_INTE1_INTE1(uint16_t value) volatile
{
uint32_t curr = INTE1;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
INTE1 = curr;
}
inline uint16_t get_INTF1_INTF1() volatile
{
return (INTF1 >> 0u) & 0b1111111111111111u;
}
inline void set_INTF1_INTF1(uint16_t value) volatile
{
uint32_t curr = INTF1;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
INTF1 = curr;
}
inline uint16_t get_INTS1_INTS1() volatile
{
return (INTS1 >> 0u) & 0b1111111111111111u;
}
inline void set_INTS1_INTS1(uint16_t value) volatile
{
uint32_t curr = INTS1;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
INTS1 = curr;
}
inline uint16_t get_TIMER0_Y() volatile
{
return (TIMER0 >> 0u) & 0b1111111111111111u;
}
inline void set_TIMER0_Y(uint16_t value) volatile
{
uint32_t curr = TIMER0;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
TIMER0 = curr;
}
inline uint16_t get_TIMER0_X() volatile
{
return (TIMER0 >> 16u) & 0b1111111111111111u;
}
inline void set_TIMER0_X(uint16_t value) volatile
{
uint32_t curr = TIMER0;
curr &= ~(0b1111111111111111u << 16u);
curr |= (value & 0b1111111111111111u) << 16u;
TIMER0 = curr;
}
inline void get_TIMER0(uint16_t &Y, uint16_t &X) volatile
{
uint32_t curr = TIMER0;
Y = (curr >> 0u) & 0b1111111111111111u;
X = (curr >> 16u) & 0b1111111111111111u;
}
inline void set_TIMER0(uint16_t Y, uint16_t X) volatile
{
uint32_t curr = TIMER0;
curr &= ~(0b1111111111111111u << 0u);
curr |= (Y & 0b1111111111111111u) << 0u;
curr &= ~(0b1111111111111111u << 16u);
curr |= (X & 0b1111111111111111u) << 16u;
TIMER0 = curr;
}
inline uint16_t get_TIMER1_Y() volatile
{
return (TIMER1 >> 0u) & 0b1111111111111111u;
}
inline void set_TIMER1_Y(uint16_t value) volatile
{
uint32_t curr = TIMER1;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
TIMER1 = curr;
}
inline uint16_t get_TIMER1_X() volatile
{
return (TIMER1 >> 16u) & 0b1111111111111111u;
}
inline void set_TIMER1_X(uint16_t value) volatile
{
uint32_t curr = TIMER1;
curr &= ~(0b1111111111111111u << 16u);
curr |= (value & 0b1111111111111111u) << 16u;
TIMER1 = curr;
}
inline void get_TIMER1(uint16_t &Y, uint16_t &X) volatile
{
uint32_t curr = TIMER1;
Y = (curr >> 0u) & 0b1111111111111111u;
X = (curr >> 16u) & 0b1111111111111111u;
}
inline void set_TIMER1(uint16_t Y, uint16_t X) volatile
{
uint32_t curr = TIMER1;
curr &= ~(0b1111111111111111u << 0u);
curr |= (Y & 0b1111111111111111u) << 0u;
curr &= ~(0b1111111111111111u << 16u);
curr |= (X & 0b1111111111111111u) << 16u;
TIMER1 = curr;
}
inline uint16_t get_TIMER2_Y() volatile
{
return (TIMER2 >> 0u) & 0b1111111111111111u;
}
inline void set_TIMER2_Y(uint16_t value) volatile
{
uint32_t curr = TIMER2;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
TIMER2 = curr;
}
inline uint16_t get_TIMER2_X() volatile
{
return (TIMER2 >> 16u) & 0b1111111111111111u;
}
inline void set_TIMER2_X(uint16_t value) volatile
{
uint32_t curr = TIMER2;
curr &= ~(0b1111111111111111u << 16u);
curr |= (value & 0b1111111111111111u) << 16u;
TIMER2 = curr;
}
inline void get_TIMER2(uint16_t &Y, uint16_t &X) volatile
{
uint32_t curr = TIMER2;
Y = (curr >> 0u) & 0b1111111111111111u;
X = (curr >> 16u) & 0b1111111111111111u;
}
inline void set_TIMER2(uint16_t Y, uint16_t X) volatile
{
uint32_t curr = TIMER2;
curr &= ~(0b1111111111111111u << 0u);
curr |= (Y & 0b1111111111111111u) << 0u;
curr &= ~(0b1111111111111111u << 16u);
curr |= (X & 0b1111111111111111u) << 16u;
TIMER2 = curr;
}
inline uint16_t get_TIMER3_Y() volatile
{
return (TIMER3 >> 0u) & 0b1111111111111111u;
}
inline void set_TIMER3_Y(uint16_t value) volatile
{
uint32_t curr = TIMER3;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
TIMER3 = curr;
}
inline uint16_t get_TIMER3_X() volatile
{
return (TIMER3 >> 16u) & 0b1111111111111111u;
}
inline void set_TIMER3_X(uint16_t value) volatile
{
uint32_t curr = TIMER3;
curr &= ~(0b1111111111111111u << 16u);
curr |= (value & 0b1111111111111111u) << 16u;
TIMER3 = curr;
}
inline void get_TIMER3(uint16_t &Y, uint16_t &X) volatile
{
uint32_t curr = TIMER3;
Y = (curr >> 0u) & 0b1111111111111111u;
X = (curr >> 16u) & 0b1111111111111111u;
}
inline void set_TIMER3(uint16_t Y, uint16_t X) volatile
{
uint32_t curr = TIMER3;
curr &= ~(0b1111111111111111u << 0u);
curr |= (Y & 0b1111111111111111u) << 0u;
curr &= ~(0b1111111111111111u << 16u);
curr |= (X & 0b1111111111111111u) << 16u;
TIMER3 = curr;
}
inline uint16_t get_MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER() volatile
{
return (MULTI_CHAN_TRIGGER >> 0u) & 0b1111111111111111u;
}
inline void set_MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER(
uint16_t value) volatile
{
uint32_t curr = MULTI_CHAN_TRIGGER;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
MULTI_CHAN_TRIGGER = curr;
}
inline bool get_SNIFF_CTRL_EN() volatile
{
return SNIFF_CTRL & (1u << 0u);
}
inline void set_SNIFF_CTRL_EN() volatile
{
SNIFF_CTRL |= 1u << 0u;
}
inline void clear_SNIFF_CTRL_EN() volatile
{
SNIFF_CTRL &= ~(1u << 0u);
}
inline void toggle_SNIFF_CTRL_EN() volatile
{
SNIFF_CTRL ^= 1u << 0u;
}
inline uint8_t get_SNIFF_CTRL_DMACH() volatile
{
return (SNIFF_CTRL >> 1u) & 0b1111u;
}
inline void set_SNIFF_CTRL_DMACH(uint8_t value) volatile
{
uint32_t curr = SNIFF_CTRL;
curr &= ~(0b1111u << 1u);
curr |= (value & 0b1111u) << 1u;
SNIFF_CTRL = curr;
}
inline DMA_SNIFF_CTRL_CALC get_SNIFF_CTRL_CALC() volatile
{
return DMA_SNIFF_CTRL_CALC((SNIFF_CTRL >> 5u) & 0b1111u);
}
inline void set_SNIFF_CTRL_CALC(DMA_SNIFF_CTRL_CALC value) volatile
{
uint32_t curr = SNIFF_CTRL;
curr &= ~(0b1111u << 5u);
curr |= (std::to_underlying(value) & 0b1111u) << 5u;
SNIFF_CTRL = curr;
}
inline bool get_SNIFF_CTRL_BSWAP() volatile
{
return SNIFF_CTRL & (1u << 9u);
}
inline void set_SNIFF_CTRL_BSWAP() volatile
{
SNIFF_CTRL |= 1u << 9u;
}
inline void clear_SNIFF_CTRL_BSWAP() volatile
{
SNIFF_CTRL &= ~(1u << 9u);
}
inline void toggle_SNIFF_CTRL_BSWAP() volatile
{
SNIFF_CTRL ^= 1u << 9u;
}
inline bool get_SNIFF_CTRL_OUT_REV() volatile
{
return SNIFF_CTRL & (1u << 10u);
}
inline void set_SNIFF_CTRL_OUT_REV() volatile
{
SNIFF_CTRL |= 1u << 10u;
}
inline void clear_SNIFF_CTRL_OUT_REV() volatile
{
SNIFF_CTRL &= ~(1u << 10u);
}
inline void toggle_SNIFF_CTRL_OUT_REV() volatile
{
SNIFF_CTRL ^= 1u << 10u;
}
inline bool get_SNIFF_CTRL_OUT_INV() volatile
{
return SNIFF_CTRL & (1u << 11u);
}
inline void set_SNIFF_CTRL_OUT_INV() volatile
{
SNIFF_CTRL |= 1u << 11u;
}
inline void clear_SNIFF_CTRL_OUT_INV() volatile
{
SNIFF_CTRL &= ~(1u << 11u);
}
inline void toggle_SNIFF_CTRL_OUT_INV() volatile
{
SNIFF_CTRL ^= 1u << 11u;
}
inline void get_SNIFF_CTRL(bool &EN, uint8_t &DMACH,
DMA_SNIFF_CTRL_CALC &CALC, bool &BSWAP,
bool &OUT_REV, bool &OUT_INV) volatile
{
uint32_t curr = SNIFF_CTRL;
EN = curr & (1u << 0u);
DMACH = (curr >> 1u) & 0b1111u;
CALC = DMA_SNIFF_CTRL_CALC((curr >> 5u) & 0b1111u);
BSWAP = curr & (1u << 9u);
OUT_REV = curr & (1u << 10u);
OUT_INV = curr & (1u << 11u);
}
inline void set_SNIFF_CTRL(bool EN, uint8_t DMACH,
DMA_SNIFF_CTRL_CALC CALC, bool BSWAP,
bool OUT_REV, bool OUT_INV) volatile
{
uint32_t curr = SNIFF_CTRL;
curr &= ~(0b1u << 0u);
curr |= (EN & 0b1u) << 0u;
curr &= ~(0b1111u << 1u);
curr |= (DMACH & 0b1111u) << 1u;
curr &= ~(0b1111u << 5u);
curr |= (std::to_underlying(CALC) & 0b1111u) << 5u;
curr &= ~(0b1u << 9u);
curr |= (BSWAP & 0b1u) << 9u;
curr &= ~(0b1u << 10u);
curr |= (OUT_REV & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (OUT_INV & 0b1u) << 11u;
SNIFF_CTRL = curr;
}
inline uint8_t get_FIFO_LEVELS_TDF_LVL() volatile
{
return (FIFO_LEVELS >> 0u) & 0b11111111u;
}
inline uint8_t get_FIFO_LEVELS_WAF_LVL() volatile
{
return (FIFO_LEVELS >> 8u) & 0b11111111u;
}
inline uint8_t get_FIFO_LEVELS_RAF_LVL() volatile
{
return (FIFO_LEVELS >> 16u) & 0b11111111u;
}
inline void get_FIFO_LEVELS(uint8_t &TDF_LVL, uint8_t &WAF_LVL,
uint8_t &RAF_LVL) volatile
{
uint32_t curr = FIFO_LEVELS;
TDF_LVL = (curr >> 0u) & 0b11111111u;
WAF_LVL = (curr >> 8u) & 0b11111111u;
RAF_LVL = (curr >> 16u) & 0b11111111u;
}
inline uint16_t get_CHAN_ABORT_CHAN_ABORT() volatile
{
return (CHAN_ABORT >> 0u) & 0b1111111111111111u;
}
inline void set_CHAN_ABORT_CHAN_ABORT(uint16_t value) volatile
{
uint32_t curr = CHAN_ABORT;
curr &= ~(0b1111111111111111u << 0u);
curr |= (value & 0b1111111111111111u) << 0u;
CHAN_ABORT = curr;
}
inline uint8_t get_N_CHANNELS_N_CHANNELS() volatile
{
return (N_CHANNELS >> 0u) & 0b11111u;
}
inline uint8_t get_CH0_DBG_CTDREQ_CH0_DBG_CTDREQ() volatile
{
return (CH0_DBG_CTDREQ >> 0u) & 0b111111u;
}
inline void set_CH0_DBG_CTDREQ_CH0_DBG_CTDREQ(uint8_t value) volatile
{
uint32_t curr = CH0_DBG_CTDREQ;
curr &= ~(0b111111u << 0u);
curr |= (value & 0b111111u) << 0u;
CH0_DBG_CTDREQ = curr;
}
inline uint8_t get_CH1_DBG_CTDREQ_CH1_DBG_CTDREQ() volatile
{
return (CH1_DBG_CTDREQ >> 0u) & 0b111111u;
}
inline void set_CH1_DBG_CTDREQ_CH1_DBG_CTDREQ(uint8_t value) volatile
{
uint32_t curr = CH1_DBG_CTDREQ;
curr &= ~(0b111111u << 0u);
curr |= (value & 0b111111u) << 0u;
CH1_DBG_CTDREQ = curr;
}
inline uint8_t get_CH2_DBG_CTDREQ_CH2_DBG_CTDREQ() volatile
{
return (CH2_DBG_CTDREQ >> 0u) & 0b111111u;
}
inline void set_CH2_DBG_CTDREQ_CH2_DBG_CTDREQ(uint8_t value) volatile
{
uint32_t curr = CH2_DBG_CTDREQ;
curr &= ~(0b111111u << 0u);
curr |= (value & 0b111111u) << 0u;
CH2_DBG_CTDREQ = curr;
}
inline uint8_t get_CH3_DBG_CTDREQ_CH3_DBG_CTDREQ() volatile
{
return (CH3_DBG_CTDREQ >> 0u) & 0b111111u;
}
inline void set_CH3_DBG_CTDREQ_CH3_DBG_CTDREQ(uint8_t value) volatile
{
uint32_t curr = CH3_DBG_CTDREQ;
curr &= ~(0b111111u << 0u);
curr |= (value & 0b111111u) << 0u;
CH3_DBG_CTDREQ = curr;
}
inline uint8_t get_CH4_DBG_CTDREQ_CH4_DBG_CTDREQ() volatile
{
return (CH4_DBG_CTDREQ >> 0u) & 0b111111u;
}
inline void set_CH4_DBG_CTDREQ_CH4_DBG_CTDREQ(uint8_t value) volatile
{
uint32_t curr = CH4_DBG_CTDREQ;
curr &= ~(0b111111u << 0u);
curr |= (value & 0b111111u) << 0u;
CH4_DBG_CTDREQ = curr;
}
inline uint8_t get_CH5_DBG_CTDREQ_CH5_DBG_CTDREQ() volatile
{
return (CH5_DBG_CTDREQ >> 0u) & 0b111111u;
}
inline void set_CH5_DBG_CTDREQ_CH5_DBG_CTDREQ(uint8_t value) volatile
{
uint32_t curr = CH5_DBG_CTDREQ;
curr &= ~(0b111111u << 0u);
curr |= (value & 0b111111u) << 0u;
CH5_DBG_CTDREQ = curr;
}
inline uint8_t get_CH6_DBG_CTDREQ_CH6_DBG_CTDREQ() volatile
{
return (CH6_DBG_CTDREQ >> 0u) & 0b111111u;
}
inline void set_CH6_DBG_CTDREQ_CH6_DBG_CTDREQ(uint8_t value) volatile
{
uint32_t curr = CH6_DBG_CTDREQ;
curr &= ~(0b111111u << 0u);
curr |= (value & 0b111111u) << 0u;
CH6_DBG_CTDREQ = curr;
}
inline uint8_t get_CH7_DBG_CTDREQ_CH7_DBG_CTDREQ() volatile
{
return (CH7_DBG_CTDREQ >> 0u) & 0b111111u;
}
inline void set_CH7_DBG_CTDREQ_CH7_DBG_CTDREQ(uint8_t value) volatile
{
uint32_t curr = CH7_DBG_CTDREQ;
curr &= ~(0b111111u << 0u);
curr |= (value & 0b111111u) << 0u;
CH7_DBG_CTDREQ = curr;
}
inline uint8_t get_CH8_DBG_CTDREQ_CH8_DBG_CTDREQ() volatile
{
return (CH8_DBG_CTDREQ >> 0u) & 0b111111u;
}
inline void set_CH8_DBG_CTDREQ_CH8_DBG_CTDREQ(uint8_t value) volatile
{
uint32_t curr = CH8_DBG_CTDREQ;
curr &= ~(0b111111u << 0u);
curr |= (value & 0b111111u) << 0u;
CH8_DBG_CTDREQ = curr;
}
inline uint8_t get_CH9_DBG_CTDREQ_CH9_DBG_CTDREQ() volatile
{
return (CH9_DBG_CTDREQ >> 0u) & 0b111111u;
}
inline void set_CH9_DBG_CTDREQ_CH9_DBG_CTDREQ(uint8_t value) volatile
{
uint32_t curr = CH9_DBG_CTDREQ;
curr &= ~(0b111111u << 0u);
curr |= (value & 0b111111u) << 0u;
CH9_DBG_CTDREQ = curr;
}
inline uint8_t get_CH10_DBG_CTDREQ_CH10_DBG_CTDREQ() volatile
{
return (CH10_DBG_CTDREQ >> 0u) & 0b111111u;
}
inline void set_CH10_DBG_CTDREQ_CH10_DBG_CTDREQ(uint8_t value) volatile
{
uint32_t curr = CH10_DBG_CTDREQ;
curr &= ~(0b111111u << 0u);
curr |= (value & 0b111111u) << 0u;
CH10_DBG_CTDREQ = curr;
}
inline uint8_t get_CH11_DBG_CTDREQ_CH11_DBG_CTDREQ() volatile
{
return (CH11_DBG_CTDREQ >> 0u) & 0b111111u;
}
inline void set_CH11_DBG_CTDREQ_CH11_DBG_CTDREQ(uint8_t value) volatile
{
uint32_t curr = CH11_DBG_CTDREQ;
curr &= ~(0b111111u << 0u);
curr |= (value & 0b111111u) << 0u;
CH11_DBG_CTDREQ = curr;
}
};
static_assert(sizeof(dma) == dma::size);
static volatile dma *const DMA = reinterpret_cast<dma *>(0x50000000);
}; // namespace RP2040