Program Listing for File clocks.h#
↰ Return to documentation for file (src/generated/structs/clocks.h)
#pragma once
#include "../enums/CLOCKS_CLK_ADC_CTRL_AUXSRC.h"
#include "../enums/CLOCKS_CLK_GPOUT0_CTRL_AUXSRC.h"
#include "../enums/CLOCKS_CLK_GPOUT1_CTRL_AUXSRC.h"
#include "../enums/CLOCKS_CLK_GPOUT2_CTRL_AUXSRC.h"
#include "../enums/CLOCKS_CLK_GPOUT3_CTRL_AUXSRC.h"
#include "../enums/CLOCKS_CLK_PERI_CTRL_AUXSRC.h"
#include "../enums/CLOCKS_CLK_REF_CTRL_AUXSRC.h"
#include "../enums/CLOCKS_CLK_REF_CTRL_SRC.h"
#include "../enums/CLOCKS_CLK_RTC_CTRL_AUXSRC.h"
#include "../enums/CLOCKS_CLK_SYS_CTRL_AUXSRC.h"
#include "../enums/CLOCKS_CLK_USB_CTRL_AUXSRC.h"
#include "../enums/CLOCKS_FC0_SRC_FC0_SRC.h"
#include "../ifgen/common.h"
namespace RP2040
{
struct [[gnu::packed]] clocks
{
/* Constant attributes. */
static constexpr std::size_t size = 200;
/* Fields. */
uint32_t CLK_GPOUT0_CTRL;
uint32_t CLK_GPOUT0_DIV;
uint32_t CLK_GPOUT0_SELECTED;
uint32_t CLK_GPOUT1_CTRL;
uint32_t CLK_GPOUT1_DIV;
uint32_t CLK_GPOUT1_SELECTED;
uint32_t CLK_GPOUT2_CTRL;
uint32_t CLK_GPOUT2_DIV;
uint32_t CLK_GPOUT2_SELECTED;
uint32_t CLK_GPOUT3_CTRL;
uint32_t CLK_GPOUT3_DIV;
uint32_t CLK_GPOUT3_SELECTED;
uint32_t CLK_REF_CTRL;
uint32_t CLK_REF_DIV;
uint32_t CLK_REF_SELECTED;
uint32_t CLK_SYS_CTRL;
uint32_t CLK_SYS_DIV;
uint32_t CLK_SYS_SELECTED;
uint32_t CLK_PERI_CTRL;
const uint32_t reserved_padding0 = {};
uint32_t CLK_PERI_SELECTED;
uint32_t CLK_USB_CTRL;
uint32_t CLK_USB_DIV;
uint32_t CLK_USB_SELECTED;
uint32_t CLK_ADC_CTRL;
uint32_t CLK_ADC_DIV;
uint32_t CLK_ADC_SELECTED;
uint32_t CLK_RTC_CTRL;
uint32_t CLK_RTC_DIV;
uint32_t CLK_RTC_SELECTED;
uint32_t CLK_SYS_RESUS_CTRL;
const uint32_t CLK_SYS_RESUS_STATUS = {};
uint32_t FC0_REF_KHZ;
uint32_t FC0_MIN_KHZ;
uint32_t FC0_MAX_KHZ;
uint32_t FC0_DELAY;
uint32_t FC0_INTERVAL;
uint32_t FC0_SRC;
const uint32_t FC0_STATUS =
{};
const uint32_t FC0_RESULT =
{};
uint32_t WAKE_EN0;
uint32_t WAKE_EN1;
uint32_t SLEEP_EN0;
uint32_t SLEEP_EN1;
const uint32_t ENABLED0 =
{};
const uint32_t ENABLED1 =
{};
const uint32_t INTR = {};
uint32_t INTE;
uint32_t INTF;
const uint32_t INTS =
{};
/* Methods. */
inline CLOCKS_CLK_GPOUT0_CTRL_AUXSRC get_CLK_GPOUT0_CTRL_AUXSRC() volatile
{
return CLOCKS_CLK_GPOUT0_CTRL_AUXSRC((CLK_GPOUT0_CTRL >> 5u) &
0b1111u);
}
inline void set_CLK_GPOUT0_CTRL_AUXSRC(
CLOCKS_CLK_GPOUT0_CTRL_AUXSRC value) volatile
{
uint32_t curr = CLK_GPOUT0_CTRL;
curr &= ~(0b1111u << 5u);
curr |= (std::to_underlying(value) & 0b1111u) << 5u;
CLK_GPOUT0_CTRL = curr;
}
inline bool get_CLK_GPOUT0_CTRL_KILL() volatile
{
return CLK_GPOUT0_CTRL & (1u << 10u);
}
inline void set_CLK_GPOUT0_CTRL_KILL() volatile
{
CLK_GPOUT0_CTRL |= 1u << 10u;
}
inline void clear_CLK_GPOUT0_CTRL_KILL() volatile
{
CLK_GPOUT0_CTRL &= ~(1u << 10u);
}
inline void toggle_CLK_GPOUT0_CTRL_KILL() volatile
{
CLK_GPOUT0_CTRL ^= 1u << 10u;
}
inline bool get_CLK_GPOUT0_CTRL_ENABLE() volatile
{
return CLK_GPOUT0_CTRL & (1u << 11u);
}
inline void set_CLK_GPOUT0_CTRL_ENABLE() volatile
{
CLK_GPOUT0_CTRL |= 1u << 11u;
}
inline void clear_CLK_GPOUT0_CTRL_ENABLE() volatile
{
CLK_GPOUT0_CTRL &= ~(1u << 11u);
}
inline void toggle_CLK_GPOUT0_CTRL_ENABLE() volatile
{
CLK_GPOUT0_CTRL ^= 1u << 11u;
}
inline bool get_CLK_GPOUT0_CTRL_DC50() volatile
{
return CLK_GPOUT0_CTRL & (1u << 12u);
}
inline void set_CLK_GPOUT0_CTRL_DC50() volatile
{
CLK_GPOUT0_CTRL |= 1u << 12u;
}
inline void clear_CLK_GPOUT0_CTRL_DC50() volatile
{
CLK_GPOUT0_CTRL &= ~(1u << 12u);
}
inline void toggle_CLK_GPOUT0_CTRL_DC50() volatile
{
CLK_GPOUT0_CTRL ^= 1u << 12u;
}
inline uint8_t get_CLK_GPOUT0_CTRL_PHASE() volatile
{
return (CLK_GPOUT0_CTRL >> 16u) & 0b11u;
}
inline void set_CLK_GPOUT0_CTRL_PHASE(uint8_t value) volatile
{
uint32_t curr = CLK_GPOUT0_CTRL;
curr &= ~(0b11u << 16u);
curr |= (value & 0b11u) << 16u;
CLK_GPOUT0_CTRL = curr;
}
inline bool get_CLK_GPOUT0_CTRL_NUDGE() volatile
{
return CLK_GPOUT0_CTRL & (1u << 20u);
}
inline void set_CLK_GPOUT0_CTRL_NUDGE() volatile
{
CLK_GPOUT0_CTRL |= 1u << 20u;
}
inline void clear_CLK_GPOUT0_CTRL_NUDGE() volatile
{
CLK_GPOUT0_CTRL &= ~(1u << 20u);
}
inline void toggle_CLK_GPOUT0_CTRL_NUDGE() volatile
{
CLK_GPOUT0_CTRL ^= 1u << 20u;
}
inline void get_CLK_GPOUT0_CTRL(CLOCKS_CLK_GPOUT0_CTRL_AUXSRC &AUXSRC,
bool &KILL, bool &ENABLE, bool &DC50,
uint8_t &PHASE, bool &NUDGE) volatile
{
uint32_t curr = CLK_GPOUT0_CTRL;
AUXSRC = CLOCKS_CLK_GPOUT0_CTRL_AUXSRC((curr >> 5u) & 0b1111u);
KILL = curr & (1u << 10u);
ENABLE = curr & (1u << 11u);
DC50 = curr & (1u << 12u);
PHASE = (curr >> 16u) & 0b11u;
NUDGE = curr & (1u << 20u);
}
inline void set_CLK_GPOUT0_CTRL(CLOCKS_CLK_GPOUT0_CTRL_AUXSRC AUXSRC,
bool KILL, bool ENABLE, bool DC50,
uint8_t PHASE, bool NUDGE) volatile
{
uint32_t curr = CLK_GPOUT0_CTRL;
curr &= ~(0b1111u << 5u);
curr |= (std::to_underlying(AUXSRC) & 0b1111u) << 5u;
curr &= ~(0b1u << 10u);
curr |= (KILL & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (ENABLE & 0b1u) << 11u;
curr &= ~(0b1u << 12u);
curr |= (DC50 & 0b1u) << 12u;
curr &= ~(0b11u << 16u);
curr |= (PHASE & 0b11u) << 16u;
curr &= ~(0b1u << 20u);
curr |= (NUDGE & 0b1u) << 20u;
CLK_GPOUT0_CTRL = curr;
}
inline uint8_t get_CLK_GPOUT0_DIV_FRAC() volatile
{
return (CLK_GPOUT0_DIV >> 0u) & 0b11111111u;
}
inline void set_CLK_GPOUT0_DIV_FRAC(uint8_t value) volatile
{
uint32_t curr = CLK_GPOUT0_DIV;
curr &= ~(0b11111111u << 0u);
curr |= (value & 0b11111111u) << 0u;
CLK_GPOUT0_DIV = curr;
}
inline uint32_t get_CLK_GPOUT0_DIV_INT() volatile
{
return (CLK_GPOUT0_DIV >> 8u) & 0b111111111111111111111111u;
}
inline void set_CLK_GPOUT0_DIV_INT(uint32_t value) volatile
{
uint32_t curr = CLK_GPOUT0_DIV;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (value & 0b111111111111111111111111u) << 8u;
CLK_GPOUT0_DIV = curr;
}
inline void get_CLK_GPOUT0_DIV(uint8_t &FRAC, uint32_t &INT) volatile
{
uint32_t curr = CLK_GPOUT0_DIV;
FRAC = (curr >> 0u) & 0b11111111u;
INT = (curr >> 8u) & 0b111111111111111111111111u;
}
inline void set_CLK_GPOUT0_DIV(uint8_t FRAC, uint32_t INT) volatile
{
uint32_t curr = CLK_GPOUT0_DIV;
curr &= ~(0b11111111u << 0u);
curr |= (FRAC & 0b11111111u) << 0u;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (INT & 0b111111111111111111111111u) << 8u;
CLK_GPOUT0_DIV = curr;
}
inline CLOCKS_CLK_GPOUT1_CTRL_AUXSRC get_CLK_GPOUT1_CTRL_AUXSRC() volatile
{
return CLOCKS_CLK_GPOUT1_CTRL_AUXSRC((CLK_GPOUT1_CTRL >> 5u) &
0b1111u);
}
inline void set_CLK_GPOUT1_CTRL_AUXSRC(
CLOCKS_CLK_GPOUT1_CTRL_AUXSRC value) volatile
{
uint32_t curr = CLK_GPOUT1_CTRL;
curr &= ~(0b1111u << 5u);
curr |= (std::to_underlying(value) & 0b1111u) << 5u;
CLK_GPOUT1_CTRL = curr;
}
inline bool get_CLK_GPOUT1_CTRL_KILL() volatile
{
return CLK_GPOUT1_CTRL & (1u << 10u);
}
inline void set_CLK_GPOUT1_CTRL_KILL() volatile
{
CLK_GPOUT1_CTRL |= 1u << 10u;
}
inline void clear_CLK_GPOUT1_CTRL_KILL() volatile
{
CLK_GPOUT1_CTRL &= ~(1u << 10u);
}
inline void toggle_CLK_GPOUT1_CTRL_KILL() volatile
{
CLK_GPOUT1_CTRL ^= 1u << 10u;
}
inline bool get_CLK_GPOUT1_CTRL_ENABLE() volatile
{
return CLK_GPOUT1_CTRL & (1u << 11u);
}
inline void set_CLK_GPOUT1_CTRL_ENABLE() volatile
{
CLK_GPOUT1_CTRL |= 1u << 11u;
}
inline void clear_CLK_GPOUT1_CTRL_ENABLE() volatile
{
CLK_GPOUT1_CTRL &= ~(1u << 11u);
}
inline void toggle_CLK_GPOUT1_CTRL_ENABLE() volatile
{
CLK_GPOUT1_CTRL ^= 1u << 11u;
}
inline bool get_CLK_GPOUT1_CTRL_DC50() volatile
{
return CLK_GPOUT1_CTRL & (1u << 12u);
}
inline void set_CLK_GPOUT1_CTRL_DC50() volatile
{
CLK_GPOUT1_CTRL |= 1u << 12u;
}
inline void clear_CLK_GPOUT1_CTRL_DC50() volatile
{
CLK_GPOUT1_CTRL &= ~(1u << 12u);
}
inline void toggle_CLK_GPOUT1_CTRL_DC50() volatile
{
CLK_GPOUT1_CTRL ^= 1u << 12u;
}
inline uint8_t get_CLK_GPOUT1_CTRL_PHASE() volatile
{
return (CLK_GPOUT1_CTRL >> 16u) & 0b11u;
}
inline void set_CLK_GPOUT1_CTRL_PHASE(uint8_t value) volatile
{
uint32_t curr = CLK_GPOUT1_CTRL;
curr &= ~(0b11u << 16u);
curr |= (value & 0b11u) << 16u;
CLK_GPOUT1_CTRL = curr;
}
inline bool get_CLK_GPOUT1_CTRL_NUDGE() volatile
{
return CLK_GPOUT1_CTRL & (1u << 20u);
}
inline void set_CLK_GPOUT1_CTRL_NUDGE() volatile
{
CLK_GPOUT1_CTRL |= 1u << 20u;
}
inline void clear_CLK_GPOUT1_CTRL_NUDGE() volatile
{
CLK_GPOUT1_CTRL &= ~(1u << 20u);
}
inline void toggle_CLK_GPOUT1_CTRL_NUDGE() volatile
{
CLK_GPOUT1_CTRL ^= 1u << 20u;
}
inline void get_CLK_GPOUT1_CTRL(CLOCKS_CLK_GPOUT1_CTRL_AUXSRC &AUXSRC,
bool &KILL, bool &ENABLE, bool &DC50,
uint8_t &PHASE, bool &NUDGE) volatile
{
uint32_t curr = CLK_GPOUT1_CTRL;
AUXSRC = CLOCKS_CLK_GPOUT1_CTRL_AUXSRC((curr >> 5u) & 0b1111u);
KILL = curr & (1u << 10u);
ENABLE = curr & (1u << 11u);
DC50 = curr & (1u << 12u);
PHASE = (curr >> 16u) & 0b11u;
NUDGE = curr & (1u << 20u);
}
inline void set_CLK_GPOUT1_CTRL(CLOCKS_CLK_GPOUT1_CTRL_AUXSRC AUXSRC,
bool KILL, bool ENABLE, bool DC50,
uint8_t PHASE, bool NUDGE) volatile
{
uint32_t curr = CLK_GPOUT1_CTRL;
curr &= ~(0b1111u << 5u);
curr |= (std::to_underlying(AUXSRC) & 0b1111u) << 5u;
curr &= ~(0b1u << 10u);
curr |= (KILL & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (ENABLE & 0b1u) << 11u;
curr &= ~(0b1u << 12u);
curr |= (DC50 & 0b1u) << 12u;
curr &= ~(0b11u << 16u);
curr |= (PHASE & 0b11u) << 16u;
curr &= ~(0b1u << 20u);
curr |= (NUDGE & 0b1u) << 20u;
CLK_GPOUT1_CTRL = curr;
}
inline uint8_t get_CLK_GPOUT1_DIV_FRAC() volatile
{
return (CLK_GPOUT1_DIV >> 0u) & 0b11111111u;
}
inline void set_CLK_GPOUT1_DIV_FRAC(uint8_t value) volatile
{
uint32_t curr = CLK_GPOUT1_DIV;
curr &= ~(0b11111111u << 0u);
curr |= (value & 0b11111111u) << 0u;
CLK_GPOUT1_DIV = curr;
}
inline uint32_t get_CLK_GPOUT1_DIV_INT() volatile
{
return (CLK_GPOUT1_DIV >> 8u) & 0b111111111111111111111111u;
}
inline void set_CLK_GPOUT1_DIV_INT(uint32_t value) volatile
{
uint32_t curr = CLK_GPOUT1_DIV;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (value & 0b111111111111111111111111u) << 8u;
CLK_GPOUT1_DIV = curr;
}
inline void get_CLK_GPOUT1_DIV(uint8_t &FRAC, uint32_t &INT) volatile
{
uint32_t curr = CLK_GPOUT1_DIV;
FRAC = (curr >> 0u) & 0b11111111u;
INT = (curr >> 8u) & 0b111111111111111111111111u;
}
inline void set_CLK_GPOUT1_DIV(uint8_t FRAC, uint32_t INT) volatile
{
uint32_t curr = CLK_GPOUT1_DIV;
curr &= ~(0b11111111u << 0u);
curr |= (FRAC & 0b11111111u) << 0u;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (INT & 0b111111111111111111111111u) << 8u;
CLK_GPOUT1_DIV = curr;
}
inline CLOCKS_CLK_GPOUT2_CTRL_AUXSRC get_CLK_GPOUT2_CTRL_AUXSRC() volatile
{
return CLOCKS_CLK_GPOUT2_CTRL_AUXSRC((CLK_GPOUT2_CTRL >> 5u) &
0b1111u);
}
inline void set_CLK_GPOUT2_CTRL_AUXSRC(
CLOCKS_CLK_GPOUT2_CTRL_AUXSRC value) volatile
{
uint32_t curr = CLK_GPOUT2_CTRL;
curr &= ~(0b1111u << 5u);
curr |= (std::to_underlying(value) & 0b1111u) << 5u;
CLK_GPOUT2_CTRL = curr;
}
inline bool get_CLK_GPOUT2_CTRL_KILL() volatile
{
return CLK_GPOUT2_CTRL & (1u << 10u);
}
inline void set_CLK_GPOUT2_CTRL_KILL() volatile
{
CLK_GPOUT2_CTRL |= 1u << 10u;
}
inline void clear_CLK_GPOUT2_CTRL_KILL() volatile
{
CLK_GPOUT2_CTRL &= ~(1u << 10u);
}
inline void toggle_CLK_GPOUT2_CTRL_KILL() volatile
{
CLK_GPOUT2_CTRL ^= 1u << 10u;
}
inline bool get_CLK_GPOUT2_CTRL_ENABLE() volatile
{
return CLK_GPOUT2_CTRL & (1u << 11u);
}
inline void set_CLK_GPOUT2_CTRL_ENABLE() volatile
{
CLK_GPOUT2_CTRL |= 1u << 11u;
}
inline void clear_CLK_GPOUT2_CTRL_ENABLE() volatile
{
CLK_GPOUT2_CTRL &= ~(1u << 11u);
}
inline void toggle_CLK_GPOUT2_CTRL_ENABLE() volatile
{
CLK_GPOUT2_CTRL ^= 1u << 11u;
}
inline bool get_CLK_GPOUT2_CTRL_DC50() volatile
{
return CLK_GPOUT2_CTRL & (1u << 12u);
}
inline void set_CLK_GPOUT2_CTRL_DC50() volatile
{
CLK_GPOUT2_CTRL |= 1u << 12u;
}
inline void clear_CLK_GPOUT2_CTRL_DC50() volatile
{
CLK_GPOUT2_CTRL &= ~(1u << 12u);
}
inline void toggle_CLK_GPOUT2_CTRL_DC50() volatile
{
CLK_GPOUT2_CTRL ^= 1u << 12u;
}
inline uint8_t get_CLK_GPOUT2_CTRL_PHASE() volatile
{
return (CLK_GPOUT2_CTRL >> 16u) & 0b11u;
}
inline void set_CLK_GPOUT2_CTRL_PHASE(uint8_t value) volatile
{
uint32_t curr = CLK_GPOUT2_CTRL;
curr &= ~(0b11u << 16u);
curr |= (value & 0b11u) << 16u;
CLK_GPOUT2_CTRL = curr;
}
inline bool get_CLK_GPOUT2_CTRL_NUDGE() volatile
{
return CLK_GPOUT2_CTRL & (1u << 20u);
}
inline void set_CLK_GPOUT2_CTRL_NUDGE() volatile
{
CLK_GPOUT2_CTRL |= 1u << 20u;
}
inline void clear_CLK_GPOUT2_CTRL_NUDGE() volatile
{
CLK_GPOUT2_CTRL &= ~(1u << 20u);
}
inline void toggle_CLK_GPOUT2_CTRL_NUDGE() volatile
{
CLK_GPOUT2_CTRL ^= 1u << 20u;
}
inline void get_CLK_GPOUT2_CTRL(CLOCKS_CLK_GPOUT2_CTRL_AUXSRC &AUXSRC,
bool &KILL, bool &ENABLE, bool &DC50,
uint8_t &PHASE, bool &NUDGE) volatile
{
uint32_t curr = CLK_GPOUT2_CTRL;
AUXSRC = CLOCKS_CLK_GPOUT2_CTRL_AUXSRC((curr >> 5u) & 0b1111u);
KILL = curr & (1u << 10u);
ENABLE = curr & (1u << 11u);
DC50 = curr & (1u << 12u);
PHASE = (curr >> 16u) & 0b11u;
NUDGE = curr & (1u << 20u);
}
inline void set_CLK_GPOUT2_CTRL(CLOCKS_CLK_GPOUT2_CTRL_AUXSRC AUXSRC,
bool KILL, bool ENABLE, bool DC50,
uint8_t PHASE, bool NUDGE) volatile
{
uint32_t curr = CLK_GPOUT2_CTRL;
curr &= ~(0b1111u << 5u);
curr |= (std::to_underlying(AUXSRC) & 0b1111u) << 5u;
curr &= ~(0b1u << 10u);
curr |= (KILL & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (ENABLE & 0b1u) << 11u;
curr &= ~(0b1u << 12u);
curr |= (DC50 & 0b1u) << 12u;
curr &= ~(0b11u << 16u);
curr |= (PHASE & 0b11u) << 16u;
curr &= ~(0b1u << 20u);
curr |= (NUDGE & 0b1u) << 20u;
CLK_GPOUT2_CTRL = curr;
}
inline uint8_t get_CLK_GPOUT2_DIV_FRAC() volatile
{
return (CLK_GPOUT2_DIV >> 0u) & 0b11111111u;
}
inline void set_CLK_GPOUT2_DIV_FRAC(uint8_t value) volatile
{
uint32_t curr = CLK_GPOUT2_DIV;
curr &= ~(0b11111111u << 0u);
curr |= (value & 0b11111111u) << 0u;
CLK_GPOUT2_DIV = curr;
}
inline uint32_t get_CLK_GPOUT2_DIV_INT() volatile
{
return (CLK_GPOUT2_DIV >> 8u) & 0b111111111111111111111111u;
}
inline void set_CLK_GPOUT2_DIV_INT(uint32_t value) volatile
{
uint32_t curr = CLK_GPOUT2_DIV;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (value & 0b111111111111111111111111u) << 8u;
CLK_GPOUT2_DIV = curr;
}
inline void get_CLK_GPOUT2_DIV(uint8_t &FRAC, uint32_t &INT) volatile
{
uint32_t curr = CLK_GPOUT2_DIV;
FRAC = (curr >> 0u) & 0b11111111u;
INT = (curr >> 8u) & 0b111111111111111111111111u;
}
inline void set_CLK_GPOUT2_DIV(uint8_t FRAC, uint32_t INT) volatile
{
uint32_t curr = CLK_GPOUT2_DIV;
curr &= ~(0b11111111u << 0u);
curr |= (FRAC & 0b11111111u) << 0u;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (INT & 0b111111111111111111111111u) << 8u;
CLK_GPOUT2_DIV = curr;
}
inline CLOCKS_CLK_GPOUT3_CTRL_AUXSRC get_CLK_GPOUT3_CTRL_AUXSRC() volatile
{
return CLOCKS_CLK_GPOUT3_CTRL_AUXSRC((CLK_GPOUT3_CTRL >> 5u) &
0b1111u);
}
inline void set_CLK_GPOUT3_CTRL_AUXSRC(
CLOCKS_CLK_GPOUT3_CTRL_AUXSRC value) volatile
{
uint32_t curr = CLK_GPOUT3_CTRL;
curr &= ~(0b1111u << 5u);
curr |= (std::to_underlying(value) & 0b1111u) << 5u;
CLK_GPOUT3_CTRL = curr;
}
inline bool get_CLK_GPOUT3_CTRL_KILL() volatile
{
return CLK_GPOUT3_CTRL & (1u << 10u);
}
inline void set_CLK_GPOUT3_CTRL_KILL() volatile
{
CLK_GPOUT3_CTRL |= 1u << 10u;
}
inline void clear_CLK_GPOUT3_CTRL_KILL() volatile
{
CLK_GPOUT3_CTRL &= ~(1u << 10u);
}
inline void toggle_CLK_GPOUT3_CTRL_KILL() volatile
{
CLK_GPOUT3_CTRL ^= 1u << 10u;
}
inline bool get_CLK_GPOUT3_CTRL_ENABLE() volatile
{
return CLK_GPOUT3_CTRL & (1u << 11u);
}
inline void set_CLK_GPOUT3_CTRL_ENABLE() volatile
{
CLK_GPOUT3_CTRL |= 1u << 11u;
}
inline void clear_CLK_GPOUT3_CTRL_ENABLE() volatile
{
CLK_GPOUT3_CTRL &= ~(1u << 11u);
}
inline void toggle_CLK_GPOUT3_CTRL_ENABLE() volatile
{
CLK_GPOUT3_CTRL ^= 1u << 11u;
}
inline bool get_CLK_GPOUT3_CTRL_DC50() volatile
{
return CLK_GPOUT3_CTRL & (1u << 12u);
}
inline void set_CLK_GPOUT3_CTRL_DC50() volatile
{
CLK_GPOUT3_CTRL |= 1u << 12u;
}
inline void clear_CLK_GPOUT3_CTRL_DC50() volatile
{
CLK_GPOUT3_CTRL &= ~(1u << 12u);
}
inline void toggle_CLK_GPOUT3_CTRL_DC50() volatile
{
CLK_GPOUT3_CTRL ^= 1u << 12u;
}
inline uint8_t get_CLK_GPOUT3_CTRL_PHASE() volatile
{
return (CLK_GPOUT3_CTRL >> 16u) & 0b11u;
}
inline void set_CLK_GPOUT3_CTRL_PHASE(uint8_t value) volatile
{
uint32_t curr = CLK_GPOUT3_CTRL;
curr &= ~(0b11u << 16u);
curr |= (value & 0b11u) << 16u;
CLK_GPOUT3_CTRL = curr;
}
inline bool get_CLK_GPOUT3_CTRL_NUDGE() volatile
{
return CLK_GPOUT3_CTRL & (1u << 20u);
}
inline void set_CLK_GPOUT3_CTRL_NUDGE() volatile
{
CLK_GPOUT3_CTRL |= 1u << 20u;
}
inline void clear_CLK_GPOUT3_CTRL_NUDGE() volatile
{
CLK_GPOUT3_CTRL &= ~(1u << 20u);
}
inline void toggle_CLK_GPOUT3_CTRL_NUDGE() volatile
{
CLK_GPOUT3_CTRL ^= 1u << 20u;
}
inline void get_CLK_GPOUT3_CTRL(CLOCKS_CLK_GPOUT3_CTRL_AUXSRC &AUXSRC,
bool &KILL, bool &ENABLE, bool &DC50,
uint8_t &PHASE, bool &NUDGE) volatile
{
uint32_t curr = CLK_GPOUT3_CTRL;
AUXSRC = CLOCKS_CLK_GPOUT3_CTRL_AUXSRC((curr >> 5u) & 0b1111u);
KILL = curr & (1u << 10u);
ENABLE = curr & (1u << 11u);
DC50 = curr & (1u << 12u);
PHASE = (curr >> 16u) & 0b11u;
NUDGE = curr & (1u << 20u);
}
inline void set_CLK_GPOUT3_CTRL(CLOCKS_CLK_GPOUT3_CTRL_AUXSRC AUXSRC,
bool KILL, bool ENABLE, bool DC50,
uint8_t PHASE, bool NUDGE) volatile
{
uint32_t curr = CLK_GPOUT3_CTRL;
curr &= ~(0b1111u << 5u);
curr |= (std::to_underlying(AUXSRC) & 0b1111u) << 5u;
curr &= ~(0b1u << 10u);
curr |= (KILL & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (ENABLE & 0b1u) << 11u;
curr &= ~(0b1u << 12u);
curr |= (DC50 & 0b1u) << 12u;
curr &= ~(0b11u << 16u);
curr |= (PHASE & 0b11u) << 16u;
curr &= ~(0b1u << 20u);
curr |= (NUDGE & 0b1u) << 20u;
CLK_GPOUT3_CTRL = curr;
}
inline uint8_t get_CLK_GPOUT3_DIV_FRAC() volatile
{
return (CLK_GPOUT3_DIV >> 0u) & 0b11111111u;
}
inline void set_CLK_GPOUT3_DIV_FRAC(uint8_t value) volatile
{
uint32_t curr = CLK_GPOUT3_DIV;
curr &= ~(0b11111111u << 0u);
curr |= (value & 0b11111111u) << 0u;
CLK_GPOUT3_DIV = curr;
}
inline uint32_t get_CLK_GPOUT3_DIV_INT() volatile
{
return (CLK_GPOUT3_DIV >> 8u) & 0b111111111111111111111111u;
}
inline void set_CLK_GPOUT3_DIV_INT(uint32_t value) volatile
{
uint32_t curr = CLK_GPOUT3_DIV;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (value & 0b111111111111111111111111u) << 8u;
CLK_GPOUT3_DIV = curr;
}
inline void get_CLK_GPOUT3_DIV(uint8_t &FRAC, uint32_t &INT) volatile
{
uint32_t curr = CLK_GPOUT3_DIV;
FRAC = (curr >> 0u) & 0b11111111u;
INT = (curr >> 8u) & 0b111111111111111111111111u;
}
inline void set_CLK_GPOUT3_DIV(uint8_t FRAC, uint32_t INT) volatile
{
uint32_t curr = CLK_GPOUT3_DIV;
curr &= ~(0b11111111u << 0u);
curr |= (FRAC & 0b11111111u) << 0u;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (INT & 0b111111111111111111111111u) << 8u;
CLK_GPOUT3_DIV = curr;
}
inline CLOCKS_CLK_REF_CTRL_SRC get_CLK_REF_CTRL_SRC() volatile
{
return CLOCKS_CLK_REF_CTRL_SRC((CLK_REF_CTRL >> 0u) & 0b11u);
}
inline void set_CLK_REF_CTRL_SRC(CLOCKS_CLK_REF_CTRL_SRC value) volatile
{
uint32_t curr = CLK_REF_CTRL;
curr &= ~(0b11u << 0u);
curr |= (std::to_underlying(value) & 0b11u) << 0u;
CLK_REF_CTRL = curr;
}
inline CLOCKS_CLK_REF_CTRL_AUXSRC get_CLK_REF_CTRL_AUXSRC() volatile
{
return CLOCKS_CLK_REF_CTRL_AUXSRC((CLK_REF_CTRL >> 5u) & 0b11u);
}
inline void set_CLK_REF_CTRL_AUXSRC(
CLOCKS_CLK_REF_CTRL_AUXSRC value) volatile
{
uint32_t curr = CLK_REF_CTRL;
curr &= ~(0b11u << 5u);
curr |= (std::to_underlying(value) & 0b11u) << 5u;
CLK_REF_CTRL = curr;
}
inline void get_CLK_REF_CTRL(CLOCKS_CLK_REF_CTRL_SRC &SRC,
CLOCKS_CLK_REF_CTRL_AUXSRC &AUXSRC) volatile
{
uint32_t curr = CLK_REF_CTRL;
SRC = CLOCKS_CLK_REF_CTRL_SRC((curr >> 0u) & 0b11u);
AUXSRC = CLOCKS_CLK_REF_CTRL_AUXSRC((curr >> 5u) & 0b11u);
}
inline void set_CLK_REF_CTRL(CLOCKS_CLK_REF_CTRL_SRC SRC,
CLOCKS_CLK_REF_CTRL_AUXSRC AUXSRC) volatile
{
uint32_t curr = CLK_REF_CTRL;
curr &= ~(0b11u << 0u);
curr |= (std::to_underlying(SRC) & 0b11u) << 0u;
curr &= ~(0b11u << 5u);
curr |= (std::to_underlying(AUXSRC) & 0b11u) << 5u;
CLK_REF_CTRL = curr;
}
inline uint8_t get_CLK_REF_DIV_INT() volatile
{
return (CLK_REF_DIV >> 8u) & 0b11u;
}
inline void set_CLK_REF_DIV_INT(uint8_t value) volatile
{
uint32_t curr = CLK_REF_DIV;
curr &= ~(0b11u << 8u);
curr |= (value & 0b11u) << 8u;
CLK_REF_DIV = curr;
}
inline bool get_CLK_SYS_CTRL_SRC() volatile
{
return CLK_SYS_CTRL & (1u << 0u);
}
inline void set_CLK_SYS_CTRL_SRC() volatile
{
CLK_SYS_CTRL |= 1u << 0u;
}
inline void clear_CLK_SYS_CTRL_SRC() volatile
{
CLK_SYS_CTRL &= ~(1u << 0u);
}
inline void toggle_CLK_SYS_CTRL_SRC() volatile
{
CLK_SYS_CTRL ^= 1u << 0u;
}
inline CLOCKS_CLK_SYS_CTRL_AUXSRC get_CLK_SYS_CTRL_AUXSRC() volatile
{
return CLOCKS_CLK_SYS_CTRL_AUXSRC((CLK_SYS_CTRL >> 5u) & 0b111u);
}
inline void set_CLK_SYS_CTRL_AUXSRC(
CLOCKS_CLK_SYS_CTRL_AUXSRC value) volatile
{
uint32_t curr = CLK_SYS_CTRL;
curr &= ~(0b111u << 5u);
curr |= (std::to_underlying(value) & 0b111u) << 5u;
CLK_SYS_CTRL = curr;
}
inline void get_CLK_SYS_CTRL(bool &SRC,
CLOCKS_CLK_SYS_CTRL_AUXSRC &AUXSRC) volatile
{
uint32_t curr = CLK_SYS_CTRL;
SRC = curr & (1u << 0u);
AUXSRC = CLOCKS_CLK_SYS_CTRL_AUXSRC((curr >> 5u) & 0b111u);
}
inline void set_CLK_SYS_CTRL(bool SRC,
CLOCKS_CLK_SYS_CTRL_AUXSRC AUXSRC) volatile
{
uint32_t curr = CLK_SYS_CTRL;
curr &= ~(0b1u << 0u);
curr |= (SRC & 0b1u) << 0u;
curr &= ~(0b111u << 5u);
curr |= (std::to_underlying(AUXSRC) & 0b111u) << 5u;
CLK_SYS_CTRL = curr;
}
inline uint8_t get_CLK_SYS_DIV_FRAC() volatile
{
return (CLK_SYS_DIV >> 0u) & 0b11111111u;
}
inline void set_CLK_SYS_DIV_FRAC(uint8_t value) volatile
{
uint32_t curr = CLK_SYS_DIV;
curr &= ~(0b11111111u << 0u);
curr |= (value & 0b11111111u) << 0u;
CLK_SYS_DIV = curr;
}
inline uint32_t get_CLK_SYS_DIV_INT() volatile
{
return (CLK_SYS_DIV >> 8u) & 0b111111111111111111111111u;
}
inline void set_CLK_SYS_DIV_INT(uint32_t value) volatile
{
uint32_t curr = CLK_SYS_DIV;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (value & 0b111111111111111111111111u) << 8u;
CLK_SYS_DIV = curr;
}
inline void get_CLK_SYS_DIV(uint8_t &FRAC, uint32_t &INT) volatile
{
uint32_t curr = CLK_SYS_DIV;
FRAC = (curr >> 0u) & 0b11111111u;
INT = (curr >> 8u) & 0b111111111111111111111111u;
}
inline void set_CLK_SYS_DIV(uint8_t FRAC, uint32_t INT) volatile
{
uint32_t curr = CLK_SYS_DIV;
curr &= ~(0b11111111u << 0u);
curr |= (FRAC & 0b11111111u) << 0u;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (INT & 0b111111111111111111111111u) << 8u;
CLK_SYS_DIV = curr;
}
inline CLOCKS_CLK_PERI_CTRL_AUXSRC get_CLK_PERI_CTRL_AUXSRC() volatile
{
return CLOCKS_CLK_PERI_CTRL_AUXSRC((CLK_PERI_CTRL >> 5u) & 0b111u);
}
inline void set_CLK_PERI_CTRL_AUXSRC(
CLOCKS_CLK_PERI_CTRL_AUXSRC value) volatile
{
uint32_t curr = CLK_PERI_CTRL;
curr &= ~(0b111u << 5u);
curr |= (std::to_underlying(value) & 0b111u) << 5u;
CLK_PERI_CTRL = curr;
}
inline bool get_CLK_PERI_CTRL_KILL() volatile
{
return CLK_PERI_CTRL & (1u << 10u);
}
inline void set_CLK_PERI_CTRL_KILL() volatile
{
CLK_PERI_CTRL |= 1u << 10u;
}
inline void clear_CLK_PERI_CTRL_KILL() volatile
{
CLK_PERI_CTRL &= ~(1u << 10u);
}
inline void toggle_CLK_PERI_CTRL_KILL() volatile
{
CLK_PERI_CTRL ^= 1u << 10u;
}
inline bool get_CLK_PERI_CTRL_ENABLE() volatile
{
return CLK_PERI_CTRL & (1u << 11u);
}
inline void set_CLK_PERI_CTRL_ENABLE() volatile
{
CLK_PERI_CTRL |= 1u << 11u;
}
inline void clear_CLK_PERI_CTRL_ENABLE() volatile
{
CLK_PERI_CTRL &= ~(1u << 11u);
}
inline void toggle_CLK_PERI_CTRL_ENABLE() volatile
{
CLK_PERI_CTRL ^= 1u << 11u;
}
inline void get_CLK_PERI_CTRL(CLOCKS_CLK_PERI_CTRL_AUXSRC &AUXSRC,
bool &KILL, bool &ENABLE) volatile
{
uint32_t curr = CLK_PERI_CTRL;
AUXSRC = CLOCKS_CLK_PERI_CTRL_AUXSRC((curr >> 5u) & 0b111u);
KILL = curr & (1u << 10u);
ENABLE = curr & (1u << 11u);
}
inline void set_CLK_PERI_CTRL(CLOCKS_CLK_PERI_CTRL_AUXSRC AUXSRC,
bool KILL, bool ENABLE) volatile
{
uint32_t curr = CLK_PERI_CTRL;
curr &= ~(0b111u << 5u);
curr |= (std::to_underlying(AUXSRC) & 0b111u) << 5u;
curr &= ~(0b1u << 10u);
curr |= (KILL & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (ENABLE & 0b1u) << 11u;
CLK_PERI_CTRL = curr;
}
inline CLOCKS_CLK_USB_CTRL_AUXSRC get_CLK_USB_CTRL_AUXSRC() volatile
{
return CLOCKS_CLK_USB_CTRL_AUXSRC((CLK_USB_CTRL >> 5u) & 0b111u);
}
inline void set_CLK_USB_CTRL_AUXSRC(
CLOCKS_CLK_USB_CTRL_AUXSRC value) volatile
{
uint32_t curr = CLK_USB_CTRL;
curr &= ~(0b111u << 5u);
curr |= (std::to_underlying(value) & 0b111u) << 5u;
CLK_USB_CTRL = curr;
}
inline bool get_CLK_USB_CTRL_KILL() volatile
{
return CLK_USB_CTRL & (1u << 10u);
}
inline void set_CLK_USB_CTRL_KILL() volatile
{
CLK_USB_CTRL |= 1u << 10u;
}
inline void clear_CLK_USB_CTRL_KILL() volatile
{
CLK_USB_CTRL &= ~(1u << 10u);
}
inline void toggle_CLK_USB_CTRL_KILL() volatile
{
CLK_USB_CTRL ^= 1u << 10u;
}
inline bool get_CLK_USB_CTRL_ENABLE() volatile
{
return CLK_USB_CTRL & (1u << 11u);
}
inline void set_CLK_USB_CTRL_ENABLE() volatile
{
CLK_USB_CTRL |= 1u << 11u;
}
inline void clear_CLK_USB_CTRL_ENABLE() volatile
{
CLK_USB_CTRL &= ~(1u << 11u);
}
inline void toggle_CLK_USB_CTRL_ENABLE() volatile
{
CLK_USB_CTRL ^= 1u << 11u;
}
inline uint8_t get_CLK_USB_CTRL_PHASE() volatile
{
return (CLK_USB_CTRL >> 16u) & 0b11u;
}
inline void set_CLK_USB_CTRL_PHASE(uint8_t value) volatile
{
uint32_t curr = CLK_USB_CTRL;
curr &= ~(0b11u << 16u);
curr |= (value & 0b11u) << 16u;
CLK_USB_CTRL = curr;
}
inline bool get_CLK_USB_CTRL_NUDGE() volatile
{
return CLK_USB_CTRL & (1u << 20u);
}
inline void set_CLK_USB_CTRL_NUDGE() volatile
{
CLK_USB_CTRL |= 1u << 20u;
}
inline void clear_CLK_USB_CTRL_NUDGE() volatile
{
CLK_USB_CTRL &= ~(1u << 20u);
}
inline void toggle_CLK_USB_CTRL_NUDGE() volatile
{
CLK_USB_CTRL ^= 1u << 20u;
}
inline void get_CLK_USB_CTRL(CLOCKS_CLK_USB_CTRL_AUXSRC &AUXSRC,
bool &KILL, bool &ENABLE, uint8_t &PHASE,
bool &NUDGE) volatile
{
uint32_t curr = CLK_USB_CTRL;
AUXSRC = CLOCKS_CLK_USB_CTRL_AUXSRC((curr >> 5u) & 0b111u);
KILL = curr & (1u << 10u);
ENABLE = curr & (1u << 11u);
PHASE = (curr >> 16u) & 0b11u;
NUDGE = curr & (1u << 20u);
}
inline void set_CLK_USB_CTRL(CLOCKS_CLK_USB_CTRL_AUXSRC AUXSRC, bool KILL,
bool ENABLE, uint8_t PHASE,
bool NUDGE) volatile
{
uint32_t curr = CLK_USB_CTRL;
curr &= ~(0b111u << 5u);
curr |= (std::to_underlying(AUXSRC) & 0b111u) << 5u;
curr &= ~(0b1u << 10u);
curr |= (KILL & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (ENABLE & 0b1u) << 11u;
curr &= ~(0b11u << 16u);
curr |= (PHASE & 0b11u) << 16u;
curr &= ~(0b1u << 20u);
curr |= (NUDGE & 0b1u) << 20u;
CLK_USB_CTRL = curr;
}
inline uint8_t get_CLK_USB_DIV_INT() volatile
{
return (CLK_USB_DIV >> 8u) & 0b11u;
}
inline void set_CLK_USB_DIV_INT(uint8_t value) volatile
{
uint32_t curr = CLK_USB_DIV;
curr &= ~(0b11u << 8u);
curr |= (value & 0b11u) << 8u;
CLK_USB_DIV = curr;
}
inline CLOCKS_CLK_ADC_CTRL_AUXSRC get_CLK_ADC_CTRL_AUXSRC() volatile
{
return CLOCKS_CLK_ADC_CTRL_AUXSRC((CLK_ADC_CTRL >> 5u) & 0b111u);
}
inline void set_CLK_ADC_CTRL_AUXSRC(
CLOCKS_CLK_ADC_CTRL_AUXSRC value) volatile
{
uint32_t curr = CLK_ADC_CTRL;
curr &= ~(0b111u << 5u);
curr |= (std::to_underlying(value) & 0b111u) << 5u;
CLK_ADC_CTRL = curr;
}
inline bool get_CLK_ADC_CTRL_KILL() volatile
{
return CLK_ADC_CTRL & (1u << 10u);
}
inline void set_CLK_ADC_CTRL_KILL() volatile
{
CLK_ADC_CTRL |= 1u << 10u;
}
inline void clear_CLK_ADC_CTRL_KILL() volatile
{
CLK_ADC_CTRL &= ~(1u << 10u);
}
inline void toggle_CLK_ADC_CTRL_KILL() volatile
{
CLK_ADC_CTRL ^= 1u << 10u;
}
inline bool get_CLK_ADC_CTRL_ENABLE() volatile
{
return CLK_ADC_CTRL & (1u << 11u);
}
inline void set_CLK_ADC_CTRL_ENABLE() volatile
{
CLK_ADC_CTRL |= 1u << 11u;
}
inline void clear_CLK_ADC_CTRL_ENABLE() volatile
{
CLK_ADC_CTRL &= ~(1u << 11u);
}
inline void toggle_CLK_ADC_CTRL_ENABLE() volatile
{
CLK_ADC_CTRL ^= 1u << 11u;
}
inline uint8_t get_CLK_ADC_CTRL_PHASE() volatile
{
return (CLK_ADC_CTRL >> 16u) & 0b11u;
}
inline void set_CLK_ADC_CTRL_PHASE(uint8_t value) volatile
{
uint32_t curr = CLK_ADC_CTRL;
curr &= ~(0b11u << 16u);
curr |= (value & 0b11u) << 16u;
CLK_ADC_CTRL = curr;
}
inline bool get_CLK_ADC_CTRL_NUDGE() volatile
{
return CLK_ADC_CTRL & (1u << 20u);
}
inline void set_CLK_ADC_CTRL_NUDGE() volatile
{
CLK_ADC_CTRL |= 1u << 20u;
}
inline void clear_CLK_ADC_CTRL_NUDGE() volatile
{
CLK_ADC_CTRL &= ~(1u << 20u);
}
inline void toggle_CLK_ADC_CTRL_NUDGE() volatile
{
CLK_ADC_CTRL ^= 1u << 20u;
}
inline void get_CLK_ADC_CTRL(CLOCKS_CLK_ADC_CTRL_AUXSRC &AUXSRC,
bool &KILL, bool &ENABLE, uint8_t &PHASE,
bool &NUDGE) volatile
{
uint32_t curr = CLK_ADC_CTRL;
AUXSRC = CLOCKS_CLK_ADC_CTRL_AUXSRC((curr >> 5u) & 0b111u);
KILL = curr & (1u << 10u);
ENABLE = curr & (1u << 11u);
PHASE = (curr >> 16u) & 0b11u;
NUDGE = curr & (1u << 20u);
}
inline void set_CLK_ADC_CTRL(CLOCKS_CLK_ADC_CTRL_AUXSRC AUXSRC, bool KILL,
bool ENABLE, uint8_t PHASE,
bool NUDGE) volatile
{
uint32_t curr = CLK_ADC_CTRL;
curr &= ~(0b111u << 5u);
curr |= (std::to_underlying(AUXSRC) & 0b111u) << 5u;
curr &= ~(0b1u << 10u);
curr |= (KILL & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (ENABLE & 0b1u) << 11u;
curr &= ~(0b11u << 16u);
curr |= (PHASE & 0b11u) << 16u;
curr &= ~(0b1u << 20u);
curr |= (NUDGE & 0b1u) << 20u;
CLK_ADC_CTRL = curr;
}
inline uint8_t get_CLK_ADC_DIV_INT() volatile
{
return (CLK_ADC_DIV >> 8u) & 0b11u;
}
inline void set_CLK_ADC_DIV_INT(uint8_t value) volatile
{
uint32_t curr = CLK_ADC_DIV;
curr &= ~(0b11u << 8u);
curr |= (value & 0b11u) << 8u;
CLK_ADC_DIV = curr;
}
inline CLOCKS_CLK_RTC_CTRL_AUXSRC get_CLK_RTC_CTRL_AUXSRC() volatile
{
return CLOCKS_CLK_RTC_CTRL_AUXSRC((CLK_RTC_CTRL >> 5u) & 0b111u);
}
inline void set_CLK_RTC_CTRL_AUXSRC(
CLOCKS_CLK_RTC_CTRL_AUXSRC value) volatile
{
uint32_t curr = CLK_RTC_CTRL;
curr &= ~(0b111u << 5u);
curr |= (std::to_underlying(value) & 0b111u) << 5u;
CLK_RTC_CTRL = curr;
}
inline bool get_CLK_RTC_CTRL_KILL() volatile
{
return CLK_RTC_CTRL & (1u << 10u);
}
inline void set_CLK_RTC_CTRL_KILL() volatile
{
CLK_RTC_CTRL |= 1u << 10u;
}
inline void clear_CLK_RTC_CTRL_KILL() volatile
{
CLK_RTC_CTRL &= ~(1u << 10u);
}
inline void toggle_CLK_RTC_CTRL_KILL() volatile
{
CLK_RTC_CTRL ^= 1u << 10u;
}
inline bool get_CLK_RTC_CTRL_ENABLE() volatile
{
return CLK_RTC_CTRL & (1u << 11u);
}
inline void set_CLK_RTC_CTRL_ENABLE() volatile
{
CLK_RTC_CTRL |= 1u << 11u;
}
inline void clear_CLK_RTC_CTRL_ENABLE() volatile
{
CLK_RTC_CTRL &= ~(1u << 11u);
}
inline void toggle_CLK_RTC_CTRL_ENABLE() volatile
{
CLK_RTC_CTRL ^= 1u << 11u;
}
inline uint8_t get_CLK_RTC_CTRL_PHASE() volatile
{
return (CLK_RTC_CTRL >> 16u) & 0b11u;
}
inline void set_CLK_RTC_CTRL_PHASE(uint8_t value) volatile
{
uint32_t curr = CLK_RTC_CTRL;
curr &= ~(0b11u << 16u);
curr |= (value & 0b11u) << 16u;
CLK_RTC_CTRL = curr;
}
inline bool get_CLK_RTC_CTRL_NUDGE() volatile
{
return CLK_RTC_CTRL & (1u << 20u);
}
inline void set_CLK_RTC_CTRL_NUDGE() volatile
{
CLK_RTC_CTRL |= 1u << 20u;
}
inline void clear_CLK_RTC_CTRL_NUDGE() volatile
{
CLK_RTC_CTRL &= ~(1u << 20u);
}
inline void toggle_CLK_RTC_CTRL_NUDGE() volatile
{
CLK_RTC_CTRL ^= 1u << 20u;
}
inline void get_CLK_RTC_CTRL(CLOCKS_CLK_RTC_CTRL_AUXSRC &AUXSRC,
bool &KILL, bool &ENABLE, uint8_t &PHASE,
bool &NUDGE) volatile
{
uint32_t curr = CLK_RTC_CTRL;
AUXSRC = CLOCKS_CLK_RTC_CTRL_AUXSRC((curr >> 5u) & 0b111u);
KILL = curr & (1u << 10u);
ENABLE = curr & (1u << 11u);
PHASE = (curr >> 16u) & 0b11u;
NUDGE = curr & (1u << 20u);
}
inline void set_CLK_RTC_CTRL(CLOCKS_CLK_RTC_CTRL_AUXSRC AUXSRC, bool KILL,
bool ENABLE, uint8_t PHASE,
bool NUDGE) volatile
{
uint32_t curr = CLK_RTC_CTRL;
curr &= ~(0b111u << 5u);
curr |= (std::to_underlying(AUXSRC) & 0b111u) << 5u;
curr &= ~(0b1u << 10u);
curr |= (KILL & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (ENABLE & 0b1u) << 11u;
curr &= ~(0b11u << 16u);
curr |= (PHASE & 0b11u) << 16u;
curr &= ~(0b1u << 20u);
curr |= (NUDGE & 0b1u) << 20u;
CLK_RTC_CTRL = curr;
}
inline uint8_t get_CLK_RTC_DIV_FRAC() volatile
{
return (CLK_RTC_DIV >> 0u) & 0b11111111u;
}
inline void set_CLK_RTC_DIV_FRAC(uint8_t value) volatile
{
uint32_t curr = CLK_RTC_DIV;
curr &= ~(0b11111111u << 0u);
curr |= (value & 0b11111111u) << 0u;
CLK_RTC_DIV = curr;
}
inline uint32_t get_CLK_RTC_DIV_INT() volatile
{
return (CLK_RTC_DIV >> 8u) & 0b111111111111111111111111u;
}
inline void set_CLK_RTC_DIV_INT(uint32_t value) volatile
{
uint32_t curr = CLK_RTC_DIV;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (value & 0b111111111111111111111111u) << 8u;
CLK_RTC_DIV = curr;
}
inline void get_CLK_RTC_DIV(uint8_t &FRAC, uint32_t &INT) volatile
{
uint32_t curr = CLK_RTC_DIV;
FRAC = (curr >> 0u) & 0b11111111u;
INT = (curr >> 8u) & 0b111111111111111111111111u;
}
inline void set_CLK_RTC_DIV(uint8_t FRAC, uint32_t INT) volatile
{
uint32_t curr = CLK_RTC_DIV;
curr &= ~(0b11111111u << 0u);
curr |= (FRAC & 0b11111111u) << 0u;
curr &= ~(0b111111111111111111111111u << 8u);
curr |= (INT & 0b111111111111111111111111u) << 8u;
CLK_RTC_DIV = curr;
}
inline uint8_t get_CLK_SYS_RESUS_CTRL_TIMEOUT() volatile
{
return (CLK_SYS_RESUS_CTRL >> 0u) & 0b11111111u;
}
inline void set_CLK_SYS_RESUS_CTRL_TIMEOUT(uint8_t value) volatile
{
uint32_t curr = CLK_SYS_RESUS_CTRL;
curr &= ~(0b11111111u << 0u);
curr |= (value & 0b11111111u) << 0u;
CLK_SYS_RESUS_CTRL = curr;
}
inline bool get_CLK_SYS_RESUS_CTRL_ENABLE() volatile
{
return CLK_SYS_RESUS_CTRL & (1u << 8u);
}
inline void set_CLK_SYS_RESUS_CTRL_ENABLE() volatile
{
CLK_SYS_RESUS_CTRL |= 1u << 8u;
}
inline void clear_CLK_SYS_RESUS_CTRL_ENABLE() volatile
{
CLK_SYS_RESUS_CTRL &= ~(1u << 8u);
}
inline void toggle_CLK_SYS_RESUS_CTRL_ENABLE() volatile
{
CLK_SYS_RESUS_CTRL ^= 1u << 8u;
}
inline bool get_CLK_SYS_RESUS_CTRL_FRCE() volatile
{
return CLK_SYS_RESUS_CTRL & (1u << 12u);
}
inline void set_CLK_SYS_RESUS_CTRL_FRCE() volatile
{
CLK_SYS_RESUS_CTRL |= 1u << 12u;
}
inline void clear_CLK_SYS_RESUS_CTRL_FRCE() volatile
{
CLK_SYS_RESUS_CTRL &= ~(1u << 12u);
}
inline void toggle_CLK_SYS_RESUS_CTRL_FRCE() volatile
{
CLK_SYS_RESUS_CTRL ^= 1u << 12u;
}
inline bool get_CLK_SYS_RESUS_CTRL_CLEAR() volatile
{
return CLK_SYS_RESUS_CTRL & (1u << 16u);
}
inline void set_CLK_SYS_RESUS_CTRL_CLEAR() volatile
{
CLK_SYS_RESUS_CTRL |= 1u << 16u;
}
inline void clear_CLK_SYS_RESUS_CTRL_CLEAR() volatile
{
CLK_SYS_RESUS_CTRL &= ~(1u << 16u);
}
inline void toggle_CLK_SYS_RESUS_CTRL_CLEAR() volatile
{
CLK_SYS_RESUS_CTRL ^= 1u << 16u;
}
inline void get_CLK_SYS_RESUS_CTRL(uint8_t &TIMEOUT, bool &ENABLE,
bool &FRCE, bool &CLEAR) volatile
{
uint32_t curr = CLK_SYS_RESUS_CTRL;
TIMEOUT = (curr >> 0u) & 0b11111111u;
ENABLE = curr & (1u << 8u);
FRCE = curr & (1u << 12u);
CLEAR = curr & (1u << 16u);
}
inline void set_CLK_SYS_RESUS_CTRL(uint8_t TIMEOUT, bool ENABLE, bool FRCE,
bool CLEAR) volatile
{
uint32_t curr = CLK_SYS_RESUS_CTRL;
curr &= ~(0b11111111u << 0u);
curr |= (TIMEOUT & 0b11111111u) << 0u;
curr &= ~(0b1u << 8u);
curr |= (ENABLE & 0b1u) << 8u;
curr &= ~(0b1u << 12u);
curr |= (FRCE & 0b1u) << 12u;
curr &= ~(0b1u << 16u);
curr |= (CLEAR & 0b1u) << 16u;
CLK_SYS_RESUS_CTRL = curr;
}
inline bool get_CLK_SYS_RESUS_STATUS_RESUSSED() volatile
{
return CLK_SYS_RESUS_STATUS & (1u << 0u);
}
inline uint32_t get_FC0_REF_KHZ_FC0_REF_KHZ() volatile
{
return (FC0_REF_KHZ >> 0u) & 0b11111111111111111111u;
}
inline void set_FC0_REF_KHZ_FC0_REF_KHZ(uint32_t value) volatile
{
uint32_t curr = FC0_REF_KHZ;
curr &= ~(0b11111111111111111111u << 0u);
curr |= (value & 0b11111111111111111111u) << 0u;
FC0_REF_KHZ = curr;
}
inline uint32_t get_FC0_MIN_KHZ_FC0_MIN_KHZ() volatile
{
return (FC0_MIN_KHZ >> 0u) & 0b1111111111111111111111111u;
}
inline void set_FC0_MIN_KHZ_FC0_MIN_KHZ(uint32_t value) volatile
{
uint32_t curr = FC0_MIN_KHZ;
curr &= ~(0b1111111111111111111111111u << 0u);
curr |= (value & 0b1111111111111111111111111u) << 0u;
FC0_MIN_KHZ = curr;
}
inline uint32_t get_FC0_MAX_KHZ_FC0_MAX_KHZ() volatile
{
return (FC0_MAX_KHZ >> 0u) & 0b1111111111111111111111111u;
}
inline void set_FC0_MAX_KHZ_FC0_MAX_KHZ(uint32_t value) volatile
{
uint32_t curr = FC0_MAX_KHZ;
curr &= ~(0b1111111111111111111111111u << 0u);
curr |= (value & 0b1111111111111111111111111u) << 0u;
FC0_MAX_KHZ = curr;
}
inline uint8_t get_FC0_DELAY_FC0_DELAY() volatile
{
return (FC0_DELAY >> 0u) & 0b111u;
}
inline void set_FC0_DELAY_FC0_DELAY(uint8_t value) volatile
{
uint32_t curr = FC0_DELAY;
curr &= ~(0b111u << 0u);
curr |= (value & 0b111u) << 0u;
FC0_DELAY = curr;
}
inline uint8_t get_FC0_INTERVAL_FC0_INTERVAL() volatile
{
return (FC0_INTERVAL >> 0u) & 0b1111u;
}
inline void set_FC0_INTERVAL_FC0_INTERVAL(uint8_t value) volatile
{
uint32_t curr = FC0_INTERVAL;
curr &= ~(0b1111u << 0u);
curr |= (value & 0b1111u) << 0u;
FC0_INTERVAL = curr;
}
inline CLOCKS_FC0_SRC_FC0_SRC get_FC0_SRC_FC0_SRC() volatile
{
return CLOCKS_FC0_SRC_FC0_SRC((FC0_SRC >> 0u) & 0b11111111u);
}
inline void set_FC0_SRC_FC0_SRC(CLOCKS_FC0_SRC_FC0_SRC value) volatile
{
uint32_t curr = FC0_SRC;
curr &= ~(0b11111111u << 0u);
curr |= (std::to_underlying(value) & 0b11111111u) << 0u;
FC0_SRC = curr;
}
inline bool get_FC0_STATUS_PASS() volatile
{
return FC0_STATUS & (1u << 0u);
}
inline bool get_FC0_STATUS_DONE() volatile
{
return FC0_STATUS & (1u << 4u);
}
inline bool get_FC0_STATUS_RUNNING() volatile
{
return FC0_STATUS & (1u << 8u);
}
inline bool get_FC0_STATUS_WAITING() volatile
{
return FC0_STATUS & (1u << 12u);
}
inline bool get_FC0_STATUS_FAIL() volatile
{
return FC0_STATUS & (1u << 16u);
}
inline bool get_FC0_STATUS_SLOW() volatile
{
return FC0_STATUS & (1u << 20u);
}
inline bool get_FC0_STATUS_FAST() volatile
{
return FC0_STATUS & (1u << 24u);
}
inline bool get_FC0_STATUS_DIED() volatile
{
return FC0_STATUS & (1u << 28u);
}
inline void get_FC0_STATUS(bool &PASS, bool &DONE, bool &RUNNING,
bool &WAITING, bool &FAIL, bool &SLOW,
bool &FAST, bool &DIED) volatile
{
uint32_t curr = FC0_STATUS;
PASS = curr & (1u << 0u);
DONE = curr & (1u << 4u);
RUNNING = curr & (1u << 8u);
WAITING = curr & (1u << 12u);
FAIL = curr & (1u << 16u);
SLOW = curr & (1u << 20u);
FAST = curr & (1u << 24u);
DIED = curr & (1u << 28u);
}
inline uint8_t get_FC0_RESULT_FRAC() volatile
{
return (FC0_RESULT >> 0u) & 0b11111u;
}
inline uint32_t get_FC0_RESULT_KHZ() volatile
{
return (FC0_RESULT >> 5u) & 0b1111111111111111111111111u;
}
inline void get_FC0_RESULT(uint8_t &FRAC, uint32_t &KHZ) volatile
{
uint32_t curr = FC0_RESULT;
FRAC = (curr >> 0u) & 0b11111u;
KHZ = (curr >> 5u) & 0b1111111111111111111111111u;
}
inline bool get_WAKE_EN0_clk_sys_clocks() volatile
{
return WAKE_EN0 & (1u << 0u);
}
inline void set_WAKE_EN0_clk_sys_clocks() volatile
{
WAKE_EN0 |= 1u << 0u;
}
inline void clear_WAKE_EN0_clk_sys_clocks() volatile
{
WAKE_EN0 &= ~(1u << 0u);
}
inline void toggle_WAKE_EN0_clk_sys_clocks() volatile
{
WAKE_EN0 ^= 1u << 0u;
}
inline bool get_WAKE_EN0_clk_adc_adc() volatile
{
return WAKE_EN0 & (1u << 1u);
}
inline void set_WAKE_EN0_clk_adc_adc() volatile
{
WAKE_EN0 |= 1u << 1u;
}
inline void clear_WAKE_EN0_clk_adc_adc() volatile
{
WAKE_EN0 &= ~(1u << 1u);
}
inline void toggle_WAKE_EN0_clk_adc_adc() volatile
{
WAKE_EN0 ^= 1u << 1u;
}
inline bool get_WAKE_EN0_clk_sys_adc() volatile
{
return WAKE_EN0 & (1u << 2u);
}
inline void set_WAKE_EN0_clk_sys_adc() volatile
{
WAKE_EN0 |= 1u << 2u;
}
inline void clear_WAKE_EN0_clk_sys_adc() volatile
{
WAKE_EN0 &= ~(1u << 2u);
}
inline void toggle_WAKE_EN0_clk_sys_adc() volatile
{
WAKE_EN0 ^= 1u << 2u;
}
inline bool get_WAKE_EN0_clk_sys_busctrl() volatile
{
return WAKE_EN0 & (1u << 3u);
}
inline void set_WAKE_EN0_clk_sys_busctrl() volatile
{
WAKE_EN0 |= 1u << 3u;
}
inline void clear_WAKE_EN0_clk_sys_busctrl() volatile
{
WAKE_EN0 &= ~(1u << 3u);
}
inline void toggle_WAKE_EN0_clk_sys_busctrl() volatile
{
WAKE_EN0 ^= 1u << 3u;
}
inline bool get_WAKE_EN0_clk_sys_busfabric() volatile
{
return WAKE_EN0 & (1u << 4u);
}
inline void set_WAKE_EN0_clk_sys_busfabric() volatile
{
WAKE_EN0 |= 1u << 4u;
}
inline void clear_WAKE_EN0_clk_sys_busfabric() volatile
{
WAKE_EN0 &= ~(1u << 4u);
}
inline void toggle_WAKE_EN0_clk_sys_busfabric() volatile
{
WAKE_EN0 ^= 1u << 4u;
}
inline bool get_WAKE_EN0_clk_sys_dma() volatile
{
return WAKE_EN0 & (1u << 5u);
}
inline void set_WAKE_EN0_clk_sys_dma() volatile
{
WAKE_EN0 |= 1u << 5u;
}
inline void clear_WAKE_EN0_clk_sys_dma() volatile
{
WAKE_EN0 &= ~(1u << 5u);
}
inline void toggle_WAKE_EN0_clk_sys_dma() volatile
{
WAKE_EN0 ^= 1u << 5u;
}
inline bool get_WAKE_EN0_clk_sys_i2c0() volatile
{
return WAKE_EN0 & (1u << 6u);
}
inline void set_WAKE_EN0_clk_sys_i2c0() volatile
{
WAKE_EN0 |= 1u << 6u;
}
inline void clear_WAKE_EN0_clk_sys_i2c0() volatile
{
WAKE_EN0 &= ~(1u << 6u);
}
inline void toggle_WAKE_EN0_clk_sys_i2c0() volatile
{
WAKE_EN0 ^= 1u << 6u;
}
inline bool get_WAKE_EN0_clk_sys_i2c1() volatile
{
return WAKE_EN0 & (1u << 7u);
}
inline void set_WAKE_EN0_clk_sys_i2c1() volatile
{
WAKE_EN0 |= 1u << 7u;
}
inline void clear_WAKE_EN0_clk_sys_i2c1() volatile
{
WAKE_EN0 &= ~(1u << 7u);
}
inline void toggle_WAKE_EN0_clk_sys_i2c1() volatile
{
WAKE_EN0 ^= 1u << 7u;
}
inline bool get_WAKE_EN0_clk_sys_io() volatile
{
return WAKE_EN0 & (1u << 8u);
}
inline void set_WAKE_EN0_clk_sys_io() volatile
{
WAKE_EN0 |= 1u << 8u;
}
inline void clear_WAKE_EN0_clk_sys_io() volatile
{
WAKE_EN0 &= ~(1u << 8u);
}
inline void toggle_WAKE_EN0_clk_sys_io() volatile
{
WAKE_EN0 ^= 1u << 8u;
}
inline bool get_WAKE_EN0_clk_sys_jtag() volatile
{
return WAKE_EN0 & (1u << 9u);
}
inline void set_WAKE_EN0_clk_sys_jtag() volatile
{
WAKE_EN0 |= 1u << 9u;
}
inline void clear_WAKE_EN0_clk_sys_jtag() volatile
{
WAKE_EN0 &= ~(1u << 9u);
}
inline void toggle_WAKE_EN0_clk_sys_jtag() volatile
{
WAKE_EN0 ^= 1u << 9u;
}
inline bool get_WAKE_EN0_clk_sys_vreg_and_chip_reset() volatile
{
return WAKE_EN0 & (1u << 10u);
}
inline void set_WAKE_EN0_clk_sys_vreg_and_chip_reset() volatile
{
WAKE_EN0 |= 1u << 10u;
}
inline void clear_WAKE_EN0_clk_sys_vreg_and_chip_reset() volatile
{
WAKE_EN0 &= ~(1u << 10u);
}
inline void toggle_WAKE_EN0_clk_sys_vreg_and_chip_reset() volatile
{
WAKE_EN0 ^= 1u << 10u;
}
inline bool get_WAKE_EN0_clk_sys_pads() volatile
{
return WAKE_EN0 & (1u << 11u);
}
inline void set_WAKE_EN0_clk_sys_pads() volatile
{
WAKE_EN0 |= 1u << 11u;
}
inline void clear_WAKE_EN0_clk_sys_pads() volatile
{
WAKE_EN0 &= ~(1u << 11u);
}
inline void toggle_WAKE_EN0_clk_sys_pads() volatile
{
WAKE_EN0 ^= 1u << 11u;
}
inline bool get_WAKE_EN0_clk_sys_pio0() volatile
{
return WAKE_EN0 & (1u << 12u);
}
inline void set_WAKE_EN0_clk_sys_pio0() volatile
{
WAKE_EN0 |= 1u << 12u;
}
inline void clear_WAKE_EN0_clk_sys_pio0() volatile
{
WAKE_EN0 &= ~(1u << 12u);
}
inline void toggle_WAKE_EN0_clk_sys_pio0() volatile
{
WAKE_EN0 ^= 1u << 12u;
}
inline bool get_WAKE_EN0_clk_sys_pio1() volatile
{
return WAKE_EN0 & (1u << 13u);
}
inline void set_WAKE_EN0_clk_sys_pio1() volatile
{
WAKE_EN0 |= 1u << 13u;
}
inline void clear_WAKE_EN0_clk_sys_pio1() volatile
{
WAKE_EN0 &= ~(1u << 13u);
}
inline void toggle_WAKE_EN0_clk_sys_pio1() volatile
{
WAKE_EN0 ^= 1u << 13u;
}
inline bool get_WAKE_EN0_clk_sys_pll_sys() volatile
{
return WAKE_EN0 & (1u << 14u);
}
inline void set_WAKE_EN0_clk_sys_pll_sys() volatile
{
WAKE_EN0 |= 1u << 14u;
}
inline void clear_WAKE_EN0_clk_sys_pll_sys() volatile
{
WAKE_EN0 &= ~(1u << 14u);
}
inline void toggle_WAKE_EN0_clk_sys_pll_sys() volatile
{
WAKE_EN0 ^= 1u << 14u;
}
inline bool get_WAKE_EN0_clk_sys_pll_usb() volatile
{
return WAKE_EN0 & (1u << 15u);
}
inline void set_WAKE_EN0_clk_sys_pll_usb() volatile
{
WAKE_EN0 |= 1u << 15u;
}
inline void clear_WAKE_EN0_clk_sys_pll_usb() volatile
{
WAKE_EN0 &= ~(1u << 15u);
}
inline void toggle_WAKE_EN0_clk_sys_pll_usb() volatile
{
WAKE_EN0 ^= 1u << 15u;
}
inline bool get_WAKE_EN0_clk_sys_psm() volatile
{
return WAKE_EN0 & (1u << 16u);
}
inline void set_WAKE_EN0_clk_sys_psm() volatile
{
WAKE_EN0 |= 1u << 16u;
}
inline void clear_WAKE_EN0_clk_sys_psm() volatile
{
WAKE_EN0 &= ~(1u << 16u);
}
inline void toggle_WAKE_EN0_clk_sys_psm() volatile
{
WAKE_EN0 ^= 1u << 16u;
}
inline bool get_WAKE_EN0_clk_sys_pwm() volatile
{
return WAKE_EN0 & (1u << 17u);
}
inline void set_WAKE_EN0_clk_sys_pwm() volatile
{
WAKE_EN0 |= 1u << 17u;
}
inline void clear_WAKE_EN0_clk_sys_pwm() volatile
{
WAKE_EN0 &= ~(1u << 17u);
}
inline void toggle_WAKE_EN0_clk_sys_pwm() volatile
{
WAKE_EN0 ^= 1u << 17u;
}
inline bool get_WAKE_EN0_clk_sys_resets() volatile
{
return WAKE_EN0 & (1u << 18u);
}
inline void set_WAKE_EN0_clk_sys_resets() volatile
{
WAKE_EN0 |= 1u << 18u;
}
inline void clear_WAKE_EN0_clk_sys_resets() volatile
{
WAKE_EN0 &= ~(1u << 18u);
}
inline void toggle_WAKE_EN0_clk_sys_resets() volatile
{
WAKE_EN0 ^= 1u << 18u;
}
inline bool get_WAKE_EN0_clk_sys_rom() volatile
{
return WAKE_EN0 & (1u << 19u);
}
inline void set_WAKE_EN0_clk_sys_rom() volatile
{
WAKE_EN0 |= 1u << 19u;
}
inline void clear_WAKE_EN0_clk_sys_rom() volatile
{
WAKE_EN0 &= ~(1u << 19u);
}
inline void toggle_WAKE_EN0_clk_sys_rom() volatile
{
WAKE_EN0 ^= 1u << 19u;
}
inline bool get_WAKE_EN0_clk_sys_rosc() volatile
{
return WAKE_EN0 & (1u << 20u);
}
inline void set_WAKE_EN0_clk_sys_rosc() volatile
{
WAKE_EN0 |= 1u << 20u;
}
inline void clear_WAKE_EN0_clk_sys_rosc() volatile
{
WAKE_EN0 &= ~(1u << 20u);
}
inline void toggle_WAKE_EN0_clk_sys_rosc() volatile
{
WAKE_EN0 ^= 1u << 20u;
}
inline bool get_WAKE_EN0_clk_rtc_rtc() volatile
{
return WAKE_EN0 & (1u << 21u);
}
inline void set_WAKE_EN0_clk_rtc_rtc() volatile
{
WAKE_EN0 |= 1u << 21u;
}
inline void clear_WAKE_EN0_clk_rtc_rtc() volatile
{
WAKE_EN0 &= ~(1u << 21u);
}
inline void toggle_WAKE_EN0_clk_rtc_rtc() volatile
{
WAKE_EN0 ^= 1u << 21u;
}
inline bool get_WAKE_EN0_clk_sys_rtc() volatile
{
return WAKE_EN0 & (1u << 22u);
}
inline void set_WAKE_EN0_clk_sys_rtc() volatile
{
WAKE_EN0 |= 1u << 22u;
}
inline void clear_WAKE_EN0_clk_sys_rtc() volatile
{
WAKE_EN0 &= ~(1u << 22u);
}
inline void toggle_WAKE_EN0_clk_sys_rtc() volatile
{
WAKE_EN0 ^= 1u << 22u;
}
inline bool get_WAKE_EN0_clk_sys_sio() volatile
{
return WAKE_EN0 & (1u << 23u);
}
inline void set_WAKE_EN0_clk_sys_sio() volatile
{
WAKE_EN0 |= 1u << 23u;
}
inline void clear_WAKE_EN0_clk_sys_sio() volatile
{
WAKE_EN0 &= ~(1u << 23u);
}
inline void toggle_WAKE_EN0_clk_sys_sio() volatile
{
WAKE_EN0 ^= 1u << 23u;
}
inline bool get_WAKE_EN0_clk_peri_spi0() volatile
{
return WAKE_EN0 & (1u << 24u);
}
inline void set_WAKE_EN0_clk_peri_spi0() volatile
{
WAKE_EN0 |= 1u << 24u;
}
inline void clear_WAKE_EN0_clk_peri_spi0() volatile
{
WAKE_EN0 &= ~(1u << 24u);
}
inline void toggle_WAKE_EN0_clk_peri_spi0() volatile
{
WAKE_EN0 ^= 1u << 24u;
}
inline bool get_WAKE_EN0_clk_sys_spi0() volatile
{
return WAKE_EN0 & (1u << 25u);
}
inline void set_WAKE_EN0_clk_sys_spi0() volatile
{
WAKE_EN0 |= 1u << 25u;
}
inline void clear_WAKE_EN0_clk_sys_spi0() volatile
{
WAKE_EN0 &= ~(1u << 25u);
}
inline void toggle_WAKE_EN0_clk_sys_spi0() volatile
{
WAKE_EN0 ^= 1u << 25u;
}
inline bool get_WAKE_EN0_clk_peri_spi1() volatile
{
return WAKE_EN0 & (1u << 26u);
}
inline void set_WAKE_EN0_clk_peri_spi1() volatile
{
WAKE_EN0 |= 1u << 26u;
}
inline void clear_WAKE_EN0_clk_peri_spi1() volatile
{
WAKE_EN0 &= ~(1u << 26u);
}
inline void toggle_WAKE_EN0_clk_peri_spi1() volatile
{
WAKE_EN0 ^= 1u << 26u;
}
inline bool get_WAKE_EN0_clk_sys_spi1() volatile
{
return WAKE_EN0 & (1u << 27u);
}
inline void set_WAKE_EN0_clk_sys_spi1() volatile
{
WAKE_EN0 |= 1u << 27u;
}
inline void clear_WAKE_EN0_clk_sys_spi1() volatile
{
WAKE_EN0 &= ~(1u << 27u);
}
inline void toggle_WAKE_EN0_clk_sys_spi1() volatile
{
WAKE_EN0 ^= 1u << 27u;
}
inline bool get_WAKE_EN0_clk_sys_sram0() volatile
{
return WAKE_EN0 & (1u << 28u);
}
inline void set_WAKE_EN0_clk_sys_sram0() volatile
{
WAKE_EN0 |= 1u << 28u;
}
inline void clear_WAKE_EN0_clk_sys_sram0() volatile
{
WAKE_EN0 &= ~(1u << 28u);
}
inline void toggle_WAKE_EN0_clk_sys_sram0() volatile
{
WAKE_EN0 ^= 1u << 28u;
}
inline bool get_WAKE_EN0_clk_sys_sram1() volatile
{
return WAKE_EN0 & (1u << 29u);
}
inline void set_WAKE_EN0_clk_sys_sram1() volatile
{
WAKE_EN0 |= 1u << 29u;
}
inline void clear_WAKE_EN0_clk_sys_sram1() volatile
{
WAKE_EN0 &= ~(1u << 29u);
}
inline void toggle_WAKE_EN0_clk_sys_sram1() volatile
{
WAKE_EN0 ^= 1u << 29u;
}
inline bool get_WAKE_EN0_clk_sys_sram2() volatile
{
return WAKE_EN0 & (1u << 30u);
}
inline void set_WAKE_EN0_clk_sys_sram2() volatile
{
WAKE_EN0 |= 1u << 30u;
}
inline void clear_WAKE_EN0_clk_sys_sram2() volatile
{
WAKE_EN0 &= ~(1u << 30u);
}
inline void toggle_WAKE_EN0_clk_sys_sram2() volatile
{
WAKE_EN0 ^= 1u << 30u;
}
inline bool get_WAKE_EN0_clk_sys_sram3() volatile
{
return WAKE_EN0 & (1u << 31u);
}
inline void set_WAKE_EN0_clk_sys_sram3() volatile
{
WAKE_EN0 |= 1u << 31u;
}
inline void clear_WAKE_EN0_clk_sys_sram3() volatile
{
WAKE_EN0 &= ~(1u << 31u);
}
inline void toggle_WAKE_EN0_clk_sys_sram3() volatile
{
WAKE_EN0 ^= 1u << 31u;
}
inline void get_WAKE_EN0(
bool &clk_sys_clocks, bool &clk_adc_adc, bool &clk_sys_adc,
bool &clk_sys_busctrl, bool &clk_sys_busfabric, bool &clk_sys_dma,
bool &clk_sys_i2c0, bool &clk_sys_i2c1, bool &clk_sys_io,
bool &clk_sys_jtag, bool &clk_sys_vreg_and_chip_reset,
bool &clk_sys_pads, bool &clk_sys_pio0, bool &clk_sys_pio1,
bool &clk_sys_pll_sys, bool &clk_sys_pll_usb, bool &clk_sys_psm,
bool &clk_sys_pwm, bool &clk_sys_resets, bool &clk_sys_rom,
bool &clk_sys_rosc, bool &clk_rtc_rtc, bool &clk_sys_rtc,
bool &clk_sys_sio, bool &clk_peri_spi0, bool &clk_sys_spi0,
bool &clk_peri_spi1, bool &clk_sys_spi1, bool &clk_sys_sram0,
bool &clk_sys_sram1, bool &clk_sys_sram2, bool &clk_sys_sram3) volatile
{
uint32_t curr = WAKE_EN0;
clk_sys_clocks = curr & (1u << 0u);
clk_adc_adc = curr & (1u << 1u);
clk_sys_adc = curr & (1u << 2u);
clk_sys_busctrl = curr & (1u << 3u);
clk_sys_busfabric = curr & (1u << 4u);
clk_sys_dma = curr & (1u << 5u);
clk_sys_i2c0 = curr & (1u << 6u);
clk_sys_i2c1 = curr & (1u << 7u);
clk_sys_io = curr & (1u << 8u);
clk_sys_jtag = curr & (1u << 9u);
clk_sys_vreg_and_chip_reset = curr & (1u << 10u);
clk_sys_pads = curr & (1u << 11u);
clk_sys_pio0 = curr & (1u << 12u);
clk_sys_pio1 = curr & (1u << 13u);
clk_sys_pll_sys = curr & (1u << 14u);
clk_sys_pll_usb = curr & (1u << 15u);
clk_sys_psm = curr & (1u << 16u);
clk_sys_pwm = curr & (1u << 17u);
clk_sys_resets = curr & (1u << 18u);
clk_sys_rom = curr & (1u << 19u);
clk_sys_rosc = curr & (1u << 20u);
clk_rtc_rtc = curr & (1u << 21u);
clk_sys_rtc = curr & (1u << 22u);
clk_sys_sio = curr & (1u << 23u);
clk_peri_spi0 = curr & (1u << 24u);
clk_sys_spi0 = curr & (1u << 25u);
clk_peri_spi1 = curr & (1u << 26u);
clk_sys_spi1 = curr & (1u << 27u);
clk_sys_sram0 = curr & (1u << 28u);
clk_sys_sram1 = curr & (1u << 29u);
clk_sys_sram2 = curr & (1u << 30u);
clk_sys_sram3 = curr & (1u << 31u);
}
inline void set_WAKE_EN0(
bool clk_sys_clocks, bool clk_adc_adc, bool clk_sys_adc,
bool clk_sys_busctrl, bool clk_sys_busfabric, bool clk_sys_dma,
bool clk_sys_i2c0, bool clk_sys_i2c1, bool clk_sys_io,
bool clk_sys_jtag, bool clk_sys_vreg_and_chip_reset, bool clk_sys_pads,
bool clk_sys_pio0, bool clk_sys_pio1, bool clk_sys_pll_sys,
bool clk_sys_pll_usb, bool clk_sys_psm, bool clk_sys_pwm,
bool clk_sys_resets, bool clk_sys_rom, bool clk_sys_rosc,
bool clk_rtc_rtc, bool clk_sys_rtc, bool clk_sys_sio,
bool clk_peri_spi0, bool clk_sys_spi0, bool clk_peri_spi1,
bool clk_sys_spi1, bool clk_sys_sram0, bool clk_sys_sram1,
bool clk_sys_sram2, bool clk_sys_sram3) volatile
{
uint32_t curr = WAKE_EN0;
curr &= ~(0b1u << 0u);
curr |= (clk_sys_clocks & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (clk_adc_adc & 0b1u) << 1u;
curr &= ~(0b1u << 2u);
curr |= (clk_sys_adc & 0b1u) << 2u;
curr &= ~(0b1u << 3u);
curr |= (clk_sys_busctrl & 0b1u) << 3u;
curr &= ~(0b1u << 4u);
curr |= (clk_sys_busfabric & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (clk_sys_dma & 0b1u) << 5u;
curr &= ~(0b1u << 6u);
curr |= (clk_sys_i2c0 & 0b1u) << 6u;
curr &= ~(0b1u << 7u);
curr |= (clk_sys_i2c1 & 0b1u) << 7u;
curr &= ~(0b1u << 8u);
curr |= (clk_sys_io & 0b1u) << 8u;
curr &= ~(0b1u << 9u);
curr |= (clk_sys_jtag & 0b1u) << 9u;
curr &= ~(0b1u << 10u);
curr |= (clk_sys_vreg_and_chip_reset & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (clk_sys_pads & 0b1u) << 11u;
curr &= ~(0b1u << 12u);
curr |= (clk_sys_pio0 & 0b1u) << 12u;
curr &= ~(0b1u << 13u);
curr |= (clk_sys_pio1 & 0b1u) << 13u;
curr &= ~(0b1u << 14u);
curr |= (clk_sys_pll_sys & 0b1u) << 14u;
curr &= ~(0b1u << 15u);
curr |= (clk_sys_pll_usb & 0b1u) << 15u;
curr &= ~(0b1u << 16u);
curr |= (clk_sys_psm & 0b1u) << 16u;
curr &= ~(0b1u << 17u);
curr |= (clk_sys_pwm & 0b1u) << 17u;
curr &= ~(0b1u << 18u);
curr |= (clk_sys_resets & 0b1u) << 18u;
curr &= ~(0b1u << 19u);
curr |= (clk_sys_rom & 0b1u) << 19u;
curr &= ~(0b1u << 20u);
curr |= (clk_sys_rosc & 0b1u) << 20u;
curr &= ~(0b1u << 21u);
curr |= (clk_rtc_rtc & 0b1u) << 21u;
curr &= ~(0b1u << 22u);
curr |= (clk_sys_rtc & 0b1u) << 22u;
curr &= ~(0b1u << 23u);
curr |= (clk_sys_sio & 0b1u) << 23u;
curr &= ~(0b1u << 24u);
curr |= (clk_peri_spi0 & 0b1u) << 24u;
curr &= ~(0b1u << 25u);
curr |= (clk_sys_spi0 & 0b1u) << 25u;
curr &= ~(0b1u << 26u);
curr |= (clk_peri_spi1 & 0b1u) << 26u;
curr &= ~(0b1u << 27u);
curr |= (clk_sys_spi1 & 0b1u) << 27u;
curr &= ~(0b1u << 28u);
curr |= (clk_sys_sram0 & 0b1u) << 28u;
curr &= ~(0b1u << 29u);
curr |= (clk_sys_sram1 & 0b1u) << 29u;
curr &= ~(0b1u << 30u);
curr |= (clk_sys_sram2 & 0b1u) << 30u;
curr &= ~(0b1u << 31u);
curr |= (clk_sys_sram3 & 0b1u) << 31u;
WAKE_EN0 = curr;
}
inline bool get_WAKE_EN1_clk_sys_sram4() volatile
{
return WAKE_EN1 & (1u << 0u);
}
inline void set_WAKE_EN1_clk_sys_sram4() volatile
{
WAKE_EN1 |= 1u << 0u;
}
inline void clear_WAKE_EN1_clk_sys_sram4() volatile
{
WAKE_EN1 &= ~(1u << 0u);
}
inline void toggle_WAKE_EN1_clk_sys_sram4() volatile
{
WAKE_EN1 ^= 1u << 0u;
}
inline bool get_WAKE_EN1_clk_sys_sram5() volatile
{
return WAKE_EN1 & (1u << 1u);
}
inline void set_WAKE_EN1_clk_sys_sram5() volatile
{
WAKE_EN1 |= 1u << 1u;
}
inline void clear_WAKE_EN1_clk_sys_sram5() volatile
{
WAKE_EN1 &= ~(1u << 1u);
}
inline void toggle_WAKE_EN1_clk_sys_sram5() volatile
{
WAKE_EN1 ^= 1u << 1u;
}
inline bool get_WAKE_EN1_clk_sys_syscfg() volatile
{
return WAKE_EN1 & (1u << 2u);
}
inline void set_WAKE_EN1_clk_sys_syscfg() volatile
{
WAKE_EN1 |= 1u << 2u;
}
inline void clear_WAKE_EN1_clk_sys_syscfg() volatile
{
WAKE_EN1 &= ~(1u << 2u);
}
inline void toggle_WAKE_EN1_clk_sys_syscfg() volatile
{
WAKE_EN1 ^= 1u << 2u;
}
inline bool get_WAKE_EN1_clk_sys_sysinfo() volatile
{
return WAKE_EN1 & (1u << 3u);
}
inline void set_WAKE_EN1_clk_sys_sysinfo() volatile
{
WAKE_EN1 |= 1u << 3u;
}
inline void clear_WAKE_EN1_clk_sys_sysinfo() volatile
{
WAKE_EN1 &= ~(1u << 3u);
}
inline void toggle_WAKE_EN1_clk_sys_sysinfo() volatile
{
WAKE_EN1 ^= 1u << 3u;
}
inline bool get_WAKE_EN1_clk_sys_tbman() volatile
{
return WAKE_EN1 & (1u << 4u);
}
inline void set_WAKE_EN1_clk_sys_tbman() volatile
{
WAKE_EN1 |= 1u << 4u;
}
inline void clear_WAKE_EN1_clk_sys_tbman() volatile
{
WAKE_EN1 &= ~(1u << 4u);
}
inline void toggle_WAKE_EN1_clk_sys_tbman() volatile
{
WAKE_EN1 ^= 1u << 4u;
}
inline bool get_WAKE_EN1_clk_sys_timer() volatile
{
return WAKE_EN1 & (1u << 5u);
}
inline void set_WAKE_EN1_clk_sys_timer() volatile
{
WAKE_EN1 |= 1u << 5u;
}
inline void clear_WAKE_EN1_clk_sys_timer() volatile
{
WAKE_EN1 &= ~(1u << 5u);
}
inline void toggle_WAKE_EN1_clk_sys_timer() volatile
{
WAKE_EN1 ^= 1u << 5u;
}
inline bool get_WAKE_EN1_clk_peri_uart0() volatile
{
return WAKE_EN1 & (1u << 6u);
}
inline void set_WAKE_EN1_clk_peri_uart0() volatile
{
WAKE_EN1 |= 1u << 6u;
}
inline void clear_WAKE_EN1_clk_peri_uart0() volatile
{
WAKE_EN1 &= ~(1u << 6u);
}
inline void toggle_WAKE_EN1_clk_peri_uart0() volatile
{
WAKE_EN1 ^= 1u << 6u;
}
inline bool get_WAKE_EN1_clk_sys_uart0() volatile
{
return WAKE_EN1 & (1u << 7u);
}
inline void set_WAKE_EN1_clk_sys_uart0() volatile
{
WAKE_EN1 |= 1u << 7u;
}
inline void clear_WAKE_EN1_clk_sys_uart0() volatile
{
WAKE_EN1 &= ~(1u << 7u);
}
inline void toggle_WAKE_EN1_clk_sys_uart0() volatile
{
WAKE_EN1 ^= 1u << 7u;
}
inline bool get_WAKE_EN1_clk_peri_uart1() volatile
{
return WAKE_EN1 & (1u << 8u);
}
inline void set_WAKE_EN1_clk_peri_uart1() volatile
{
WAKE_EN1 |= 1u << 8u;
}
inline void clear_WAKE_EN1_clk_peri_uart1() volatile
{
WAKE_EN1 &= ~(1u << 8u);
}
inline void toggle_WAKE_EN1_clk_peri_uart1() volatile
{
WAKE_EN1 ^= 1u << 8u;
}
inline bool get_WAKE_EN1_clk_sys_uart1() volatile
{
return WAKE_EN1 & (1u << 9u);
}
inline void set_WAKE_EN1_clk_sys_uart1() volatile
{
WAKE_EN1 |= 1u << 9u;
}
inline void clear_WAKE_EN1_clk_sys_uart1() volatile
{
WAKE_EN1 &= ~(1u << 9u);
}
inline void toggle_WAKE_EN1_clk_sys_uart1() volatile
{
WAKE_EN1 ^= 1u << 9u;
}
inline bool get_WAKE_EN1_clk_sys_usbctrl() volatile
{
return WAKE_EN1 & (1u << 10u);
}
inline void set_WAKE_EN1_clk_sys_usbctrl() volatile
{
WAKE_EN1 |= 1u << 10u;
}
inline void clear_WAKE_EN1_clk_sys_usbctrl() volatile
{
WAKE_EN1 &= ~(1u << 10u);
}
inline void toggle_WAKE_EN1_clk_sys_usbctrl() volatile
{
WAKE_EN1 ^= 1u << 10u;
}
inline bool get_WAKE_EN1_clk_usb_usbctrl() volatile
{
return WAKE_EN1 & (1u << 11u);
}
inline void set_WAKE_EN1_clk_usb_usbctrl() volatile
{
WAKE_EN1 |= 1u << 11u;
}
inline void clear_WAKE_EN1_clk_usb_usbctrl() volatile
{
WAKE_EN1 &= ~(1u << 11u);
}
inline void toggle_WAKE_EN1_clk_usb_usbctrl() volatile
{
WAKE_EN1 ^= 1u << 11u;
}
inline bool get_WAKE_EN1_clk_sys_watchdog() volatile
{
return WAKE_EN1 & (1u << 12u);
}
inline void set_WAKE_EN1_clk_sys_watchdog() volatile
{
WAKE_EN1 |= 1u << 12u;
}
inline void clear_WAKE_EN1_clk_sys_watchdog() volatile
{
WAKE_EN1 &= ~(1u << 12u);
}
inline void toggle_WAKE_EN1_clk_sys_watchdog() volatile
{
WAKE_EN1 ^= 1u << 12u;
}
inline bool get_WAKE_EN1_clk_sys_xip() volatile
{
return WAKE_EN1 & (1u << 13u);
}
inline void set_WAKE_EN1_clk_sys_xip() volatile
{
WAKE_EN1 |= 1u << 13u;
}
inline void clear_WAKE_EN1_clk_sys_xip() volatile
{
WAKE_EN1 &= ~(1u << 13u);
}
inline void toggle_WAKE_EN1_clk_sys_xip() volatile
{
WAKE_EN1 ^= 1u << 13u;
}
inline bool get_WAKE_EN1_clk_sys_xosc() volatile
{
return WAKE_EN1 & (1u << 14u);
}
inline void set_WAKE_EN1_clk_sys_xosc() volatile
{
WAKE_EN1 |= 1u << 14u;
}
inline void clear_WAKE_EN1_clk_sys_xosc() volatile
{
WAKE_EN1 &= ~(1u << 14u);
}
inline void toggle_WAKE_EN1_clk_sys_xosc() volatile
{
WAKE_EN1 ^= 1u << 14u;
}
inline void get_WAKE_EN1(bool &clk_sys_sram4, bool &clk_sys_sram5,
bool &clk_sys_syscfg, bool &clk_sys_sysinfo,
bool &clk_sys_tbman, bool &clk_sys_timer,
bool &clk_peri_uart0, bool &clk_sys_uart0,
bool &clk_peri_uart1, bool &clk_sys_uart1,
bool &clk_sys_usbctrl, bool &clk_usb_usbctrl,
bool &clk_sys_watchdog, bool &clk_sys_xip,
bool &clk_sys_xosc) volatile
{
uint32_t curr = WAKE_EN1;
clk_sys_sram4 = curr & (1u << 0u);
clk_sys_sram5 = curr & (1u << 1u);
clk_sys_syscfg = curr & (1u << 2u);
clk_sys_sysinfo = curr & (1u << 3u);
clk_sys_tbman = curr & (1u << 4u);
clk_sys_timer = curr & (1u << 5u);
clk_peri_uart0 = curr & (1u << 6u);
clk_sys_uart0 = curr & (1u << 7u);
clk_peri_uart1 = curr & (1u << 8u);
clk_sys_uart1 = curr & (1u << 9u);
clk_sys_usbctrl = curr & (1u << 10u);
clk_usb_usbctrl = curr & (1u << 11u);
clk_sys_watchdog = curr & (1u << 12u);
clk_sys_xip = curr & (1u << 13u);
clk_sys_xosc = curr & (1u << 14u);
}
inline void set_WAKE_EN1(bool clk_sys_sram4, bool clk_sys_sram5,
bool clk_sys_syscfg, bool clk_sys_sysinfo,
bool clk_sys_tbman, bool clk_sys_timer,
bool clk_peri_uart0, bool clk_sys_uart0,
bool clk_peri_uart1, bool clk_sys_uart1,
bool clk_sys_usbctrl, bool clk_usb_usbctrl,
bool clk_sys_watchdog, bool clk_sys_xip,
bool clk_sys_xosc) volatile
{
uint32_t curr = WAKE_EN1;
curr &= ~(0b1u << 0u);
curr |= (clk_sys_sram4 & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (clk_sys_sram5 & 0b1u) << 1u;
curr &= ~(0b1u << 2u);
curr |= (clk_sys_syscfg & 0b1u) << 2u;
curr &= ~(0b1u << 3u);
curr |= (clk_sys_sysinfo & 0b1u) << 3u;
curr &= ~(0b1u << 4u);
curr |= (clk_sys_tbman & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (clk_sys_timer & 0b1u) << 5u;
curr &= ~(0b1u << 6u);
curr |= (clk_peri_uart0 & 0b1u) << 6u;
curr &= ~(0b1u << 7u);
curr |= (clk_sys_uart0 & 0b1u) << 7u;
curr &= ~(0b1u << 8u);
curr |= (clk_peri_uart1 & 0b1u) << 8u;
curr &= ~(0b1u << 9u);
curr |= (clk_sys_uart1 & 0b1u) << 9u;
curr &= ~(0b1u << 10u);
curr |= (clk_sys_usbctrl & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (clk_usb_usbctrl & 0b1u) << 11u;
curr &= ~(0b1u << 12u);
curr |= (clk_sys_watchdog & 0b1u) << 12u;
curr &= ~(0b1u << 13u);
curr |= (clk_sys_xip & 0b1u) << 13u;
curr &= ~(0b1u << 14u);
curr |= (clk_sys_xosc & 0b1u) << 14u;
WAKE_EN1 = curr;
}
inline bool get_SLEEP_EN0_clk_sys_clocks() volatile
{
return SLEEP_EN0 & (1u << 0u);
}
inline void set_SLEEP_EN0_clk_sys_clocks() volatile
{
SLEEP_EN0 |= 1u << 0u;
}
inline void clear_SLEEP_EN0_clk_sys_clocks() volatile
{
SLEEP_EN0 &= ~(1u << 0u);
}
inline void toggle_SLEEP_EN0_clk_sys_clocks() volatile
{
SLEEP_EN0 ^= 1u << 0u;
}
inline bool get_SLEEP_EN0_clk_adc_adc() volatile
{
return SLEEP_EN0 & (1u << 1u);
}
inline void set_SLEEP_EN0_clk_adc_adc() volatile
{
SLEEP_EN0 |= 1u << 1u;
}
inline void clear_SLEEP_EN0_clk_adc_adc() volatile
{
SLEEP_EN0 &= ~(1u << 1u);
}
inline void toggle_SLEEP_EN0_clk_adc_adc() volatile
{
SLEEP_EN0 ^= 1u << 1u;
}
inline bool get_SLEEP_EN0_clk_sys_adc() volatile
{
return SLEEP_EN0 & (1u << 2u);
}
inline void set_SLEEP_EN0_clk_sys_adc() volatile
{
SLEEP_EN0 |= 1u << 2u;
}
inline void clear_SLEEP_EN0_clk_sys_adc() volatile
{
SLEEP_EN0 &= ~(1u << 2u);
}
inline void toggle_SLEEP_EN0_clk_sys_adc() volatile
{
SLEEP_EN0 ^= 1u << 2u;
}
inline bool get_SLEEP_EN0_clk_sys_busctrl() volatile
{
return SLEEP_EN0 & (1u << 3u);
}
inline void set_SLEEP_EN0_clk_sys_busctrl() volatile
{
SLEEP_EN0 |= 1u << 3u;
}
inline void clear_SLEEP_EN0_clk_sys_busctrl() volatile
{
SLEEP_EN0 &= ~(1u << 3u);
}
inline void toggle_SLEEP_EN0_clk_sys_busctrl() volatile
{
SLEEP_EN0 ^= 1u << 3u;
}
inline bool get_SLEEP_EN0_clk_sys_busfabric() volatile
{
return SLEEP_EN0 & (1u << 4u);
}
inline void set_SLEEP_EN0_clk_sys_busfabric() volatile
{
SLEEP_EN0 |= 1u << 4u;
}
inline void clear_SLEEP_EN0_clk_sys_busfabric() volatile
{
SLEEP_EN0 &= ~(1u << 4u);
}
inline void toggle_SLEEP_EN0_clk_sys_busfabric() volatile
{
SLEEP_EN0 ^= 1u << 4u;
}
inline bool get_SLEEP_EN0_clk_sys_dma() volatile
{
return SLEEP_EN0 & (1u << 5u);
}
inline void set_SLEEP_EN0_clk_sys_dma() volatile
{
SLEEP_EN0 |= 1u << 5u;
}
inline void clear_SLEEP_EN0_clk_sys_dma() volatile
{
SLEEP_EN0 &= ~(1u << 5u);
}
inline void toggle_SLEEP_EN0_clk_sys_dma() volatile
{
SLEEP_EN0 ^= 1u << 5u;
}
inline bool get_SLEEP_EN0_clk_sys_i2c0() volatile
{
return SLEEP_EN0 & (1u << 6u);
}
inline void set_SLEEP_EN0_clk_sys_i2c0() volatile
{
SLEEP_EN0 |= 1u << 6u;
}
inline void clear_SLEEP_EN0_clk_sys_i2c0() volatile
{
SLEEP_EN0 &= ~(1u << 6u);
}
inline void toggle_SLEEP_EN0_clk_sys_i2c0() volatile
{
SLEEP_EN0 ^= 1u << 6u;
}
inline bool get_SLEEP_EN0_clk_sys_i2c1() volatile
{
return SLEEP_EN0 & (1u << 7u);
}
inline void set_SLEEP_EN0_clk_sys_i2c1() volatile
{
SLEEP_EN0 |= 1u << 7u;
}
inline void clear_SLEEP_EN0_clk_sys_i2c1() volatile
{
SLEEP_EN0 &= ~(1u << 7u);
}
inline void toggle_SLEEP_EN0_clk_sys_i2c1() volatile
{
SLEEP_EN0 ^= 1u << 7u;
}
inline bool get_SLEEP_EN0_clk_sys_io() volatile
{
return SLEEP_EN0 & (1u << 8u);
}
inline void set_SLEEP_EN0_clk_sys_io() volatile
{
SLEEP_EN0 |= 1u << 8u;
}
inline void clear_SLEEP_EN0_clk_sys_io() volatile
{
SLEEP_EN0 &= ~(1u << 8u);
}
inline void toggle_SLEEP_EN0_clk_sys_io() volatile
{
SLEEP_EN0 ^= 1u << 8u;
}
inline bool get_SLEEP_EN0_clk_sys_jtag() volatile
{
return SLEEP_EN0 & (1u << 9u);
}
inline void set_SLEEP_EN0_clk_sys_jtag() volatile
{
SLEEP_EN0 |= 1u << 9u;
}
inline void clear_SLEEP_EN0_clk_sys_jtag() volatile
{
SLEEP_EN0 &= ~(1u << 9u);
}
inline void toggle_SLEEP_EN0_clk_sys_jtag() volatile
{
SLEEP_EN0 ^= 1u << 9u;
}
inline bool get_SLEEP_EN0_clk_sys_vreg_and_chip_reset() volatile
{
return SLEEP_EN0 & (1u << 10u);
}
inline void set_SLEEP_EN0_clk_sys_vreg_and_chip_reset() volatile
{
SLEEP_EN0 |= 1u << 10u;
}
inline void clear_SLEEP_EN0_clk_sys_vreg_and_chip_reset() volatile
{
SLEEP_EN0 &= ~(1u << 10u);
}
inline void toggle_SLEEP_EN0_clk_sys_vreg_and_chip_reset() volatile
{
SLEEP_EN0 ^= 1u << 10u;
}
inline bool get_SLEEP_EN0_clk_sys_pads() volatile
{
return SLEEP_EN0 & (1u << 11u);
}
inline void set_SLEEP_EN0_clk_sys_pads() volatile
{
SLEEP_EN0 |= 1u << 11u;
}
inline void clear_SLEEP_EN0_clk_sys_pads() volatile
{
SLEEP_EN0 &= ~(1u << 11u);
}
inline void toggle_SLEEP_EN0_clk_sys_pads() volatile
{
SLEEP_EN0 ^= 1u << 11u;
}
inline bool get_SLEEP_EN0_clk_sys_pio0() volatile
{
return SLEEP_EN0 & (1u << 12u);
}
inline void set_SLEEP_EN0_clk_sys_pio0() volatile
{
SLEEP_EN0 |= 1u << 12u;
}
inline void clear_SLEEP_EN0_clk_sys_pio0() volatile
{
SLEEP_EN0 &= ~(1u << 12u);
}
inline void toggle_SLEEP_EN0_clk_sys_pio0() volatile
{
SLEEP_EN0 ^= 1u << 12u;
}
inline bool get_SLEEP_EN0_clk_sys_pio1() volatile
{
return SLEEP_EN0 & (1u << 13u);
}
inline void set_SLEEP_EN0_clk_sys_pio1() volatile
{
SLEEP_EN0 |= 1u << 13u;
}
inline void clear_SLEEP_EN0_clk_sys_pio1() volatile
{
SLEEP_EN0 &= ~(1u << 13u);
}
inline void toggle_SLEEP_EN0_clk_sys_pio1() volatile
{
SLEEP_EN0 ^= 1u << 13u;
}
inline bool get_SLEEP_EN0_clk_sys_pll_sys() volatile
{
return SLEEP_EN0 & (1u << 14u);
}
inline void set_SLEEP_EN0_clk_sys_pll_sys() volatile
{
SLEEP_EN0 |= 1u << 14u;
}
inline void clear_SLEEP_EN0_clk_sys_pll_sys() volatile
{
SLEEP_EN0 &= ~(1u << 14u);
}
inline void toggle_SLEEP_EN0_clk_sys_pll_sys() volatile
{
SLEEP_EN0 ^= 1u << 14u;
}
inline bool get_SLEEP_EN0_clk_sys_pll_usb() volatile
{
return SLEEP_EN0 & (1u << 15u);
}
inline void set_SLEEP_EN0_clk_sys_pll_usb() volatile
{
SLEEP_EN0 |= 1u << 15u;
}
inline void clear_SLEEP_EN0_clk_sys_pll_usb() volatile
{
SLEEP_EN0 &= ~(1u << 15u);
}
inline void toggle_SLEEP_EN0_clk_sys_pll_usb() volatile
{
SLEEP_EN0 ^= 1u << 15u;
}
inline bool get_SLEEP_EN0_clk_sys_psm() volatile
{
return SLEEP_EN0 & (1u << 16u);
}
inline void set_SLEEP_EN0_clk_sys_psm() volatile
{
SLEEP_EN0 |= 1u << 16u;
}
inline void clear_SLEEP_EN0_clk_sys_psm() volatile
{
SLEEP_EN0 &= ~(1u << 16u);
}
inline void toggle_SLEEP_EN0_clk_sys_psm() volatile
{
SLEEP_EN0 ^= 1u << 16u;
}
inline bool get_SLEEP_EN0_clk_sys_pwm() volatile
{
return SLEEP_EN0 & (1u << 17u);
}
inline void set_SLEEP_EN0_clk_sys_pwm() volatile
{
SLEEP_EN0 |= 1u << 17u;
}
inline void clear_SLEEP_EN0_clk_sys_pwm() volatile
{
SLEEP_EN0 &= ~(1u << 17u);
}
inline void toggle_SLEEP_EN0_clk_sys_pwm() volatile
{
SLEEP_EN0 ^= 1u << 17u;
}
inline bool get_SLEEP_EN0_clk_sys_resets() volatile
{
return SLEEP_EN0 & (1u << 18u);
}
inline void set_SLEEP_EN0_clk_sys_resets() volatile
{
SLEEP_EN0 |= 1u << 18u;
}
inline void clear_SLEEP_EN0_clk_sys_resets() volatile
{
SLEEP_EN0 &= ~(1u << 18u);
}
inline void toggle_SLEEP_EN0_clk_sys_resets() volatile
{
SLEEP_EN0 ^= 1u << 18u;
}
inline bool get_SLEEP_EN0_clk_sys_rom() volatile
{
return SLEEP_EN0 & (1u << 19u);
}
inline void set_SLEEP_EN0_clk_sys_rom() volatile
{
SLEEP_EN0 |= 1u << 19u;
}
inline void clear_SLEEP_EN0_clk_sys_rom() volatile
{
SLEEP_EN0 &= ~(1u << 19u);
}
inline void toggle_SLEEP_EN0_clk_sys_rom() volatile
{
SLEEP_EN0 ^= 1u << 19u;
}
inline bool get_SLEEP_EN0_clk_sys_rosc() volatile
{
return SLEEP_EN0 & (1u << 20u);
}
inline void set_SLEEP_EN0_clk_sys_rosc() volatile
{
SLEEP_EN0 |= 1u << 20u;
}
inline void clear_SLEEP_EN0_clk_sys_rosc() volatile
{
SLEEP_EN0 &= ~(1u << 20u);
}
inline void toggle_SLEEP_EN0_clk_sys_rosc() volatile
{
SLEEP_EN0 ^= 1u << 20u;
}
inline bool get_SLEEP_EN0_clk_rtc_rtc() volatile
{
return SLEEP_EN0 & (1u << 21u);
}
inline void set_SLEEP_EN0_clk_rtc_rtc() volatile
{
SLEEP_EN0 |= 1u << 21u;
}
inline void clear_SLEEP_EN0_clk_rtc_rtc() volatile
{
SLEEP_EN0 &= ~(1u << 21u);
}
inline void toggle_SLEEP_EN0_clk_rtc_rtc() volatile
{
SLEEP_EN0 ^= 1u << 21u;
}
inline bool get_SLEEP_EN0_clk_sys_rtc() volatile
{
return SLEEP_EN0 & (1u << 22u);
}
inline void set_SLEEP_EN0_clk_sys_rtc() volatile
{
SLEEP_EN0 |= 1u << 22u;
}
inline void clear_SLEEP_EN0_clk_sys_rtc() volatile
{
SLEEP_EN0 &= ~(1u << 22u);
}
inline void toggle_SLEEP_EN0_clk_sys_rtc() volatile
{
SLEEP_EN0 ^= 1u << 22u;
}
inline bool get_SLEEP_EN0_clk_sys_sio() volatile
{
return SLEEP_EN0 & (1u << 23u);
}
inline void set_SLEEP_EN0_clk_sys_sio() volatile
{
SLEEP_EN0 |= 1u << 23u;
}
inline void clear_SLEEP_EN0_clk_sys_sio() volatile
{
SLEEP_EN0 &= ~(1u << 23u);
}
inline void toggle_SLEEP_EN0_clk_sys_sio() volatile
{
SLEEP_EN0 ^= 1u << 23u;
}
inline bool get_SLEEP_EN0_clk_peri_spi0() volatile
{
return SLEEP_EN0 & (1u << 24u);
}
inline void set_SLEEP_EN0_clk_peri_spi0() volatile
{
SLEEP_EN0 |= 1u << 24u;
}
inline void clear_SLEEP_EN0_clk_peri_spi0() volatile
{
SLEEP_EN0 &= ~(1u << 24u);
}
inline void toggle_SLEEP_EN0_clk_peri_spi0() volatile
{
SLEEP_EN0 ^= 1u << 24u;
}
inline bool get_SLEEP_EN0_clk_sys_spi0() volatile
{
return SLEEP_EN0 & (1u << 25u);
}
inline void set_SLEEP_EN0_clk_sys_spi0() volatile
{
SLEEP_EN0 |= 1u << 25u;
}
inline void clear_SLEEP_EN0_clk_sys_spi0() volatile
{
SLEEP_EN0 &= ~(1u << 25u);
}
inline void toggle_SLEEP_EN0_clk_sys_spi0() volatile
{
SLEEP_EN0 ^= 1u << 25u;
}
inline bool get_SLEEP_EN0_clk_peri_spi1() volatile
{
return SLEEP_EN0 & (1u << 26u);
}
inline void set_SLEEP_EN0_clk_peri_spi1() volatile
{
SLEEP_EN0 |= 1u << 26u;
}
inline void clear_SLEEP_EN0_clk_peri_spi1() volatile
{
SLEEP_EN0 &= ~(1u << 26u);
}
inline void toggle_SLEEP_EN0_clk_peri_spi1() volatile
{
SLEEP_EN0 ^= 1u << 26u;
}
inline bool get_SLEEP_EN0_clk_sys_spi1() volatile
{
return SLEEP_EN0 & (1u << 27u);
}
inline void set_SLEEP_EN0_clk_sys_spi1() volatile
{
SLEEP_EN0 |= 1u << 27u;
}
inline void clear_SLEEP_EN0_clk_sys_spi1() volatile
{
SLEEP_EN0 &= ~(1u << 27u);
}
inline void toggle_SLEEP_EN0_clk_sys_spi1() volatile
{
SLEEP_EN0 ^= 1u << 27u;
}
inline bool get_SLEEP_EN0_clk_sys_sram0() volatile
{
return SLEEP_EN0 & (1u << 28u);
}
inline void set_SLEEP_EN0_clk_sys_sram0() volatile
{
SLEEP_EN0 |= 1u << 28u;
}
inline void clear_SLEEP_EN0_clk_sys_sram0() volatile
{
SLEEP_EN0 &= ~(1u << 28u);
}
inline void toggle_SLEEP_EN0_clk_sys_sram0() volatile
{
SLEEP_EN0 ^= 1u << 28u;
}
inline bool get_SLEEP_EN0_clk_sys_sram1() volatile
{
return SLEEP_EN0 & (1u << 29u);
}
inline void set_SLEEP_EN0_clk_sys_sram1() volatile
{
SLEEP_EN0 |= 1u << 29u;
}
inline void clear_SLEEP_EN0_clk_sys_sram1() volatile
{
SLEEP_EN0 &= ~(1u << 29u);
}
inline void toggle_SLEEP_EN0_clk_sys_sram1() volatile
{
SLEEP_EN0 ^= 1u << 29u;
}
inline bool get_SLEEP_EN0_clk_sys_sram2() volatile
{
return SLEEP_EN0 & (1u << 30u);
}
inline void set_SLEEP_EN0_clk_sys_sram2() volatile
{
SLEEP_EN0 |= 1u << 30u;
}
inline void clear_SLEEP_EN0_clk_sys_sram2() volatile
{
SLEEP_EN0 &= ~(1u << 30u);
}
inline void toggle_SLEEP_EN0_clk_sys_sram2() volatile
{
SLEEP_EN0 ^= 1u << 30u;
}
inline bool get_SLEEP_EN0_clk_sys_sram3() volatile
{
return SLEEP_EN0 & (1u << 31u);
}
inline void set_SLEEP_EN0_clk_sys_sram3() volatile
{
SLEEP_EN0 |= 1u << 31u;
}
inline void clear_SLEEP_EN0_clk_sys_sram3() volatile
{
SLEEP_EN0 &= ~(1u << 31u);
}
inline void toggle_SLEEP_EN0_clk_sys_sram3() volatile
{
SLEEP_EN0 ^= 1u << 31u;
}
inline void get_SLEEP_EN0(
bool &clk_sys_clocks, bool &clk_adc_adc, bool &clk_sys_adc,
bool &clk_sys_busctrl, bool &clk_sys_busfabric, bool &clk_sys_dma,
bool &clk_sys_i2c0, bool &clk_sys_i2c1, bool &clk_sys_io,
bool &clk_sys_jtag, bool &clk_sys_vreg_and_chip_reset,
bool &clk_sys_pads, bool &clk_sys_pio0, bool &clk_sys_pio1,
bool &clk_sys_pll_sys, bool &clk_sys_pll_usb, bool &clk_sys_psm,
bool &clk_sys_pwm, bool &clk_sys_resets, bool &clk_sys_rom,
bool &clk_sys_rosc, bool &clk_rtc_rtc, bool &clk_sys_rtc,
bool &clk_sys_sio, bool &clk_peri_spi0, bool &clk_sys_spi0,
bool &clk_peri_spi1, bool &clk_sys_spi1, bool &clk_sys_sram0,
bool &clk_sys_sram1, bool &clk_sys_sram2, bool &clk_sys_sram3) volatile
{
uint32_t curr = SLEEP_EN0;
clk_sys_clocks = curr & (1u << 0u);
clk_adc_adc = curr & (1u << 1u);
clk_sys_adc = curr & (1u << 2u);
clk_sys_busctrl = curr & (1u << 3u);
clk_sys_busfabric = curr & (1u << 4u);
clk_sys_dma = curr & (1u << 5u);
clk_sys_i2c0 = curr & (1u << 6u);
clk_sys_i2c1 = curr & (1u << 7u);
clk_sys_io = curr & (1u << 8u);
clk_sys_jtag = curr & (1u << 9u);
clk_sys_vreg_and_chip_reset = curr & (1u << 10u);
clk_sys_pads = curr & (1u << 11u);
clk_sys_pio0 = curr & (1u << 12u);
clk_sys_pio1 = curr & (1u << 13u);
clk_sys_pll_sys = curr & (1u << 14u);
clk_sys_pll_usb = curr & (1u << 15u);
clk_sys_psm = curr & (1u << 16u);
clk_sys_pwm = curr & (1u << 17u);
clk_sys_resets = curr & (1u << 18u);
clk_sys_rom = curr & (1u << 19u);
clk_sys_rosc = curr & (1u << 20u);
clk_rtc_rtc = curr & (1u << 21u);
clk_sys_rtc = curr & (1u << 22u);
clk_sys_sio = curr & (1u << 23u);
clk_peri_spi0 = curr & (1u << 24u);
clk_sys_spi0 = curr & (1u << 25u);
clk_peri_spi1 = curr & (1u << 26u);
clk_sys_spi1 = curr & (1u << 27u);
clk_sys_sram0 = curr & (1u << 28u);
clk_sys_sram1 = curr & (1u << 29u);
clk_sys_sram2 = curr & (1u << 30u);
clk_sys_sram3 = curr & (1u << 31u);
}
inline void set_SLEEP_EN0(
bool clk_sys_clocks, bool clk_adc_adc, bool clk_sys_adc,
bool clk_sys_busctrl, bool clk_sys_busfabric, bool clk_sys_dma,
bool clk_sys_i2c0, bool clk_sys_i2c1, bool clk_sys_io,
bool clk_sys_jtag, bool clk_sys_vreg_and_chip_reset, bool clk_sys_pads,
bool clk_sys_pio0, bool clk_sys_pio1, bool clk_sys_pll_sys,
bool clk_sys_pll_usb, bool clk_sys_psm, bool clk_sys_pwm,
bool clk_sys_resets, bool clk_sys_rom, bool clk_sys_rosc,
bool clk_rtc_rtc, bool clk_sys_rtc, bool clk_sys_sio,
bool clk_peri_spi0, bool clk_sys_spi0, bool clk_peri_spi1,
bool clk_sys_spi1, bool clk_sys_sram0, bool clk_sys_sram1,
bool clk_sys_sram2, bool clk_sys_sram3) volatile
{
uint32_t curr = SLEEP_EN0;
curr &= ~(0b1u << 0u);
curr |= (clk_sys_clocks & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (clk_adc_adc & 0b1u) << 1u;
curr &= ~(0b1u << 2u);
curr |= (clk_sys_adc & 0b1u) << 2u;
curr &= ~(0b1u << 3u);
curr |= (clk_sys_busctrl & 0b1u) << 3u;
curr &= ~(0b1u << 4u);
curr |= (clk_sys_busfabric & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (clk_sys_dma & 0b1u) << 5u;
curr &= ~(0b1u << 6u);
curr |= (clk_sys_i2c0 & 0b1u) << 6u;
curr &= ~(0b1u << 7u);
curr |= (clk_sys_i2c1 & 0b1u) << 7u;
curr &= ~(0b1u << 8u);
curr |= (clk_sys_io & 0b1u) << 8u;
curr &= ~(0b1u << 9u);
curr |= (clk_sys_jtag & 0b1u) << 9u;
curr &= ~(0b1u << 10u);
curr |= (clk_sys_vreg_and_chip_reset & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (clk_sys_pads & 0b1u) << 11u;
curr &= ~(0b1u << 12u);
curr |= (clk_sys_pio0 & 0b1u) << 12u;
curr &= ~(0b1u << 13u);
curr |= (clk_sys_pio1 & 0b1u) << 13u;
curr &= ~(0b1u << 14u);
curr |= (clk_sys_pll_sys & 0b1u) << 14u;
curr &= ~(0b1u << 15u);
curr |= (clk_sys_pll_usb & 0b1u) << 15u;
curr &= ~(0b1u << 16u);
curr |= (clk_sys_psm & 0b1u) << 16u;
curr &= ~(0b1u << 17u);
curr |= (clk_sys_pwm & 0b1u) << 17u;
curr &= ~(0b1u << 18u);
curr |= (clk_sys_resets & 0b1u) << 18u;
curr &= ~(0b1u << 19u);
curr |= (clk_sys_rom & 0b1u) << 19u;
curr &= ~(0b1u << 20u);
curr |= (clk_sys_rosc & 0b1u) << 20u;
curr &= ~(0b1u << 21u);
curr |= (clk_rtc_rtc & 0b1u) << 21u;
curr &= ~(0b1u << 22u);
curr |= (clk_sys_rtc & 0b1u) << 22u;
curr &= ~(0b1u << 23u);
curr |= (clk_sys_sio & 0b1u) << 23u;
curr &= ~(0b1u << 24u);
curr |= (clk_peri_spi0 & 0b1u) << 24u;
curr &= ~(0b1u << 25u);
curr |= (clk_sys_spi0 & 0b1u) << 25u;
curr &= ~(0b1u << 26u);
curr |= (clk_peri_spi1 & 0b1u) << 26u;
curr &= ~(0b1u << 27u);
curr |= (clk_sys_spi1 & 0b1u) << 27u;
curr &= ~(0b1u << 28u);
curr |= (clk_sys_sram0 & 0b1u) << 28u;
curr &= ~(0b1u << 29u);
curr |= (clk_sys_sram1 & 0b1u) << 29u;
curr &= ~(0b1u << 30u);
curr |= (clk_sys_sram2 & 0b1u) << 30u;
curr &= ~(0b1u << 31u);
curr |= (clk_sys_sram3 & 0b1u) << 31u;
SLEEP_EN0 = curr;
}
inline bool get_SLEEP_EN1_clk_sys_sram4() volatile
{
return SLEEP_EN1 & (1u << 0u);
}
inline void set_SLEEP_EN1_clk_sys_sram4() volatile
{
SLEEP_EN1 |= 1u << 0u;
}
inline void clear_SLEEP_EN1_clk_sys_sram4() volatile
{
SLEEP_EN1 &= ~(1u << 0u);
}
inline void toggle_SLEEP_EN1_clk_sys_sram4() volatile
{
SLEEP_EN1 ^= 1u << 0u;
}
inline bool get_SLEEP_EN1_clk_sys_sram5() volatile
{
return SLEEP_EN1 & (1u << 1u);
}
inline void set_SLEEP_EN1_clk_sys_sram5() volatile
{
SLEEP_EN1 |= 1u << 1u;
}
inline void clear_SLEEP_EN1_clk_sys_sram5() volatile
{
SLEEP_EN1 &= ~(1u << 1u);
}
inline void toggle_SLEEP_EN1_clk_sys_sram5() volatile
{
SLEEP_EN1 ^= 1u << 1u;
}
inline bool get_SLEEP_EN1_clk_sys_syscfg() volatile
{
return SLEEP_EN1 & (1u << 2u);
}
inline void set_SLEEP_EN1_clk_sys_syscfg() volatile
{
SLEEP_EN1 |= 1u << 2u;
}
inline void clear_SLEEP_EN1_clk_sys_syscfg() volatile
{
SLEEP_EN1 &= ~(1u << 2u);
}
inline void toggle_SLEEP_EN1_clk_sys_syscfg() volatile
{
SLEEP_EN1 ^= 1u << 2u;
}
inline bool get_SLEEP_EN1_clk_sys_sysinfo() volatile
{
return SLEEP_EN1 & (1u << 3u);
}
inline void set_SLEEP_EN1_clk_sys_sysinfo() volatile
{
SLEEP_EN1 |= 1u << 3u;
}
inline void clear_SLEEP_EN1_clk_sys_sysinfo() volatile
{
SLEEP_EN1 &= ~(1u << 3u);
}
inline void toggle_SLEEP_EN1_clk_sys_sysinfo() volatile
{
SLEEP_EN1 ^= 1u << 3u;
}
inline bool get_SLEEP_EN1_clk_sys_tbman() volatile
{
return SLEEP_EN1 & (1u << 4u);
}
inline void set_SLEEP_EN1_clk_sys_tbman() volatile
{
SLEEP_EN1 |= 1u << 4u;
}
inline void clear_SLEEP_EN1_clk_sys_tbman() volatile
{
SLEEP_EN1 &= ~(1u << 4u);
}
inline void toggle_SLEEP_EN1_clk_sys_tbman() volatile
{
SLEEP_EN1 ^= 1u << 4u;
}
inline bool get_SLEEP_EN1_clk_sys_timer() volatile
{
return SLEEP_EN1 & (1u << 5u);
}
inline void set_SLEEP_EN1_clk_sys_timer() volatile
{
SLEEP_EN1 |= 1u << 5u;
}
inline void clear_SLEEP_EN1_clk_sys_timer() volatile
{
SLEEP_EN1 &= ~(1u << 5u);
}
inline void toggle_SLEEP_EN1_clk_sys_timer() volatile
{
SLEEP_EN1 ^= 1u << 5u;
}
inline bool get_SLEEP_EN1_clk_peri_uart0() volatile
{
return SLEEP_EN1 & (1u << 6u);
}
inline void set_SLEEP_EN1_clk_peri_uart0() volatile
{
SLEEP_EN1 |= 1u << 6u;
}
inline void clear_SLEEP_EN1_clk_peri_uart0() volatile
{
SLEEP_EN1 &= ~(1u << 6u);
}
inline void toggle_SLEEP_EN1_clk_peri_uart0() volatile
{
SLEEP_EN1 ^= 1u << 6u;
}
inline bool get_SLEEP_EN1_clk_sys_uart0() volatile
{
return SLEEP_EN1 & (1u << 7u);
}
inline void set_SLEEP_EN1_clk_sys_uart0() volatile
{
SLEEP_EN1 |= 1u << 7u;
}
inline void clear_SLEEP_EN1_clk_sys_uart0() volatile
{
SLEEP_EN1 &= ~(1u << 7u);
}
inline void toggle_SLEEP_EN1_clk_sys_uart0() volatile
{
SLEEP_EN1 ^= 1u << 7u;
}
inline bool get_SLEEP_EN1_clk_peri_uart1() volatile
{
return SLEEP_EN1 & (1u << 8u);
}
inline void set_SLEEP_EN1_clk_peri_uart1() volatile
{
SLEEP_EN1 |= 1u << 8u;
}
inline void clear_SLEEP_EN1_clk_peri_uart1() volatile
{
SLEEP_EN1 &= ~(1u << 8u);
}
inline void toggle_SLEEP_EN1_clk_peri_uart1() volatile
{
SLEEP_EN1 ^= 1u << 8u;
}
inline bool get_SLEEP_EN1_clk_sys_uart1() volatile
{
return SLEEP_EN1 & (1u << 9u);
}
inline void set_SLEEP_EN1_clk_sys_uart1() volatile
{
SLEEP_EN1 |= 1u << 9u;
}
inline void clear_SLEEP_EN1_clk_sys_uart1() volatile
{
SLEEP_EN1 &= ~(1u << 9u);
}
inline void toggle_SLEEP_EN1_clk_sys_uart1() volatile
{
SLEEP_EN1 ^= 1u << 9u;
}
inline bool get_SLEEP_EN1_clk_sys_usbctrl() volatile
{
return SLEEP_EN1 & (1u << 10u);
}
inline void set_SLEEP_EN1_clk_sys_usbctrl() volatile
{
SLEEP_EN1 |= 1u << 10u;
}
inline void clear_SLEEP_EN1_clk_sys_usbctrl() volatile
{
SLEEP_EN1 &= ~(1u << 10u);
}
inline void toggle_SLEEP_EN1_clk_sys_usbctrl() volatile
{
SLEEP_EN1 ^= 1u << 10u;
}
inline bool get_SLEEP_EN1_clk_usb_usbctrl() volatile
{
return SLEEP_EN1 & (1u << 11u);
}
inline void set_SLEEP_EN1_clk_usb_usbctrl() volatile
{
SLEEP_EN1 |= 1u << 11u;
}
inline void clear_SLEEP_EN1_clk_usb_usbctrl() volatile
{
SLEEP_EN1 &= ~(1u << 11u);
}
inline void toggle_SLEEP_EN1_clk_usb_usbctrl() volatile
{
SLEEP_EN1 ^= 1u << 11u;
}
inline bool get_SLEEP_EN1_clk_sys_watchdog() volatile
{
return SLEEP_EN1 & (1u << 12u);
}
inline void set_SLEEP_EN1_clk_sys_watchdog() volatile
{
SLEEP_EN1 |= 1u << 12u;
}
inline void clear_SLEEP_EN1_clk_sys_watchdog() volatile
{
SLEEP_EN1 &= ~(1u << 12u);
}
inline void toggle_SLEEP_EN1_clk_sys_watchdog() volatile
{
SLEEP_EN1 ^= 1u << 12u;
}
inline bool get_SLEEP_EN1_clk_sys_xip() volatile
{
return SLEEP_EN1 & (1u << 13u);
}
inline void set_SLEEP_EN1_clk_sys_xip() volatile
{
SLEEP_EN1 |= 1u << 13u;
}
inline void clear_SLEEP_EN1_clk_sys_xip() volatile
{
SLEEP_EN1 &= ~(1u << 13u);
}
inline void toggle_SLEEP_EN1_clk_sys_xip() volatile
{
SLEEP_EN1 ^= 1u << 13u;
}
inline bool get_SLEEP_EN1_clk_sys_xosc() volatile
{
return SLEEP_EN1 & (1u << 14u);
}
inline void set_SLEEP_EN1_clk_sys_xosc() volatile
{
SLEEP_EN1 |= 1u << 14u;
}
inline void clear_SLEEP_EN1_clk_sys_xosc() volatile
{
SLEEP_EN1 &= ~(1u << 14u);
}
inline void toggle_SLEEP_EN1_clk_sys_xosc() volatile
{
SLEEP_EN1 ^= 1u << 14u;
}
inline void get_SLEEP_EN1(bool &clk_sys_sram4, bool &clk_sys_sram5,
bool &clk_sys_syscfg, bool &clk_sys_sysinfo,
bool &clk_sys_tbman, bool &clk_sys_timer,
bool &clk_peri_uart0, bool &clk_sys_uart0,
bool &clk_peri_uart1, bool &clk_sys_uart1,
bool &clk_sys_usbctrl, bool &clk_usb_usbctrl,
bool &clk_sys_watchdog, bool &clk_sys_xip,
bool &clk_sys_xosc) volatile
{
uint32_t curr = SLEEP_EN1;
clk_sys_sram4 = curr & (1u << 0u);
clk_sys_sram5 = curr & (1u << 1u);
clk_sys_syscfg = curr & (1u << 2u);
clk_sys_sysinfo = curr & (1u << 3u);
clk_sys_tbman = curr & (1u << 4u);
clk_sys_timer = curr & (1u << 5u);
clk_peri_uart0 = curr & (1u << 6u);
clk_sys_uart0 = curr & (1u << 7u);
clk_peri_uart1 = curr & (1u << 8u);
clk_sys_uart1 = curr & (1u << 9u);
clk_sys_usbctrl = curr & (1u << 10u);
clk_usb_usbctrl = curr & (1u << 11u);
clk_sys_watchdog = curr & (1u << 12u);
clk_sys_xip = curr & (1u << 13u);
clk_sys_xosc = curr & (1u << 14u);
}
inline void set_SLEEP_EN1(bool clk_sys_sram4, bool clk_sys_sram5,
bool clk_sys_syscfg, bool clk_sys_sysinfo,
bool clk_sys_tbman, bool clk_sys_timer,
bool clk_peri_uart0, bool clk_sys_uart0,
bool clk_peri_uart1, bool clk_sys_uart1,
bool clk_sys_usbctrl, bool clk_usb_usbctrl,
bool clk_sys_watchdog, bool clk_sys_xip,
bool clk_sys_xosc) volatile
{
uint32_t curr = SLEEP_EN1;
curr &= ~(0b1u << 0u);
curr |= (clk_sys_sram4 & 0b1u) << 0u;
curr &= ~(0b1u << 1u);
curr |= (clk_sys_sram5 & 0b1u) << 1u;
curr &= ~(0b1u << 2u);
curr |= (clk_sys_syscfg & 0b1u) << 2u;
curr &= ~(0b1u << 3u);
curr |= (clk_sys_sysinfo & 0b1u) << 3u;
curr &= ~(0b1u << 4u);
curr |= (clk_sys_tbman & 0b1u) << 4u;
curr &= ~(0b1u << 5u);
curr |= (clk_sys_timer & 0b1u) << 5u;
curr &= ~(0b1u << 6u);
curr |= (clk_peri_uart0 & 0b1u) << 6u;
curr &= ~(0b1u << 7u);
curr |= (clk_sys_uart0 & 0b1u) << 7u;
curr &= ~(0b1u << 8u);
curr |= (clk_peri_uart1 & 0b1u) << 8u;
curr &= ~(0b1u << 9u);
curr |= (clk_sys_uart1 & 0b1u) << 9u;
curr &= ~(0b1u << 10u);
curr |= (clk_sys_usbctrl & 0b1u) << 10u;
curr &= ~(0b1u << 11u);
curr |= (clk_usb_usbctrl & 0b1u) << 11u;
curr &= ~(0b1u << 12u);
curr |= (clk_sys_watchdog & 0b1u) << 12u;
curr &= ~(0b1u << 13u);
curr |= (clk_sys_xip & 0b1u) << 13u;
curr &= ~(0b1u << 14u);
curr |= (clk_sys_xosc & 0b1u) << 14u;
SLEEP_EN1 = curr;
}
inline bool get_ENABLED0_clk_sys_clocks() volatile
{
return ENABLED0 & (1u << 0u);
}
inline bool get_ENABLED0_clk_adc_adc() volatile
{
return ENABLED0 & (1u << 1u);
}
inline bool get_ENABLED0_clk_sys_adc() volatile
{
return ENABLED0 & (1u << 2u);
}
inline bool get_ENABLED0_clk_sys_busctrl() volatile
{
return ENABLED0 & (1u << 3u);
}
inline bool get_ENABLED0_clk_sys_busfabric() volatile
{
return ENABLED0 & (1u << 4u);
}
inline bool get_ENABLED0_clk_sys_dma() volatile
{
return ENABLED0 & (1u << 5u);
}
inline bool get_ENABLED0_clk_sys_i2c0() volatile
{
return ENABLED0 & (1u << 6u);
}
inline bool get_ENABLED0_clk_sys_i2c1() volatile
{
return ENABLED0 & (1u << 7u);
}
inline bool get_ENABLED0_clk_sys_io() volatile
{
return ENABLED0 & (1u << 8u);
}
inline bool get_ENABLED0_clk_sys_jtag() volatile
{
return ENABLED0 & (1u << 9u);
}
inline bool get_ENABLED0_clk_sys_vreg_and_chip_reset() volatile
{
return ENABLED0 & (1u << 10u);
}
inline bool get_ENABLED0_clk_sys_pads() volatile
{
return ENABLED0 & (1u << 11u);
}
inline bool get_ENABLED0_clk_sys_pio0() volatile
{
return ENABLED0 & (1u << 12u);
}
inline bool get_ENABLED0_clk_sys_pio1() volatile
{
return ENABLED0 & (1u << 13u);
}
inline bool get_ENABLED0_clk_sys_pll_sys() volatile
{
return ENABLED0 & (1u << 14u);
}
inline bool get_ENABLED0_clk_sys_pll_usb() volatile
{
return ENABLED0 & (1u << 15u);
}
inline bool get_ENABLED0_clk_sys_psm() volatile
{
return ENABLED0 & (1u << 16u);
}
inline bool get_ENABLED0_clk_sys_pwm() volatile
{
return ENABLED0 & (1u << 17u);
}
inline bool get_ENABLED0_clk_sys_resets() volatile
{
return ENABLED0 & (1u << 18u);
}
inline bool get_ENABLED0_clk_sys_rom() volatile
{
return ENABLED0 & (1u << 19u);
}
inline bool get_ENABLED0_clk_sys_rosc() volatile
{
return ENABLED0 & (1u << 20u);
}
inline bool get_ENABLED0_clk_rtc_rtc() volatile
{
return ENABLED0 & (1u << 21u);
}
inline bool get_ENABLED0_clk_sys_rtc() volatile
{
return ENABLED0 & (1u << 22u);
}
inline bool get_ENABLED0_clk_sys_sio() volatile
{
return ENABLED0 & (1u << 23u);
}
inline bool get_ENABLED0_clk_peri_spi0() volatile
{
return ENABLED0 & (1u << 24u);
}
inline bool get_ENABLED0_clk_sys_spi0() volatile
{
return ENABLED0 & (1u << 25u);
}
inline bool get_ENABLED0_clk_peri_spi1() volatile
{
return ENABLED0 & (1u << 26u);
}
inline bool get_ENABLED0_clk_sys_spi1() volatile
{
return ENABLED0 & (1u << 27u);
}
inline bool get_ENABLED0_clk_sys_sram0() volatile
{
return ENABLED0 & (1u << 28u);
}
inline bool get_ENABLED0_clk_sys_sram1() volatile
{
return ENABLED0 & (1u << 29u);
}
inline bool get_ENABLED0_clk_sys_sram2() volatile
{
return ENABLED0 & (1u << 30u);
}
inline bool get_ENABLED0_clk_sys_sram3() volatile
{
return ENABLED0 & (1u << 31u);
}
inline void get_ENABLED0(
bool &clk_sys_clocks, bool &clk_adc_adc, bool &clk_sys_adc,
bool &clk_sys_busctrl, bool &clk_sys_busfabric, bool &clk_sys_dma,
bool &clk_sys_i2c0, bool &clk_sys_i2c1, bool &clk_sys_io,
bool &clk_sys_jtag, bool &clk_sys_vreg_and_chip_reset,
bool &clk_sys_pads, bool &clk_sys_pio0, bool &clk_sys_pio1,
bool &clk_sys_pll_sys, bool &clk_sys_pll_usb, bool &clk_sys_psm,
bool &clk_sys_pwm, bool &clk_sys_resets, bool &clk_sys_rom,
bool &clk_sys_rosc, bool &clk_rtc_rtc, bool &clk_sys_rtc,
bool &clk_sys_sio, bool &clk_peri_spi0, bool &clk_sys_spi0,
bool &clk_peri_spi1, bool &clk_sys_spi1, bool &clk_sys_sram0,
bool &clk_sys_sram1, bool &clk_sys_sram2, bool &clk_sys_sram3) volatile
{
uint32_t curr = ENABLED0;
clk_sys_clocks = curr & (1u << 0u);
clk_adc_adc = curr & (1u << 1u);
clk_sys_adc = curr & (1u << 2u);
clk_sys_busctrl = curr & (1u << 3u);
clk_sys_busfabric = curr & (1u << 4u);
clk_sys_dma = curr & (1u << 5u);
clk_sys_i2c0 = curr & (1u << 6u);
clk_sys_i2c1 = curr & (1u << 7u);
clk_sys_io = curr & (1u << 8u);
clk_sys_jtag = curr & (1u << 9u);
clk_sys_vreg_and_chip_reset = curr & (1u << 10u);
clk_sys_pads = curr & (1u << 11u);
clk_sys_pio0 = curr & (1u << 12u);
clk_sys_pio1 = curr & (1u << 13u);
clk_sys_pll_sys = curr & (1u << 14u);
clk_sys_pll_usb = curr & (1u << 15u);
clk_sys_psm = curr & (1u << 16u);
clk_sys_pwm = curr & (1u << 17u);
clk_sys_resets = curr & (1u << 18u);
clk_sys_rom = curr & (1u << 19u);
clk_sys_rosc = curr & (1u << 20u);
clk_rtc_rtc = curr & (1u << 21u);
clk_sys_rtc = curr & (1u << 22u);
clk_sys_sio = curr & (1u << 23u);
clk_peri_spi0 = curr & (1u << 24u);
clk_sys_spi0 = curr & (1u << 25u);
clk_peri_spi1 = curr & (1u << 26u);
clk_sys_spi1 = curr & (1u << 27u);
clk_sys_sram0 = curr & (1u << 28u);
clk_sys_sram1 = curr & (1u << 29u);
clk_sys_sram2 = curr & (1u << 30u);
clk_sys_sram3 = curr & (1u << 31u);
}
inline bool get_ENABLED1_clk_sys_sram4() volatile
{
return ENABLED1 & (1u << 0u);
}
inline bool get_ENABLED1_clk_sys_sram5() volatile
{
return ENABLED1 & (1u << 1u);
}
inline bool get_ENABLED1_clk_sys_syscfg() volatile
{
return ENABLED1 & (1u << 2u);
}
inline bool get_ENABLED1_clk_sys_sysinfo() volatile
{
return ENABLED1 & (1u << 3u);
}
inline bool get_ENABLED1_clk_sys_tbman() volatile
{
return ENABLED1 & (1u << 4u);
}
inline bool get_ENABLED1_clk_sys_timer() volatile
{
return ENABLED1 & (1u << 5u);
}
inline bool get_ENABLED1_clk_peri_uart0() volatile
{
return ENABLED1 & (1u << 6u);
}
inline bool get_ENABLED1_clk_sys_uart0() volatile
{
return ENABLED1 & (1u << 7u);
}
inline bool get_ENABLED1_clk_peri_uart1() volatile
{
return ENABLED1 & (1u << 8u);
}
inline bool get_ENABLED1_clk_sys_uart1() volatile
{
return ENABLED1 & (1u << 9u);
}
inline bool get_ENABLED1_clk_sys_usbctrl() volatile
{
return ENABLED1 & (1u << 10u);
}
inline bool get_ENABLED1_clk_usb_usbctrl() volatile
{
return ENABLED1 & (1u << 11u);
}
inline bool get_ENABLED1_clk_sys_watchdog() volatile
{
return ENABLED1 & (1u << 12u);
}
inline bool get_ENABLED1_clk_sys_xip() volatile
{
return ENABLED1 & (1u << 13u);
}
inline bool get_ENABLED1_clk_sys_xosc() volatile
{
return ENABLED1 & (1u << 14u);
}
inline void get_ENABLED1(bool &clk_sys_sram4, bool &clk_sys_sram5,
bool &clk_sys_syscfg, bool &clk_sys_sysinfo,
bool &clk_sys_tbman, bool &clk_sys_timer,
bool &clk_peri_uart0, bool &clk_sys_uart0,
bool &clk_peri_uart1, bool &clk_sys_uart1,
bool &clk_sys_usbctrl, bool &clk_usb_usbctrl,
bool &clk_sys_watchdog, bool &clk_sys_xip,
bool &clk_sys_xosc) volatile
{
uint32_t curr = ENABLED1;
clk_sys_sram4 = curr & (1u << 0u);
clk_sys_sram5 = curr & (1u << 1u);
clk_sys_syscfg = curr & (1u << 2u);
clk_sys_sysinfo = curr & (1u << 3u);
clk_sys_tbman = curr & (1u << 4u);
clk_sys_timer = curr & (1u << 5u);
clk_peri_uart0 = curr & (1u << 6u);
clk_sys_uart0 = curr & (1u << 7u);
clk_peri_uart1 = curr & (1u << 8u);
clk_sys_uart1 = curr & (1u << 9u);
clk_sys_usbctrl = curr & (1u << 10u);
clk_usb_usbctrl = curr & (1u << 11u);
clk_sys_watchdog = curr & (1u << 12u);
clk_sys_xip = curr & (1u << 13u);
clk_sys_xosc = curr & (1u << 14u);
}
inline bool get_INTR_CLK_SYS_RESUS() volatile
{
return INTR & (1u << 0u);
}
inline bool get_INTE_CLK_SYS_RESUS() volatile
{
return INTE & (1u << 0u);
}
inline void set_INTE_CLK_SYS_RESUS() volatile
{
INTE |= 1u << 0u;
}
inline void clear_INTE_CLK_SYS_RESUS() volatile
{
INTE &= ~(1u << 0u);
}
inline void toggle_INTE_CLK_SYS_RESUS() volatile
{
INTE ^= 1u << 0u;
}
inline bool get_INTF_CLK_SYS_RESUS() volatile
{
return INTF & (1u << 0u);
}
inline void set_INTF_CLK_SYS_RESUS() volatile
{
INTF |= 1u << 0u;
}
inline void clear_INTF_CLK_SYS_RESUS() volatile
{
INTF &= ~(1u << 0u);
}
inline void toggle_INTF_CLK_SYS_RESUS() volatile
{
INTF ^= 1u << 0u;
}
inline bool get_INTS_CLK_SYS_RESUS() volatile
{
return INTS & (1u << 0u);
}
};
static_assert(sizeof(clocks) == clocks::size);
static volatile clocks *const CLOCKS = reinterpret_cast<clocks *>(0x40008000);
}; // namespace RP2040