Program Listing for File dma_control.h

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#pragma once
#ifndef RP2040_STRUCTS_DMA_CONTROL_H
#define RP2040_STRUCTS_DMA_CONTROL_H

#include "../enums/DMA_DATA_SIZE.h"
#include "../enums/DMA_RING_SIZE.h"
#include "../enums/DMA_TREQ_SEL.h"
#include "../ifgen/common.h"

namespace RP2040
{

struct dma_control
{
    /* Constant attributes. */
    static constexpr struct_id_t id = 5;
    static constexpr std::size_t size =
        64;
    /* Fields. */
    uint32_t READ_ADDR;
    uint32_t WRITE_ADDR;
    uint32_t
        TRANS_COUNT;
    uint32_t CTRL_TRIG;
    uint32_t AL1_CTRL;
    uint32_t AL1_READ_ADDR;
    uint32_t AL1_WRITE_ADDR;
    uint32_t
        AL1_TRANS_COUNT_TRIG;
    uint32_t AL2_CTRL;
    uint32_t AL2_TRANS_COUNT;
    uint32_t AL2_READ_ADDR;
    uint32_t
        AL2_WRITE_ADDR_TRIG;
    uint32_t AL3_CTRL;
    uint32_t AL3_WRITE_ADDR;
    uint32_t AL3_TRANS_COUNT;
    uint32_t AL3_READ_ADDR_TRIG;
    /* Methods. */

    inline bool get_CTRL_TRIG_EN()
    {
        return CTRL_TRIG & 1u;
    }

    inline void set_CTRL_TRIG_EN()
    {
        CTRL_TRIG |= 1u;
    }

    inline void clear_CTRL_TRIG_EN()
    {
        CTRL_TRIG &= ~(1u);
    }

    inline void toggle_CTRL_TRIG_EN()
    {
        CTRL_TRIG ^= 1u;
    }

    inline bool get_CTRL_TRIG_HIGH_PRIORITY()
    {
        return CTRL_TRIG & (1u << 1u);
    }

    inline void set_CTRL_TRIG_HIGH_PRIORITY()
    {
        CTRL_TRIG |= 1u << 1u;
    }

    inline void clear_CTRL_TRIG_HIGH_PRIORITY()
    {
        CTRL_TRIG &= ~(1u << 1u);
    }

    inline void toggle_CTRL_TRIG_HIGH_PRIORITY()
    {
        CTRL_TRIG ^= 1u << 1u;
    }

    inline DMA_DATA_SIZE get_CTRL_TRIG_DATA_SIZE()
    {
        return DMA_DATA_SIZE((CTRL_TRIG >> 2u) & 0b11u);
    }

    inline void set_CTRL_TRIG_DATA_SIZE(DMA_DATA_SIZE value)
    {
        uint32_t curr = CTRL_TRIG;

        curr &= ~(0b11u << 2u);
        curr |= (std::to_underlying(value) & 0b11u) << 2u;

        CTRL_TRIG = curr;
    }

    inline bool get_CTRL_TRIG_INCR_READ()
    {
        return CTRL_TRIG & (1u << 4u);
    }

    inline void set_CTRL_TRIG_INCR_READ()
    {
        CTRL_TRIG |= 1u << 4u;
    }

    inline void clear_CTRL_TRIG_INCR_READ()
    {
        CTRL_TRIG &= ~(1u << 4u);
    }

    inline void toggle_CTRL_TRIG_INCR_READ()
    {
        CTRL_TRIG ^= 1u << 4u;
    }

    inline bool get_CTRL_TRIG_INCR_WRITE()
    {
        return CTRL_TRIG & (1u << 5u);
    }

    inline void set_CTRL_TRIG_INCR_WRITE()
    {
        CTRL_TRIG |= 1u << 5u;
    }

    inline void clear_CTRL_TRIG_INCR_WRITE()
    {
        CTRL_TRIG &= ~(1u << 5u);
    }

    inline void toggle_CTRL_TRIG_INCR_WRITE()
    {
        CTRL_TRIG ^= 1u << 5u;
    }

    inline DMA_RING_SIZE get_CTRL_TRIG_RING_SIZE()
    {
        return DMA_RING_SIZE((CTRL_TRIG >> 6u) & 0xfu);
    }

    inline void set_CTRL_TRIG_RING_SIZE(DMA_RING_SIZE value)
    {
        uint32_t curr = CTRL_TRIG;

        curr &= ~(0xfu << 6u);
        curr |= (std::to_underlying(value) & 0xfu) << 6u;

        CTRL_TRIG = curr;
    }

    inline bool get_CTRL_TRIG_RING_SEL()
    {
        return CTRL_TRIG & (1u << 10u);
    }

    inline void set_CTRL_TRIG_RING_SEL()
    {
        CTRL_TRIG |= 1u << 10u;
    }

    inline void clear_CTRL_TRIG_RING_SEL()
    {
        CTRL_TRIG &= ~(1u << 10u);
    }

    inline void toggle_CTRL_TRIG_RING_SEL()
    {
        CTRL_TRIG ^= 1u << 10u;
    }

    inline uint8_t get_CTRL_TRIG_CHAIN_TO()
    {
        return (CTRL_TRIG >> 11u) & 0xfu;
    }

    inline void set_CTRL_TRIG_CHAIN_TO(uint8_t value)
    {
        uint32_t curr = CTRL_TRIG;

        curr &= ~(0xfu << 11u);
        curr |= (value & 0xfu) << 11u;

        CTRL_TRIG = curr;
    }

    inline DMA_TREQ_SEL get_CTRL_TRIG_TREQ_SEL()
    {
        return DMA_TREQ_SEL((CTRL_TRIG >> 15u) & 0b111111u);
    }

    inline void set_CTRL_TRIG_TREQ_SEL(DMA_TREQ_SEL value)
    {
        uint32_t curr = CTRL_TRIG;

        curr &= ~(0b111111u << 15u);
        curr |= (std::to_underlying(value) & 0b111111u) << 15u;

        CTRL_TRIG = curr;
    }

    inline bool get_CTRL_TRIG_IRQ_QUIET()
    {
        return CTRL_TRIG & (1u << 21u);
    }

    inline void set_CTRL_TRIG_IRQ_QUIET()
    {
        CTRL_TRIG |= 1u << 21u;
    }

    inline void clear_CTRL_TRIG_IRQ_QUIET()
    {
        CTRL_TRIG &= ~(1u << 21u);
    }

    inline void toggle_CTRL_TRIG_IRQ_QUIET()
    {
        CTRL_TRIG ^= 1u << 21u;
    }

    inline bool get_CTRL_TRIG_BSWAP()
    {
        return CTRL_TRIG & (1u << 22u);
    }

    inline void set_CTRL_TRIG_BSWAP()
    {
        CTRL_TRIG |= 1u << 22u;
    }

    inline void clear_CTRL_TRIG_BSWAP()
    {
        CTRL_TRIG &= ~(1u << 22u);
    }

    inline void toggle_CTRL_TRIG_BSWAP()
    {
        CTRL_TRIG ^= 1u << 22u;
    }

    inline bool get_CTRL_TRIG_SNIFF_EN()
    {
        return CTRL_TRIG & (1u << 23u);
    }

    inline void set_CTRL_TRIG_SNIFF_EN()
    {
        CTRL_TRIG |= 1u << 23u;
    }

    inline void clear_CTRL_TRIG_SNIFF_EN()
    {
        CTRL_TRIG &= ~(1u << 23u);
    }

    inline void toggle_CTRL_TRIG_SNIFF_EN()
    {
        CTRL_TRIG ^= 1u << 23u;
    }

    inline bool get_CTRL_TRIG_BUSY()
    {
        return CTRL_TRIG & (1u << 24u);
    }

    inline bool get_CTRL_TRIG_WRITE_ERROR()
    {
        return CTRL_TRIG & (1u << 29u);
    }

    inline void set_CTRL_TRIG_WRITE_ERROR()
    {
        CTRL_TRIG |= 1u << 29u;
    }

    inline void clear_CTRL_TRIG_WRITE_ERROR()
    {
        CTRL_TRIG &= ~(1u << 29u);
    }

    inline void toggle_CTRL_TRIG_WRITE_ERROR()
    {
        CTRL_TRIG ^= 1u << 29u;
    }

    inline bool get_CTRL_TRIG_READ_ERROR()
    {
        return CTRL_TRIG & (1u << 30u);
    }

    inline void set_CTRL_TRIG_READ_ERROR()
    {
        CTRL_TRIG |= 1u << 30u;
    }

    inline void clear_CTRL_TRIG_READ_ERROR()
    {
        CTRL_TRIG &= ~(1u << 30u);
    }

    inline void toggle_CTRL_TRIG_READ_ERROR()
    {
        CTRL_TRIG ^= 1u << 30u;
    }

    inline bool get_CTRL_TRIG_AHB_ERROR()
    {
        return CTRL_TRIG & (1u << 31u);
    }

    inline void get_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY,
                              DMA_DATA_SIZE &DATA_SIZE, bool &INCR_READ,
                              bool &INCR_WRITE, DMA_RING_SIZE &RING_SIZE,
                              bool &RING_SEL, uint8_t &CHAIN_TO,
                              DMA_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET,
                              bool &BSWAP, bool &SNIFF_EN, bool &BUSY,
                              bool &WRITE_ERROR, bool &READ_ERROR,
                              bool &AHB_ERROR)
    {
        uint32_t curr = CTRL_TRIG;

        EN = curr & 1u;
        HIGH_PRIORITY = curr & (1u << 1u);
        DATA_SIZE = DMA_DATA_SIZE((curr >> 2u) & 0b11u);
        INCR_READ = curr & (1u << 4u);
        INCR_WRITE = curr & (1u << 5u);
        RING_SIZE = DMA_RING_SIZE((curr >> 6u) & 0xfu);
        RING_SEL = curr & (1u << 10u);
        CHAIN_TO = (curr >> 11u) & 0xfu;
        TREQ_SEL = DMA_TREQ_SEL((curr >> 15u) & 0b111111u);
        IRQ_QUIET = curr & (1u << 21u);
        BSWAP = curr & (1u << 22u);
        SNIFF_EN = curr & (1u << 23u);
        BUSY = curr & (1u << 24u);
        WRITE_ERROR = curr & (1u << 29u);
        READ_ERROR = curr & (1u << 30u);
        AHB_ERROR = curr & (1u << 31u);
    }

    inline void set_CTRL_TRIG(bool EN, bool HIGH_PRIORITY,
                              DMA_DATA_SIZE DATA_SIZE, bool INCR_READ,
                              bool INCR_WRITE, DMA_RING_SIZE RING_SIZE,
                              bool RING_SEL, uint8_t CHAIN_TO,
                              DMA_TREQ_SEL TREQ_SEL, bool IRQ_QUIET,
                              bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR,
                              bool READ_ERROR)
    {
        uint32_t curr = CTRL_TRIG;

        curr &= ~(0b1u);
        curr |= (EN & 0b1u);
        curr &= ~(0b1u << 1u);
        curr |= (HIGH_PRIORITY & 0b1u) << 1u;
        curr &= ~(0b11u << 2u);
        curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
        curr &= ~(0b1u << 4u);
        curr |= (INCR_READ & 0b1u) << 4u;
        curr &= ~(0b1u << 5u);
        curr |= (INCR_WRITE & 0b1u) << 5u;
        curr &= ~(0xfu << 6u);
        curr |= (std::to_underlying(RING_SIZE) & 0xfu) << 6u;
        curr &= ~(0b1u << 10u);
        curr |= (RING_SEL & 0b1u) << 10u;
        curr &= ~(0xfu << 11u);
        curr |= (CHAIN_TO & 0xfu) << 11u;
        curr &= ~(0b111111u << 15u);
        curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
        curr &= ~(0b1u << 21u);
        curr |= (IRQ_QUIET & 0b1u) << 21u;
        curr &= ~(0b1u << 22u);
        curr |= (BSWAP & 0b1u) << 22u;
        curr &= ~(0b1u << 23u);
        curr |= (SNIFF_EN & 0b1u) << 23u;
        curr &= ~(0b1u << 29u);
        curr |= (WRITE_ERROR & 0b1u) << 29u;
        curr &= ~(0b1u << 30u);
        curr |= (READ_ERROR & 0b1u) << 30u;

        CTRL_TRIG = curr;
    }

    inline bool get_AL1_CTRL_EN()
    {
        return AL1_CTRL & 1u;
    }

    inline void set_AL1_CTRL_EN()
    {
        AL1_CTRL |= 1u;
    }

    inline void clear_AL1_CTRL_EN()
    {
        AL1_CTRL &= ~(1u);
    }

    inline void toggle_AL1_CTRL_EN()
    {
        AL1_CTRL ^= 1u;
    }

    inline bool get_AL1_CTRL_HIGH_PRIORITY()
    {
        return AL1_CTRL & (1u << 1u);
    }

    inline void set_AL1_CTRL_HIGH_PRIORITY()
    {
        AL1_CTRL |= 1u << 1u;
    }

    inline void clear_AL1_CTRL_HIGH_PRIORITY()
    {
        AL1_CTRL &= ~(1u << 1u);
    }

    inline void toggle_AL1_CTRL_HIGH_PRIORITY()
    {
        AL1_CTRL ^= 1u << 1u;
    }

    inline DMA_DATA_SIZE get_AL1_CTRL_DATA_SIZE()
    {
        return DMA_DATA_SIZE((AL1_CTRL >> 2u) & 0b11u);
    }

    inline void set_AL1_CTRL_DATA_SIZE(DMA_DATA_SIZE value)
    {
        uint32_t curr = AL1_CTRL;

        curr &= ~(0b11u << 2u);
        curr |= (std::to_underlying(value) & 0b11u) << 2u;

        AL1_CTRL = curr;
    }

    inline bool get_AL1_CTRL_INCR_READ()
    {
        return AL1_CTRL & (1u << 4u);
    }

    inline void set_AL1_CTRL_INCR_READ()
    {
        AL1_CTRL |= 1u << 4u;
    }

    inline void clear_AL1_CTRL_INCR_READ()
    {
        AL1_CTRL &= ~(1u << 4u);
    }

    inline void toggle_AL1_CTRL_INCR_READ()
    {
        AL1_CTRL ^= 1u << 4u;
    }

    inline bool get_AL1_CTRL_INCR_WRITE()
    {
        return AL1_CTRL & (1u << 5u);
    }

    inline void set_AL1_CTRL_INCR_WRITE()
    {
        AL1_CTRL |= 1u << 5u;
    }

    inline void clear_AL1_CTRL_INCR_WRITE()
    {
        AL1_CTRL &= ~(1u << 5u);
    }

    inline void toggle_AL1_CTRL_INCR_WRITE()
    {
        AL1_CTRL ^= 1u << 5u;
    }

    inline DMA_RING_SIZE get_AL1_CTRL_RING_SIZE()
    {
        return DMA_RING_SIZE((AL1_CTRL >> 6u) & 0xfu);
    }

    inline void set_AL1_CTRL_RING_SIZE(DMA_RING_SIZE value)
    {
        uint32_t curr = AL1_CTRL;

        curr &= ~(0xfu << 6u);
        curr |= (std::to_underlying(value) & 0xfu) << 6u;

        AL1_CTRL = curr;
    }

    inline bool get_AL1_CTRL_RING_SEL()
    {
        return AL1_CTRL & (1u << 10u);
    }

    inline void set_AL1_CTRL_RING_SEL()
    {
        AL1_CTRL |= 1u << 10u;
    }

    inline void clear_AL1_CTRL_RING_SEL()
    {
        AL1_CTRL &= ~(1u << 10u);
    }

    inline void toggle_AL1_CTRL_RING_SEL()
    {
        AL1_CTRL ^= 1u << 10u;
    }

    inline uint8_t get_AL1_CTRL_CHAIN_TO()
    {
        return (AL1_CTRL >> 11u) & 0xfu;
    }

    inline void set_AL1_CTRL_CHAIN_TO(uint8_t value)
    {
        uint32_t curr = AL1_CTRL;

        curr &= ~(0xfu << 11u);
        curr |= (value & 0xfu) << 11u;

        AL1_CTRL = curr;
    }

    inline DMA_TREQ_SEL get_AL1_CTRL_TREQ_SEL()
    {
        return DMA_TREQ_SEL((AL1_CTRL >> 15u) & 0b111111u);
    }

    inline void set_AL1_CTRL_TREQ_SEL(DMA_TREQ_SEL value)
    {
        uint32_t curr = AL1_CTRL;

        curr &= ~(0b111111u << 15u);
        curr |= (std::to_underlying(value) & 0b111111u) << 15u;

        AL1_CTRL = curr;
    }

    inline bool get_AL1_CTRL_IRQ_QUIET()
    {
        return AL1_CTRL & (1u << 21u);
    }

    inline void set_AL1_CTRL_IRQ_QUIET()
    {
        AL1_CTRL |= 1u << 21u;
    }

    inline void clear_AL1_CTRL_IRQ_QUIET()
    {
        AL1_CTRL &= ~(1u << 21u);
    }

    inline void toggle_AL1_CTRL_IRQ_QUIET()
    {
        AL1_CTRL ^= 1u << 21u;
    }

    inline bool get_AL1_CTRL_BSWAP()
    {
        return AL1_CTRL & (1u << 22u);
    }

    inline void set_AL1_CTRL_BSWAP()
    {
        AL1_CTRL |= 1u << 22u;
    }

    inline void clear_AL1_CTRL_BSWAP()
    {
        AL1_CTRL &= ~(1u << 22u);
    }

    inline void toggle_AL1_CTRL_BSWAP()
    {
        AL1_CTRL ^= 1u << 22u;
    }

    inline bool get_AL1_CTRL_SNIFF_EN()
    {
        return AL1_CTRL & (1u << 23u);
    }

    inline void set_AL1_CTRL_SNIFF_EN()
    {
        AL1_CTRL |= 1u << 23u;
    }

    inline void clear_AL1_CTRL_SNIFF_EN()
    {
        AL1_CTRL &= ~(1u << 23u);
    }

    inline void toggle_AL1_CTRL_SNIFF_EN()
    {
        AL1_CTRL ^= 1u << 23u;
    }

    inline bool get_AL1_CTRL_BUSY()
    {
        return AL1_CTRL & (1u << 24u);
    }

    inline bool get_AL1_CTRL_WRITE_ERROR()
    {
        return AL1_CTRL & (1u << 29u);
    }

    inline void set_AL1_CTRL_WRITE_ERROR()
    {
        AL1_CTRL |= 1u << 29u;
    }

    inline void clear_AL1_CTRL_WRITE_ERROR()
    {
        AL1_CTRL &= ~(1u << 29u);
    }

    inline void toggle_AL1_CTRL_WRITE_ERROR()
    {
        AL1_CTRL ^= 1u << 29u;
    }

    inline bool get_AL1_CTRL_READ_ERROR()
    {
        return AL1_CTRL & (1u << 30u);
    }

    inline void set_AL1_CTRL_READ_ERROR()
    {
        AL1_CTRL |= 1u << 30u;
    }

    inline void clear_AL1_CTRL_READ_ERROR()
    {
        AL1_CTRL &= ~(1u << 30u);
    }

    inline void toggle_AL1_CTRL_READ_ERROR()
    {
        AL1_CTRL ^= 1u << 30u;
    }

    inline bool get_AL1_CTRL_AHB_ERROR()
    {
        return AL1_CTRL & (1u << 31u);
    }

    inline void get_AL1_CTRL(bool &EN, bool &HIGH_PRIORITY,
                             DMA_DATA_SIZE &DATA_SIZE, bool &INCR_READ,
                             bool &INCR_WRITE, DMA_RING_SIZE &RING_SIZE,
                             bool &RING_SEL, uint8_t &CHAIN_TO,
                             DMA_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET,
                             bool &BSWAP, bool &SNIFF_EN, bool &BUSY,
                             bool &WRITE_ERROR, bool &READ_ERROR,
                             bool &AHB_ERROR)
    {
        uint32_t curr = AL1_CTRL;

        EN = curr & 1u;
        HIGH_PRIORITY = curr & (1u << 1u);
        DATA_SIZE = DMA_DATA_SIZE((curr >> 2u) & 0b11u);
        INCR_READ = curr & (1u << 4u);
        INCR_WRITE = curr & (1u << 5u);
        RING_SIZE = DMA_RING_SIZE((curr >> 6u) & 0xfu);
        RING_SEL = curr & (1u << 10u);
        CHAIN_TO = (curr >> 11u) & 0xfu;
        TREQ_SEL = DMA_TREQ_SEL((curr >> 15u) & 0b111111u);
        IRQ_QUIET = curr & (1u << 21u);
        BSWAP = curr & (1u << 22u);
        SNIFF_EN = curr & (1u << 23u);
        BUSY = curr & (1u << 24u);
        WRITE_ERROR = curr & (1u << 29u);
        READ_ERROR = curr & (1u << 30u);
        AHB_ERROR = curr & (1u << 31u);
    }

    inline void set_AL1_CTRL(bool EN, bool HIGH_PRIORITY,
                             DMA_DATA_SIZE DATA_SIZE, bool INCR_READ,
                             bool INCR_WRITE, DMA_RING_SIZE RING_SIZE,
                             bool RING_SEL, uint8_t CHAIN_TO,
                             DMA_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP,
                             bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR)
    {
        uint32_t curr = AL1_CTRL;

        curr &= ~(0b1u);
        curr |= (EN & 0b1u);
        curr &= ~(0b1u << 1u);
        curr |= (HIGH_PRIORITY & 0b1u) << 1u;
        curr &= ~(0b11u << 2u);
        curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
        curr &= ~(0b1u << 4u);
        curr |= (INCR_READ & 0b1u) << 4u;
        curr &= ~(0b1u << 5u);
        curr |= (INCR_WRITE & 0b1u) << 5u;
        curr &= ~(0xfu << 6u);
        curr |= (std::to_underlying(RING_SIZE) & 0xfu) << 6u;
        curr &= ~(0b1u << 10u);
        curr |= (RING_SEL & 0b1u) << 10u;
        curr &= ~(0xfu << 11u);
        curr |= (CHAIN_TO & 0xfu) << 11u;
        curr &= ~(0b111111u << 15u);
        curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
        curr &= ~(0b1u << 21u);
        curr |= (IRQ_QUIET & 0b1u) << 21u;
        curr &= ~(0b1u << 22u);
        curr |= (BSWAP & 0b1u) << 22u;
        curr &= ~(0b1u << 23u);
        curr |= (SNIFF_EN & 0b1u) << 23u;
        curr &= ~(0b1u << 29u);
        curr |= (WRITE_ERROR & 0b1u) << 29u;
        curr &= ~(0b1u << 30u);
        curr |= (READ_ERROR & 0b1u) << 30u;

        AL1_CTRL = curr;
    }

    inline bool get_AL2_CTRL_EN()
    {
        return AL2_CTRL & 1u;
    }

    inline void set_AL2_CTRL_EN()
    {
        AL2_CTRL |= 1u;
    }

    inline void clear_AL2_CTRL_EN()
    {
        AL2_CTRL &= ~(1u);
    }

    inline void toggle_AL2_CTRL_EN()
    {
        AL2_CTRL ^= 1u;
    }

    inline bool get_AL2_CTRL_HIGH_PRIORITY()
    {
        return AL2_CTRL & (1u << 1u);
    }

    inline void set_AL2_CTRL_HIGH_PRIORITY()
    {
        AL2_CTRL |= 1u << 1u;
    }

    inline void clear_AL2_CTRL_HIGH_PRIORITY()
    {
        AL2_CTRL &= ~(1u << 1u);
    }

    inline void toggle_AL2_CTRL_HIGH_PRIORITY()
    {
        AL2_CTRL ^= 1u << 1u;
    }

    inline DMA_DATA_SIZE get_AL2_CTRL_DATA_SIZE()
    {
        return DMA_DATA_SIZE((AL2_CTRL >> 2u) & 0b11u);
    }

    inline void set_AL2_CTRL_DATA_SIZE(DMA_DATA_SIZE value)
    {
        uint32_t curr = AL2_CTRL;

        curr &= ~(0b11u << 2u);
        curr |= (std::to_underlying(value) & 0b11u) << 2u;

        AL2_CTRL = curr;
    }

    inline bool get_AL2_CTRL_INCR_READ()
    {
        return AL2_CTRL & (1u << 4u);
    }

    inline void set_AL2_CTRL_INCR_READ()
    {
        AL2_CTRL |= 1u << 4u;
    }

    inline void clear_AL2_CTRL_INCR_READ()
    {
        AL2_CTRL &= ~(1u << 4u);
    }

    inline void toggle_AL2_CTRL_INCR_READ()
    {
        AL2_CTRL ^= 1u << 4u;
    }

    inline bool get_AL2_CTRL_INCR_WRITE()
    {
        return AL2_CTRL & (1u << 5u);
    }

    inline void set_AL2_CTRL_INCR_WRITE()
    {
        AL2_CTRL |= 1u << 5u;
    }

    inline void clear_AL2_CTRL_INCR_WRITE()
    {
        AL2_CTRL &= ~(1u << 5u);
    }

    inline void toggle_AL2_CTRL_INCR_WRITE()
    {
        AL2_CTRL ^= 1u << 5u;
    }

    inline DMA_RING_SIZE get_AL2_CTRL_RING_SIZE()
    {
        return DMA_RING_SIZE((AL2_CTRL >> 6u) & 0xfu);
    }

    inline void set_AL2_CTRL_RING_SIZE(DMA_RING_SIZE value)
    {
        uint32_t curr = AL2_CTRL;

        curr &= ~(0xfu << 6u);
        curr |= (std::to_underlying(value) & 0xfu) << 6u;

        AL2_CTRL = curr;
    }

    inline bool get_AL2_CTRL_RING_SEL()
    {
        return AL2_CTRL & (1u << 10u);
    }

    inline void set_AL2_CTRL_RING_SEL()
    {
        AL2_CTRL |= 1u << 10u;
    }

    inline void clear_AL2_CTRL_RING_SEL()
    {
        AL2_CTRL &= ~(1u << 10u);
    }

    inline void toggle_AL2_CTRL_RING_SEL()
    {
        AL2_CTRL ^= 1u << 10u;
    }

    inline uint8_t get_AL2_CTRL_CHAIN_TO()
    {
        return (AL2_CTRL >> 11u) & 0xfu;
    }

    inline void set_AL2_CTRL_CHAIN_TO(uint8_t value)
    {
        uint32_t curr = AL2_CTRL;

        curr &= ~(0xfu << 11u);
        curr |= (value & 0xfu) << 11u;

        AL2_CTRL = curr;
    }

    inline DMA_TREQ_SEL get_AL2_CTRL_TREQ_SEL()
    {
        return DMA_TREQ_SEL((AL2_CTRL >> 15u) & 0b111111u);
    }

    inline void set_AL2_CTRL_TREQ_SEL(DMA_TREQ_SEL value)
    {
        uint32_t curr = AL2_CTRL;

        curr &= ~(0b111111u << 15u);
        curr |= (std::to_underlying(value) & 0b111111u) << 15u;

        AL2_CTRL = curr;
    }

    inline bool get_AL2_CTRL_IRQ_QUIET()
    {
        return AL2_CTRL & (1u << 21u);
    }

    inline void set_AL2_CTRL_IRQ_QUIET()
    {
        AL2_CTRL |= 1u << 21u;
    }

    inline void clear_AL2_CTRL_IRQ_QUIET()
    {
        AL2_CTRL &= ~(1u << 21u);
    }

    inline void toggle_AL2_CTRL_IRQ_QUIET()
    {
        AL2_CTRL ^= 1u << 21u;
    }

    inline bool get_AL2_CTRL_BSWAP()
    {
        return AL2_CTRL & (1u << 22u);
    }

    inline void set_AL2_CTRL_BSWAP()
    {
        AL2_CTRL |= 1u << 22u;
    }

    inline void clear_AL2_CTRL_BSWAP()
    {
        AL2_CTRL &= ~(1u << 22u);
    }

    inline void toggle_AL2_CTRL_BSWAP()
    {
        AL2_CTRL ^= 1u << 22u;
    }

    inline bool get_AL2_CTRL_SNIFF_EN()
    {
        return AL2_CTRL & (1u << 23u);
    }

    inline void set_AL2_CTRL_SNIFF_EN()
    {
        AL2_CTRL |= 1u << 23u;
    }

    inline void clear_AL2_CTRL_SNIFF_EN()
    {
        AL2_CTRL &= ~(1u << 23u);
    }

    inline void toggle_AL2_CTRL_SNIFF_EN()
    {
        AL2_CTRL ^= 1u << 23u;
    }

    inline bool get_AL2_CTRL_BUSY()
    {
        return AL2_CTRL & (1u << 24u);
    }

    inline bool get_AL2_CTRL_WRITE_ERROR()
    {
        return AL2_CTRL & (1u << 29u);
    }

    inline void set_AL2_CTRL_WRITE_ERROR()
    {
        AL2_CTRL |= 1u << 29u;
    }

    inline void clear_AL2_CTRL_WRITE_ERROR()
    {
        AL2_CTRL &= ~(1u << 29u);
    }

    inline void toggle_AL2_CTRL_WRITE_ERROR()
    {
        AL2_CTRL ^= 1u << 29u;
    }

    inline bool get_AL2_CTRL_READ_ERROR()
    {
        return AL2_CTRL & (1u << 30u);
    }

    inline void set_AL2_CTRL_READ_ERROR()
    {
        AL2_CTRL |= 1u << 30u;
    }

    inline void clear_AL2_CTRL_READ_ERROR()
    {
        AL2_CTRL &= ~(1u << 30u);
    }

    inline void toggle_AL2_CTRL_READ_ERROR()
    {
        AL2_CTRL ^= 1u << 30u;
    }

    inline bool get_AL2_CTRL_AHB_ERROR()
    {
        return AL2_CTRL & (1u << 31u);
    }

    inline void get_AL2_CTRL(bool &EN, bool &HIGH_PRIORITY,
                             DMA_DATA_SIZE &DATA_SIZE, bool &INCR_READ,
                             bool &INCR_WRITE, DMA_RING_SIZE &RING_SIZE,
                             bool &RING_SEL, uint8_t &CHAIN_TO,
                             DMA_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET,
                             bool &BSWAP, bool &SNIFF_EN, bool &BUSY,
                             bool &WRITE_ERROR, bool &READ_ERROR,
                             bool &AHB_ERROR)
    {
        uint32_t curr = AL2_CTRL;

        EN = curr & 1u;
        HIGH_PRIORITY = curr & (1u << 1u);
        DATA_SIZE = DMA_DATA_SIZE((curr >> 2u) & 0b11u);
        INCR_READ = curr & (1u << 4u);
        INCR_WRITE = curr & (1u << 5u);
        RING_SIZE = DMA_RING_SIZE((curr >> 6u) & 0xfu);
        RING_SEL = curr & (1u << 10u);
        CHAIN_TO = (curr >> 11u) & 0xfu;
        TREQ_SEL = DMA_TREQ_SEL((curr >> 15u) & 0b111111u);
        IRQ_QUIET = curr & (1u << 21u);
        BSWAP = curr & (1u << 22u);
        SNIFF_EN = curr & (1u << 23u);
        BUSY = curr & (1u << 24u);
        WRITE_ERROR = curr & (1u << 29u);
        READ_ERROR = curr & (1u << 30u);
        AHB_ERROR = curr & (1u << 31u);
    }

    inline void set_AL2_CTRL(bool EN, bool HIGH_PRIORITY,
                             DMA_DATA_SIZE DATA_SIZE, bool INCR_READ,
                             bool INCR_WRITE, DMA_RING_SIZE RING_SIZE,
                             bool RING_SEL, uint8_t CHAIN_TO,
                             DMA_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP,
                             bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR)
    {
        uint32_t curr = AL2_CTRL;

        curr &= ~(0b1u);
        curr |= (EN & 0b1u);
        curr &= ~(0b1u << 1u);
        curr |= (HIGH_PRIORITY & 0b1u) << 1u;
        curr &= ~(0b11u << 2u);
        curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
        curr &= ~(0b1u << 4u);
        curr |= (INCR_READ & 0b1u) << 4u;
        curr &= ~(0b1u << 5u);
        curr |= (INCR_WRITE & 0b1u) << 5u;
        curr &= ~(0xfu << 6u);
        curr |= (std::to_underlying(RING_SIZE) & 0xfu) << 6u;
        curr &= ~(0b1u << 10u);
        curr |= (RING_SEL & 0b1u) << 10u;
        curr &= ~(0xfu << 11u);
        curr |= (CHAIN_TO & 0xfu) << 11u;
        curr &= ~(0b111111u << 15u);
        curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
        curr &= ~(0b1u << 21u);
        curr |= (IRQ_QUIET & 0b1u) << 21u;
        curr &= ~(0b1u << 22u);
        curr |= (BSWAP & 0b1u) << 22u;
        curr &= ~(0b1u << 23u);
        curr |= (SNIFF_EN & 0b1u) << 23u;
        curr &= ~(0b1u << 29u);
        curr |= (WRITE_ERROR & 0b1u) << 29u;
        curr &= ~(0b1u << 30u);
        curr |= (READ_ERROR & 0b1u) << 30u;

        AL2_CTRL = curr;
    }

    inline bool get_AL3_CTRL_EN()
    {
        return AL3_CTRL & 1u;
    }

    inline void set_AL3_CTRL_EN()
    {
        AL3_CTRL |= 1u;
    }

    inline void clear_AL3_CTRL_EN()
    {
        AL3_CTRL &= ~(1u);
    }

    inline void toggle_AL3_CTRL_EN()
    {
        AL3_CTRL ^= 1u;
    }

    inline bool get_AL3_CTRL_HIGH_PRIORITY()
    {
        return AL3_CTRL & (1u << 1u);
    }

    inline void set_AL3_CTRL_HIGH_PRIORITY()
    {
        AL3_CTRL |= 1u << 1u;
    }

    inline void clear_AL3_CTRL_HIGH_PRIORITY()
    {
        AL3_CTRL &= ~(1u << 1u);
    }

    inline void toggle_AL3_CTRL_HIGH_PRIORITY()
    {
        AL3_CTRL ^= 1u << 1u;
    }

    inline DMA_DATA_SIZE get_AL3_CTRL_DATA_SIZE()
    {
        return DMA_DATA_SIZE((AL3_CTRL >> 2u) & 0b11u);
    }

    inline void set_AL3_CTRL_DATA_SIZE(DMA_DATA_SIZE value)
    {
        uint32_t curr = AL3_CTRL;

        curr &= ~(0b11u << 2u);
        curr |= (std::to_underlying(value) & 0b11u) << 2u;

        AL3_CTRL = curr;
    }

    inline bool get_AL3_CTRL_INCR_READ()
    {
        return AL3_CTRL & (1u << 4u);
    }

    inline void set_AL3_CTRL_INCR_READ()
    {
        AL3_CTRL |= 1u << 4u;
    }

    inline void clear_AL3_CTRL_INCR_READ()
    {
        AL3_CTRL &= ~(1u << 4u);
    }

    inline void toggle_AL3_CTRL_INCR_READ()
    {
        AL3_CTRL ^= 1u << 4u;
    }

    inline bool get_AL3_CTRL_INCR_WRITE()
    {
        return AL3_CTRL & (1u << 5u);
    }

    inline void set_AL3_CTRL_INCR_WRITE()
    {
        AL3_CTRL |= 1u << 5u;
    }

    inline void clear_AL3_CTRL_INCR_WRITE()
    {
        AL3_CTRL &= ~(1u << 5u);
    }

    inline void toggle_AL3_CTRL_INCR_WRITE()
    {
        AL3_CTRL ^= 1u << 5u;
    }

    inline DMA_RING_SIZE get_AL3_CTRL_RING_SIZE()
    {
        return DMA_RING_SIZE((AL3_CTRL >> 6u) & 0xfu);
    }

    inline void set_AL3_CTRL_RING_SIZE(DMA_RING_SIZE value)
    {
        uint32_t curr = AL3_CTRL;

        curr &= ~(0xfu << 6u);
        curr |= (std::to_underlying(value) & 0xfu) << 6u;

        AL3_CTRL = curr;
    }

    inline bool get_AL3_CTRL_RING_SEL()
    {
        return AL3_CTRL & (1u << 10u);
    }

    inline void set_AL3_CTRL_RING_SEL()
    {
        AL3_CTRL |= 1u << 10u;
    }

    inline void clear_AL3_CTRL_RING_SEL()
    {
        AL3_CTRL &= ~(1u << 10u);
    }

    inline void toggle_AL3_CTRL_RING_SEL()
    {
        AL3_CTRL ^= 1u << 10u;
    }

    inline uint8_t get_AL3_CTRL_CHAIN_TO()
    {
        return (AL3_CTRL >> 11u) & 0xfu;
    }

    inline void set_AL3_CTRL_CHAIN_TO(uint8_t value)
    {
        uint32_t curr = AL3_CTRL;

        curr &= ~(0xfu << 11u);
        curr |= (value & 0xfu) << 11u;

        AL3_CTRL = curr;
    }

    inline DMA_TREQ_SEL get_AL3_CTRL_TREQ_SEL()
    {
        return DMA_TREQ_SEL((AL3_CTRL >> 15u) & 0b111111u);
    }

    inline void set_AL3_CTRL_TREQ_SEL(DMA_TREQ_SEL value)
    {
        uint32_t curr = AL3_CTRL;

        curr &= ~(0b111111u << 15u);
        curr |= (std::to_underlying(value) & 0b111111u) << 15u;

        AL3_CTRL = curr;
    }

    inline bool get_AL3_CTRL_IRQ_QUIET()
    {
        return AL3_CTRL & (1u << 21u);
    }

    inline void set_AL3_CTRL_IRQ_QUIET()
    {
        AL3_CTRL |= 1u << 21u;
    }

    inline void clear_AL3_CTRL_IRQ_QUIET()
    {
        AL3_CTRL &= ~(1u << 21u);
    }

    inline void toggle_AL3_CTRL_IRQ_QUIET()
    {
        AL3_CTRL ^= 1u << 21u;
    }

    inline bool get_AL3_CTRL_BSWAP()
    {
        return AL3_CTRL & (1u << 22u);
    }

    inline void set_AL3_CTRL_BSWAP()
    {
        AL3_CTRL |= 1u << 22u;
    }

    inline void clear_AL3_CTRL_BSWAP()
    {
        AL3_CTRL &= ~(1u << 22u);
    }

    inline void toggle_AL3_CTRL_BSWAP()
    {
        AL3_CTRL ^= 1u << 22u;
    }

    inline bool get_AL3_CTRL_SNIFF_EN()
    {
        return AL3_CTRL & (1u << 23u);
    }

    inline void set_AL3_CTRL_SNIFF_EN()
    {
        AL3_CTRL |= 1u << 23u;
    }

    inline void clear_AL3_CTRL_SNIFF_EN()
    {
        AL3_CTRL &= ~(1u << 23u);
    }

    inline void toggle_AL3_CTRL_SNIFF_EN()
    {
        AL3_CTRL ^= 1u << 23u;
    }

    inline bool get_AL3_CTRL_BUSY()
    {
        return AL3_CTRL & (1u << 24u);
    }

    inline bool get_AL3_CTRL_WRITE_ERROR()
    {
        return AL3_CTRL & (1u << 29u);
    }

    inline void set_AL3_CTRL_WRITE_ERROR()
    {
        AL3_CTRL |= 1u << 29u;
    }

    inline void clear_AL3_CTRL_WRITE_ERROR()
    {
        AL3_CTRL &= ~(1u << 29u);
    }

    inline void toggle_AL3_CTRL_WRITE_ERROR()
    {
        AL3_CTRL ^= 1u << 29u;
    }

    inline bool get_AL3_CTRL_READ_ERROR()
    {
        return AL3_CTRL & (1u << 30u);
    }

    inline void set_AL3_CTRL_READ_ERROR()
    {
        AL3_CTRL |= 1u << 30u;
    }

    inline void clear_AL3_CTRL_READ_ERROR()
    {
        AL3_CTRL &= ~(1u << 30u);
    }

    inline void toggle_AL3_CTRL_READ_ERROR()
    {
        AL3_CTRL ^= 1u << 30u;
    }

    inline bool get_AL3_CTRL_AHB_ERROR()
    {
        return AL3_CTRL & (1u << 31u);
    }

    inline void get_AL3_CTRL(bool &EN, bool &HIGH_PRIORITY,
                             DMA_DATA_SIZE &DATA_SIZE, bool &INCR_READ,
                             bool &INCR_WRITE, DMA_RING_SIZE &RING_SIZE,
                             bool &RING_SEL, uint8_t &CHAIN_TO,
                             DMA_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET,
                             bool &BSWAP, bool &SNIFF_EN, bool &BUSY,
                             bool &WRITE_ERROR, bool &READ_ERROR,
                             bool &AHB_ERROR)
    {
        uint32_t curr = AL3_CTRL;

        EN = curr & 1u;
        HIGH_PRIORITY = curr & (1u << 1u);
        DATA_SIZE = DMA_DATA_SIZE((curr >> 2u) & 0b11u);
        INCR_READ = curr & (1u << 4u);
        INCR_WRITE = curr & (1u << 5u);
        RING_SIZE = DMA_RING_SIZE((curr >> 6u) & 0xfu);
        RING_SEL = curr & (1u << 10u);
        CHAIN_TO = (curr >> 11u) & 0xfu;
        TREQ_SEL = DMA_TREQ_SEL((curr >> 15u) & 0b111111u);
        IRQ_QUIET = curr & (1u << 21u);
        BSWAP = curr & (1u << 22u);
        SNIFF_EN = curr & (1u << 23u);
        BUSY = curr & (1u << 24u);
        WRITE_ERROR = curr & (1u << 29u);
        READ_ERROR = curr & (1u << 30u);
        AHB_ERROR = curr & (1u << 31u);
    }

    inline void set_AL3_CTRL(bool EN, bool HIGH_PRIORITY,
                             DMA_DATA_SIZE DATA_SIZE, bool INCR_READ,
                             bool INCR_WRITE, DMA_RING_SIZE RING_SIZE,
                             bool RING_SEL, uint8_t CHAIN_TO,
                             DMA_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP,
                             bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR)
    {
        uint32_t curr = AL3_CTRL;

        curr &= ~(0b1u);
        curr |= (EN & 0b1u);
        curr &= ~(0b1u << 1u);
        curr |= (HIGH_PRIORITY & 0b1u) << 1u;
        curr &= ~(0b11u << 2u);
        curr |= (std::to_underlying(DATA_SIZE) & 0b11u) << 2u;
        curr &= ~(0b1u << 4u);
        curr |= (INCR_READ & 0b1u) << 4u;
        curr &= ~(0b1u << 5u);
        curr |= (INCR_WRITE & 0b1u) << 5u;
        curr &= ~(0xfu << 6u);
        curr |= (std::to_underlying(RING_SIZE) & 0xfu) << 6u;
        curr &= ~(0b1u << 10u);
        curr |= (RING_SEL & 0b1u) << 10u;
        curr &= ~(0xfu << 11u);
        curr |= (CHAIN_TO & 0xfu) << 11u;
        curr &= ~(0b111111u << 15u);
        curr |= (std::to_underlying(TREQ_SEL) & 0b111111u) << 15u;
        curr &= ~(0b1u << 21u);
        curr |= (IRQ_QUIET & 0b1u) << 21u;
        curr &= ~(0b1u << 22u);
        curr |= (BSWAP & 0b1u) << 22u;
        curr &= ~(0b1u << 23u);
        curr |= (SNIFF_EN & 0b1u) << 23u;
        curr &= ~(0b1u << 29u);
        curr |= (WRITE_ERROR & 0b1u) << 29u;
        curr &= ~(0b1u << 30u);
        curr |= (READ_ERROR & 0b1u) << 30u;

        AL3_CTRL = curr;
    }
};

static_assert(sizeof(dma_control) == dma_control::size);
static_assert(ifgen_struct<dma_control>);

}; // namespace RP2040

#endif