Struct dma_control

inline bool get_CTRL_TRIG_EN()#

Get CTRL_TRIG’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_CTRL_TRIG_EN()#

Set CTRL_TRIG’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_CTRL_TRIG_EN()#

Clear CTRL_TRIG’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_CTRL_TRIG_EN()#

Toggle CTRL_TRIG’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_CTRL_TRIG_HIGH_PRIORITY()#

Get CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_CTRL_TRIG_HIGH_PRIORITY()#

Set CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_CTRL_TRIG_HIGH_PRIORITY()#

Clear CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_CTRL_TRIG_HIGH_PRIORITY()#

Toggle CTRL_TRIG’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_DATA_SIZE get_CTRL_TRIG_DATA_SIZE()#

Get CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_CTRL_TRIG_DATA_SIZE(DMA_DATA_SIZE value)#

Set CTRL_TRIG’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_CTRL_TRIG_INCR_READ()#

Get CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline void set_CTRL_TRIG_INCR_READ()#

Set CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_CTRL_TRIG_INCR_READ()#

Clear CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_CTRL_TRIG_INCR_READ()#

Toggle CTRL_TRIG’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_CTRL_TRIG_INCR_WRITE()#

Get CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline void set_CTRL_TRIG_INCR_WRITE()#

Set CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_CTRL_TRIG_INCR_WRITE()#

Clear CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_CTRL_TRIG_INCR_WRITE()#

Toggle CTRL_TRIG’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_RING_SIZE get_CTRL_TRIG_RING_SIZE()#

Get CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_CTRL_TRIG_RING_SIZE(DMA_RING_SIZE value)#

Set CTRL_TRIG’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_CTRL_TRIG_RING_SEL()#

Get CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_CTRL_TRIG_RING_SEL()#

Set CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_CTRL_TRIG_RING_SEL()#

Clear CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_CTRL_TRIG_RING_SEL()#

Toggle CTRL_TRIG’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_CTRL_TRIG_CHAIN_TO()#

Get CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_CTRL_TRIG_CHAIN_TO(uint8_t value)#

Set CTRL_TRIG’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_TREQ_SEL get_CTRL_TRIG_TREQ_SEL()#

Get CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ

inline void set_CTRL_TRIG_TREQ_SEL(DMA_TREQ_SEL value)#

Set CTRL_TRIG’s TREQ_SEL field.

Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_CTRL_TRIG_IRQ_QUIET()#

Get CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_CTRL_TRIG_IRQ_QUIET()#

Set CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_CTRL_TRIG_IRQ_QUIET()#

Clear CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_CTRL_TRIG_IRQ_QUIET()#

Toggle CTRL_TRIG’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_CTRL_TRIG_BSWAP()#

Get CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_CTRL_TRIG_BSWAP()#

Set CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_CTRL_TRIG_BSWAP()#

Clear CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_CTRL_TRIG_BSWAP()#

Toggle CTRL_TRIG’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_CTRL_TRIG_SNIFF_EN()#

Get CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_CTRL_TRIG_SNIFF_EN()#

Set CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_CTRL_TRIG_SNIFF_EN()#

Clear CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_CTRL_TRIG_SNIFF_EN()#

Toggle CTRL_TRIG’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_CTRL_TRIG_BUSY()#

Get CTRL_TRIG’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_CTRL_TRIG_WRITE_ERROR()#

Get CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_CTRL_TRIG_WRITE_ERROR()#

Set CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_CTRL_TRIG_WRITE_ERROR()#

Clear CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_CTRL_TRIG_WRITE_ERROR()#

Toggle CTRL_TRIG’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_CTRL_TRIG_READ_ERROR()#

Get CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_CTRL_TRIG_READ_ERROR()#

Set CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_CTRL_TRIG_READ_ERROR()#

Clear CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_CTRL_TRIG_READ_ERROR()#

Toggle CTRL_TRIG’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_CTRL_TRIG_AHB_ERROR()#

Get CTRL_TRIG’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_CTRL_TRIG(bool &EN, bool &HIGH_PRIORITY, DMA_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR)#

Get all of CTRL_TRIG’s bit fields.

(read-write) DMA Channel Control and Status

inline void set_CTRL_TRIG(bool EN, bool HIGH_PRIORITY, DMA_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR)#

Set all of CTRL_TRIG’s bit fields.

(read-write) DMA Channel Control and Status

inline bool get_AL1_CTRL_EN()#

Get AL1_CTRL’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_AL1_CTRL_EN()#

Set AL1_CTRL’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_AL1_CTRL_EN()#

Clear AL1_CTRL’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_AL1_CTRL_EN()#

Toggle AL1_CTRL’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_AL1_CTRL_HIGH_PRIORITY()#

Get AL1_CTRL’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_AL1_CTRL_HIGH_PRIORITY()#

Set AL1_CTRL’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_AL1_CTRL_HIGH_PRIORITY()#

Clear AL1_CTRL’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_AL1_CTRL_HIGH_PRIORITY()#

Toggle AL1_CTRL’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_DATA_SIZE get_AL1_CTRL_DATA_SIZE()#

Get AL1_CTRL’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_AL1_CTRL_DATA_SIZE(DMA_DATA_SIZE value)#

Set AL1_CTRL’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_AL1_CTRL_INCR_READ()#

Get AL1_CTRL’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline void set_AL1_CTRL_INCR_READ()#

Set AL1_CTRL’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_AL1_CTRL_INCR_READ()#

Clear AL1_CTRL’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_AL1_CTRL_INCR_READ()#

Toggle AL1_CTRL’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_AL1_CTRL_INCR_WRITE()#

Get AL1_CTRL’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline void set_AL1_CTRL_INCR_WRITE()#

Set AL1_CTRL’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_AL1_CTRL_INCR_WRITE()#

Clear AL1_CTRL’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_AL1_CTRL_INCR_WRITE()#

Toggle AL1_CTRL’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_RING_SIZE get_AL1_CTRL_RING_SIZE()#

Get AL1_CTRL’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_AL1_CTRL_RING_SIZE(DMA_RING_SIZE value)#

Set AL1_CTRL’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_AL1_CTRL_RING_SEL()#

Get AL1_CTRL’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_AL1_CTRL_RING_SEL()#

Set AL1_CTRL’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_AL1_CTRL_RING_SEL()#

Clear AL1_CTRL’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_AL1_CTRL_RING_SEL()#

Toggle AL1_CTRL’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_AL1_CTRL_CHAIN_TO()#

Get AL1_CTRL’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_AL1_CTRL_CHAIN_TO(uint8_t value)#

Set AL1_CTRL’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_TREQ_SEL get_AL1_CTRL_TREQ_SEL()#

Get AL1_CTRL’s TREQ_SEL field.

Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ

inline void set_AL1_CTRL_TREQ_SEL(DMA_TREQ_SEL value)#

Set AL1_CTRL’s TREQ_SEL field.

Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_AL1_CTRL_IRQ_QUIET()#

Get AL1_CTRL’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_AL1_CTRL_IRQ_QUIET()#

Set AL1_CTRL’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_AL1_CTRL_IRQ_QUIET()#

Clear AL1_CTRL’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_AL1_CTRL_IRQ_QUIET()#

Toggle AL1_CTRL’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_AL1_CTRL_BSWAP()#

Get AL1_CTRL’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_AL1_CTRL_BSWAP()#

Set AL1_CTRL’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_AL1_CTRL_BSWAP()#

Clear AL1_CTRL’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_AL1_CTRL_BSWAP()#

Toggle AL1_CTRL’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_AL1_CTRL_SNIFF_EN()#

Get AL1_CTRL’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_AL1_CTRL_SNIFF_EN()#

Set AL1_CTRL’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_AL1_CTRL_SNIFF_EN()#

Clear AL1_CTRL’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_AL1_CTRL_SNIFF_EN()#

Toggle AL1_CTRL’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_AL1_CTRL_BUSY()#

Get AL1_CTRL’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_AL1_CTRL_WRITE_ERROR()#

Get AL1_CTRL’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_AL1_CTRL_WRITE_ERROR()#

Set AL1_CTRL’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_AL1_CTRL_WRITE_ERROR()#

Clear AL1_CTRL’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_AL1_CTRL_WRITE_ERROR()#

Toggle AL1_CTRL’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_AL1_CTRL_READ_ERROR()#

Get AL1_CTRL’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_AL1_CTRL_READ_ERROR()#

Set AL1_CTRL’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_AL1_CTRL_READ_ERROR()#

Clear AL1_CTRL’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_AL1_CTRL_READ_ERROR()#

Toggle AL1_CTRL’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_AL1_CTRL_AHB_ERROR()#

Get AL1_CTRL’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_AL1_CTRL(bool &EN, bool &HIGH_PRIORITY, DMA_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR)#

Get all of AL1_CTRL’s bit fields.

(read-write) Alias for channel CTRL register

inline void set_AL1_CTRL(bool EN, bool HIGH_PRIORITY, DMA_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR)#

Set all of AL1_CTRL’s bit fields.

(read-write) Alias for channel CTRL register

inline bool get_AL2_CTRL_EN()#

Get AL2_CTRL’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_AL2_CTRL_EN()#

Set AL2_CTRL’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_AL2_CTRL_EN()#

Clear AL2_CTRL’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_AL2_CTRL_EN()#

Toggle AL2_CTRL’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_AL2_CTRL_HIGH_PRIORITY()#

Get AL2_CTRL’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_AL2_CTRL_HIGH_PRIORITY()#

Set AL2_CTRL’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_AL2_CTRL_HIGH_PRIORITY()#

Clear AL2_CTRL’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_AL2_CTRL_HIGH_PRIORITY()#

Toggle AL2_CTRL’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_DATA_SIZE get_AL2_CTRL_DATA_SIZE()#

Get AL2_CTRL’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_AL2_CTRL_DATA_SIZE(DMA_DATA_SIZE value)#

Set AL2_CTRL’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_AL2_CTRL_INCR_READ()#

Get AL2_CTRL’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline void set_AL2_CTRL_INCR_READ()#

Set AL2_CTRL’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_AL2_CTRL_INCR_READ()#

Clear AL2_CTRL’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_AL2_CTRL_INCR_READ()#

Toggle AL2_CTRL’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_AL2_CTRL_INCR_WRITE()#

Get AL2_CTRL’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline void set_AL2_CTRL_INCR_WRITE()#

Set AL2_CTRL’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_AL2_CTRL_INCR_WRITE()#

Clear AL2_CTRL’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_AL2_CTRL_INCR_WRITE()#

Toggle AL2_CTRL’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_RING_SIZE get_AL2_CTRL_RING_SIZE()#

Get AL2_CTRL’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_AL2_CTRL_RING_SIZE(DMA_RING_SIZE value)#

Set AL2_CTRL’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_AL2_CTRL_RING_SEL()#

Get AL2_CTRL’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_AL2_CTRL_RING_SEL()#

Set AL2_CTRL’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_AL2_CTRL_RING_SEL()#

Clear AL2_CTRL’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_AL2_CTRL_RING_SEL()#

Toggle AL2_CTRL’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_AL2_CTRL_CHAIN_TO()#

Get AL2_CTRL’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_AL2_CTRL_CHAIN_TO(uint8_t value)#

Set AL2_CTRL’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_TREQ_SEL get_AL2_CTRL_TREQ_SEL()#

Get AL2_CTRL’s TREQ_SEL field.

Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ

inline void set_AL2_CTRL_TREQ_SEL(DMA_TREQ_SEL value)#

Set AL2_CTRL’s TREQ_SEL field.

Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_AL2_CTRL_IRQ_QUIET()#

Get AL2_CTRL’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_AL2_CTRL_IRQ_QUIET()#

Set AL2_CTRL’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_AL2_CTRL_IRQ_QUIET()#

Clear AL2_CTRL’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_AL2_CTRL_IRQ_QUIET()#

Toggle AL2_CTRL’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_AL2_CTRL_BSWAP()#

Get AL2_CTRL’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_AL2_CTRL_BSWAP()#

Set AL2_CTRL’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_AL2_CTRL_BSWAP()#

Clear AL2_CTRL’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_AL2_CTRL_BSWAP()#

Toggle AL2_CTRL’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_AL2_CTRL_SNIFF_EN()#

Get AL2_CTRL’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_AL2_CTRL_SNIFF_EN()#

Set AL2_CTRL’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_AL2_CTRL_SNIFF_EN()#

Clear AL2_CTRL’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_AL2_CTRL_SNIFF_EN()#

Toggle AL2_CTRL’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_AL2_CTRL_BUSY()#

Get AL2_CTRL’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_AL2_CTRL_WRITE_ERROR()#

Get AL2_CTRL’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_AL2_CTRL_WRITE_ERROR()#

Set AL2_CTRL’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_AL2_CTRL_WRITE_ERROR()#

Clear AL2_CTRL’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_AL2_CTRL_WRITE_ERROR()#

Toggle AL2_CTRL’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_AL2_CTRL_READ_ERROR()#

Get AL2_CTRL’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_AL2_CTRL_READ_ERROR()#

Set AL2_CTRL’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_AL2_CTRL_READ_ERROR()#

Clear AL2_CTRL’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_AL2_CTRL_READ_ERROR()#

Toggle AL2_CTRL’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_AL2_CTRL_AHB_ERROR()#

Get AL2_CTRL’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_AL2_CTRL(bool &EN, bool &HIGH_PRIORITY, DMA_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR)#

Get all of AL2_CTRL’s bit fields.

(read-write) Alias for channel CTRL register

inline void set_AL2_CTRL(bool EN, bool HIGH_PRIORITY, DMA_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR)#

Set all of AL2_CTRL’s bit fields.

(read-write) Alias for channel CTRL register

inline bool get_AL3_CTRL_EN()#

Get AL3_CTRL’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void set_AL3_CTRL_EN()#

Set AL3_CTRL’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void clear_AL3_CTRL_EN()#

Clear AL3_CTRL’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline void toggle_AL3_CTRL_EN()#

Toggle AL3_CTRL’s EN bit.

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

inline bool get_AL3_CTRL_HIGH_PRIORITY()#

Get AL3_CTRL’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void set_AL3_CTRL_HIGH_PRIORITY()#

Set AL3_CTRL’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void clear_AL3_CTRL_HIGH_PRIORITY()#

Clear AL3_CTRL’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline void toggle_AL3_CTRL_HIGH_PRIORITY()#

Toggle AL3_CTRL’s HIGH_PRIORITY bit.

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

inline DMA_DATA_SIZE get_AL3_CTRL_DATA_SIZE()#

Get AL3_CTRL’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline void set_AL3_CTRL_DATA_SIZE(DMA_DATA_SIZE value)#

Set AL3_CTRL’s DATA_SIZE field.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

inline bool get_AL3_CTRL_INCR_READ()#

Get AL3_CTRL’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline void set_AL3_CTRL_INCR_READ()#

Set AL3_CTRL’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline void clear_AL3_CTRL_INCR_READ()#

Clear AL3_CTRL’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline void toggle_AL3_CTRL_INCR_READ()#

Toggle AL3_CTRL’s INCR_READ bit.

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers.

inline bool get_AL3_CTRL_INCR_WRITE()#

Get AL3_CTRL’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline void set_AL3_CTRL_INCR_WRITE()#

Set AL3_CTRL’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline void clear_AL3_CTRL_INCR_WRITE()#

Clear AL3_CTRL’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline void toggle_AL3_CTRL_INCR_WRITE()#

Toggle AL3_CTRL’s INCR_WRITE bit.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers.

inline DMA_RING_SIZE get_AL3_CTRL_RING_SIZE()#

Get AL3_CTRL’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline void set_AL3_CTRL_RING_SIZE(DMA_RING_SIZE value)#

Set AL3_CTRL’s RING_SIZE field.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

inline bool get_AL3_CTRL_RING_SEL()#

Get AL3_CTRL’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void set_AL3_CTRL_RING_SEL()#

Set AL3_CTRL’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void clear_AL3_CTRL_RING_SEL()#

Clear AL3_CTRL’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline void toggle_AL3_CTRL_RING_SEL()#

Toggle AL3_CTRL’s RING_SEL bit.

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

inline uint8_t get_AL3_CTRL_CHAIN_TO()#

Get AL3_CTRL’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline void set_AL3_CTRL_CHAIN_TO(uint8_t value)#

Set AL3_CTRL’s CHAIN_TO field.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.

inline DMA_TREQ_SEL get_AL3_CTRL_TREQ_SEL()#

Get AL3_CTRL’s TREQ_SEL field.

Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ

inline void set_AL3_CTRL_TREQ_SEL(DMA_TREQ_SEL value)#

Set AL3_CTRL’s TREQ_SEL field.

Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ

inline bool get_AL3_CTRL_IRQ_QUIET()#

Get AL3_CTRL’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void set_AL3_CTRL_IRQ_QUIET()#

Set AL3_CTRL’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void clear_AL3_CTRL_IRQ_QUIET()#

Clear AL3_CTRL’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline void toggle_AL3_CTRL_IRQ_QUIET()#

Toggle AL3_CTRL’s IRQ_QUIET bit.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

inline bool get_AL3_CTRL_BSWAP()#

Get AL3_CTRL’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void set_AL3_CTRL_BSWAP()#

Set AL3_CTRL’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void clear_AL3_CTRL_BSWAP()#

Clear AL3_CTRL’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline void toggle_AL3_CTRL_BSWAP()#

Toggle AL3_CTRL’s BSWAP bit.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

inline bool get_AL3_CTRL_SNIFF_EN()#

Get AL3_CTRL’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline void set_AL3_CTRL_SNIFF_EN()#

Set AL3_CTRL’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline void clear_AL3_CTRL_SNIFF_EN()#

Clear AL3_CTRL’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline void toggle_AL3_CTRL_SNIFF_EN()#

Toggle AL3_CTRL’s SNIFF_EN bit.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis.

inline bool get_AL3_CTRL_BUSY()#

Get AL3_CTRL’s BUSY bit.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

inline bool get_AL3_CTRL_WRITE_ERROR()#

Get AL3_CTRL’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void set_AL3_CTRL_WRITE_ERROR()#

Set AL3_CTRL’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void clear_AL3_CTRL_WRITE_ERROR()#

Clear AL3_CTRL’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline void toggle_AL3_CTRL_WRITE_ERROR()#

Toggle AL3_CTRL’s WRITE_ERROR bit.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

inline bool get_AL3_CTRL_READ_ERROR()#

Get AL3_CTRL’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void set_AL3_CTRL_READ_ERROR()#

Set AL3_CTRL’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void clear_AL3_CTRL_READ_ERROR()#

Clear AL3_CTRL’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline void toggle_AL3_CTRL_READ_ERROR()#

Toggle AL3_CTRL’s READ_ERROR bit.

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

inline bool get_AL3_CTRL_AHB_ERROR()#

Get AL3_CTRL’s AHB_ERROR bit.

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

inline void get_AL3_CTRL(bool &EN, bool &HIGH_PRIORITY, DMA_DATA_SIZE &DATA_SIZE, bool &INCR_READ, bool &INCR_WRITE, DMA_RING_SIZE &RING_SIZE, bool &RING_SEL, uint8_t &CHAIN_TO, DMA_TREQ_SEL &TREQ_SEL, bool &IRQ_QUIET, bool &BSWAP, bool &SNIFF_EN, bool &BUSY, bool &WRITE_ERROR, bool &READ_ERROR, bool &AHB_ERROR)#

Get all of AL3_CTRL’s bit fields.

(read-write) Alias for channel CTRL register

inline void set_AL3_CTRL(bool EN, bool HIGH_PRIORITY, DMA_DATA_SIZE DATA_SIZE, bool INCR_READ, bool INCR_WRITE, DMA_RING_SIZE RING_SIZE, bool RING_SEL, uint8_t CHAIN_TO, DMA_TREQ_SEL TREQ_SEL, bool IRQ_QUIET, bool BSWAP, bool SNIFF_EN, bool WRITE_ERROR, bool READ_ERROR)#

Set all of AL3_CTRL’s bit fields.

(read-write) Alias for channel CTRL register

Contents

Struct dma_control#

Struct Documentation#