vcorelib.graph package

vcorelib.graph package#

Submodules#

vcorelib.graph.abc module#

A module containing abstract base-classes related to graphs.

class vcorelib.graph.abc.AbstractDiGraph(name: str, initialdata: Dict[str, T] = None, graph_attrs: Dict[str, str] = None, node_attrs: Dict[str, str] = None, edge_attrs: Dict[str, str] = None)[source]#

Bases: UserDict, Serializable

A simple, directed-graph interface.

add_edge(src: str, dst: str, src_port: str = None, dst_port: str = None, strict: bool = False, **attrs) → None[source]#: Add an edge between nodes in the graph.

add_parallel(node1: str, node2: str, src_port1: str = None, dst_port1: str = None, src_port2: str = None, dst_port2: str = None, **kwargs) → None[source]#: Add an edge in each direction for two nodes.

add_vertex(label: str, node: T) → T[source]#: Add a vertext to the graph.

handle_node(label: str, node: T = None) → T[source]#: Handle either adding a node as a new vertex or obtaining an existing one.

is_parallel(node1: str, node2: str) → bool[source]#: Determine if parallel edges exist between two nodes.

class vcorelib.graph.abc.AbstractDiGraphNode(graph: V = None, label: str = None, port: Port = None, **attrs)[source]#

Bases: Serializable

A base interface for a directed-graph node.

add_port(label: str, **kwargs) → Port[source]#: Add a port to this graph node.

allocate_port(label: str) → Port[source]#: Allocate a port on this node.

graph(kind: Type[V] = None) → V[source]#: Get the graph that this node belongs to.

incoming(graph_kind: Type[V] = None) → Iterator[T][source]#: Iterate over nodes that have incoming edges.

join_graph(graph: V, label: str) → None[source]#: Attempt to join a graph.

property label: str#: Get this node’s label.

outgoing(graph_kind: Type[V] = None) → Iterator[T][source]#: Iterate over nodes that we have outgoing edges to.

parallel() → Set[T][source]#: Iterate over nodes that this instance shares parallel edges with.

vcorelib.graph.edge module#

A module for defining and working with graph edges.

class vcorelib.graph.edge.GraphEdge(src: str, dst: str, src_port: Port | None = None, dst_port: Port | None = None, attrs: Dict[str, str] | None = None)[source]#

Bases: NamedTuple

A grouping of attributes describing a directed edge in a graph.

attrs: Dict[str, str] | None#: Alias for field number 4

dst: str#: Alias for field number 1

dst_port: Port | None#: Alias for field number 3

src: str#: Alias for field number 0

src_port: Port | None#: Alias for field number 2

to_stream(stream: TextIO, edgeop: str = '->', **_) → None[source]#: Write this object to a text stream.

vcorelib.graph.edge.write_attributes(stream: TextIO, data: Dict[str, str] = None) → None[source]#: A simple attribute writer for Graphviz’s DOT language.

vcorelib.graph.edge.write_node_id(label: str, stream: TextIO, port: Port = None) → None[source]#: Write a node identifier to a stream.

vcorelib.graph.node module#

A module for working with graph nodes.

class vcorelib.graph.node.DiGraphNode(graph: V = None, label: str = None, port: Port = None, **attrs)[source]#

Bases: AbstractDiGraphNode

A base implementation for a directed-graph node.

add_child(label: str, node: T = None, graph_kind: Type[V] = None, **kwargs) → T[source]#: Add an edge between this node (source) and the other node (destination).

add_parallel(label: str, node: T = None, graph_kind: Type[V] = None, **kwargs) → T[source]#: Add a parallel edge between two nodes. This instance is used as ‘node1’.

add_parent(label: str, node: T = None, graph_kind: Type[V] = None, **kwargs) → T[source]#: Add an edge between this node (destination) and the other node (source).

to_stream(stream: TextIO, **kwargs) → None[source]#: Write this object to a text stream.

vcorelib.graph.port module#

A module for working with graph ports.

class vcorelib.graph.port.Port(label: str, kind: PortType = PortType.INOUT, alias: str | None = None, allocated: bool = False)[source]#

Bases: NamedTuple

A simple implementation for generic, input and output ports.

alias: str | None#: Alias for field number 2

allocate() → Port[source]#: Allocate this port.

allocated: bool#: Alias for field number 3

property is_input: bool#: Determine if this is an input port.

property is_output: bool#: Determine if this is an output port.

kind: PortType#: Alias for field number 1

label: str#: Alias for field number 0

class vcorelib.graph.port.PortManager[source]#

Bases: object

An interface for managing input and output ports.

allocate(label: str) → Port[source]#: Allocate a labeled port.

create(label: str, **kwargs) → Port[source]#: Add a new port to this port manager.

inout_labels() → Set[str][source]#: Get inout port labels.

input_labels(exclude_inout: bool = True) → Set[str][source]#: Get input port labels.

label(stream: TextIO) → None[source]#: Create a record label based on the current port configuration.

output_labels(exclude_inout: bool = True) → Set[str][source]#: Get output port labels.

class vcorelib.graph.port.PortType(value, names=None, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]#

Bases: Enum

An enumeration of port types.

INOUT = 3#

INPUT = 1#

OUTPUT = 2#

property is_input: bool#: Determine if this port type is capable of input.

property is_output: bool#: Determine if this port type is capable of output.

Module contents#

A module for implementing graph-like data structures.

See Graphviz’s ‘DOT Language’ here: https://graphviz.org/doc/info/lang.html.

class vcorelib.graph.DiGraph(name: str, initialdata: Dict[str, T] = None, graph_attrs: Dict[str, str] = None, node_attrs: Dict[str, str] = None, edge_attrs: Dict[str, str] = None)[source]#

Bases: AbstractDiGraph

A simple, directed-graph implementation.

to_stream(stream: TextIO, **kwargs) → None[source]#: Write this object to a text stream.

vcorelib.graph.write_indent(indent: int, stream: TextIO, linesep: str = '\n') → None[source]#: Handle indented prefixes for new lines in a text stream.